JP4164452B2 - 情報処理方法及び装置 - Google Patents

情報処理方法及び装置 Download PDF

Info

Publication number
JP4164452B2
JP4164452B2 JP2004025349A JP2004025349A JP4164452B2 JP 4164452 B2 JP4164452 B2 JP 4164452B2 JP 2004025349 A JP2004025349 A JP 2004025349A JP 2004025349 A JP2004025349 A JP 2004025349A JP 4164452 B2 JP4164452 B2 JP 4164452B2
Authority
JP
Japan
Prior art keywords
memory
area
information processing
cache
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004025349A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005216220A (ja
JP2005216220A5 (https=
Inventor
武志 小川
岳生 崎村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP2004025349A priority Critical patent/JP4164452B2/ja
Priority to US11/044,171 priority patent/US7428616B2/en
Publication of JP2005216220A publication Critical patent/JP2005216220A/ja
Publication of JP2005216220A5 publication Critical patent/JP2005216220A5/ja
Application granted granted Critical
Publication of JP4164452B2 publication Critical patent/JP4164452B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
JP2004025349A 2004-02-02 2004-02-02 情報処理方法及び装置 Expired - Fee Related JP4164452B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004025349A JP4164452B2 (ja) 2004-02-02 2004-02-02 情報処理方法及び装置
US11/044,171 US7428616B2 (en) 2004-02-02 2005-01-28 Method and apparatus for appending buffer areas to requested memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004025349A JP4164452B2 (ja) 2004-02-02 2004-02-02 情報処理方法及び装置

Publications (3)

Publication Number Publication Date
JP2005216220A JP2005216220A (ja) 2005-08-11
JP2005216220A5 JP2005216220A5 (https=) 2007-01-18
JP4164452B2 true JP4164452B2 (ja) 2008-10-15

Family

ID=34805797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004025349A Expired - Fee Related JP4164452B2 (ja) 2004-02-02 2004-02-02 情報処理方法及び装置

Country Status (2)

Country Link
US (1) US7428616B2 (https=)
JP (1) JP4164452B2 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102014083B1 (ko) * 2012-12-31 2019-08-27 삼성전자주식회사 단말기의 메모리 관리방법 및 장치
US10747535B1 (en) * 2016-07-11 2020-08-18 Apple Inc. Handling non-cacheable loads in a non-coherent processor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US22857A (en) * 1859-02-08 Improved valve-bung
US5933847A (en) * 1995-09-28 1999-08-03 Canon Kabushiki Kaisha Selecting erase method based on type of power supply for flash EEPROM
US6115799A (en) * 1996-07-19 2000-09-05 Canon Kabushiki Kaisha Information processing apparatus and associated method for managing a memory using a next fit and for reducing a memory fragmentation problem
US6603168B1 (en) * 2000-04-20 2003-08-05 Agere Systems Inc. Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method
US6925546B2 (en) * 2002-12-02 2005-08-02 Wind River Systems, Inc. Memory pool configuration system
CA2426619A1 (en) * 2003-04-25 2004-10-25 Ibm Canada Limited - Ibm Canada Limitee Defensive heap memory management
US20050091459A1 (en) * 2003-10-23 2005-04-28 Nhon Quach Flexible mechanism for enforcing coherency among caching structures
US7257693B2 (en) * 2004-01-15 2007-08-14 Intel Corporation Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system

Also Published As

Publication number Publication date
JP2005216220A (ja) 2005-08-11
US7428616B2 (en) 2008-09-23
US20050172081A1 (en) 2005-08-04

Similar Documents

Publication Publication Date Title
JP5255348B2 (ja) クラッシュダンプ用のメモリアロケーション
US6205521B1 (en) Inclusion map for accelerated cache flush
JP5351046B2 (ja) フラッシュメモリシステムの高速起動を容易にする方法およびシステム
US6526472B2 (en) Access control method, access control apparatus and computer readable memory storing access control program
US5765201A (en) Changing page size in storage media of computer system
US20080235477A1 (en) Coherent data mover
US20100332730A1 (en) Method and system for managing a nand flash memory
JP5063152B2 (ja) 代替ページのプールを使用してｄｍａ書込みページ障害をコンピュータにより管理するための方法、装置、及びコンピュータ・プログラム
US6549995B1 (en) Compressor system memory organization and method for low latency access to uncompressed memory regions
US10331568B2 (en) Locking a cache line for write operations on a bus
US5933848A (en) System for managing the caching of data of a mass storage within a portion of a system memory
JPH1125033A (ja) バスブリッジ
JP3519954B2 (ja) チップイネーブル信号生成回路及びメモリ装置
EP1605360B1 (en) Cache coherency maintenance for DMA, task termination and synchronisation operations
US6490668B2 (en) System and method for dynamically moving checksums to different memory locations
KR100505695B1 (ko) 동적으로 할당 또는 해제되는 버퍼를 가지는 캐쉬 메모리장치, 이를 구비한 디지털 데이터 처리 시스템 및 그 방법
JP5286796B2 (ja) メモリ制御装置
JP2005115561A (ja) フラッシュｒｏｍ制御装置
JP4164452B2 (ja) 情報処理方法及び装置
EP1103898A2 (en) Microprocessor and memory
JP5587539B2 (ja) ローカルメモリデータのコヒーレントなキャッシュ処理
JP3903678B2 (ja) 計算機システムのダンプ処理方法
JP2005346582A (ja) システムｌｓｉ及び画像処理装置
JP4724289B2 (ja) データ処理装置およびデータ処理装置のメモリアクセス制御方法
JPH10133948A (ja) キャッシュメモリ装置

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061129

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061129

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080627

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080707

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080718

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080728

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110801

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4164452

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120801

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120801

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130801

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees