JP2005216220A5 - - Google Patents
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- Publication number
- JP2005216220A5 JP2005216220A5 JP2004025349A JP2004025349A JP2005216220A5 JP 2005216220 A5 JP2005216220 A5 JP 2005216220A5 JP 2004025349 A JP2004025349 A JP 2004025349A JP 2004025349 A JP2004025349 A JP 2004025349A JP 2005216220 A5 JP2005216220 A5 JP 2005216220A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004025349A JP4164452B2 (ja) | 2004-02-02 | 2004-02-02 | 情報処理方法及び装置 |
| US11/044,171 US7428616B2 (en) | 2004-02-02 | 2005-01-28 | Method and apparatus for appending buffer areas to requested memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004025349A JP4164452B2 (ja) | 2004-02-02 | 2004-02-02 | 情報処理方法及び装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005216220A JP2005216220A (ja) | 2005-08-11 |
| JP2005216220A5 true JP2005216220A5 (https=) | 2007-01-18 |
| JP4164452B2 JP4164452B2 (ja) | 2008-10-15 |
Family
ID=34805797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004025349A Expired - Fee Related JP4164452B2 (ja) | 2004-02-02 | 2004-02-02 | 情報処理方法及び装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7428616B2 (https=) |
| JP (1) | JP4164452B2 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102014083B1 (ko) * | 2012-12-31 | 2019-08-27 | 삼성전자주식회사 | 단말기의 메모리 관리방법 및 장치 |
| US10747535B1 (en) * | 2016-07-11 | 2020-08-18 | Apple Inc. | Handling non-cacheable loads in a non-coherent processor |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US22857A (en) * | 1859-02-08 | Improved valve-bung | ||
| US5933847A (en) * | 1995-09-28 | 1999-08-03 | Canon Kabushiki Kaisha | Selecting erase method based on type of power supply for flash EEPROM |
| US6115799A (en) * | 1996-07-19 | 2000-09-05 | Canon Kabushiki Kaisha | Information processing apparatus and associated method for managing a memory using a next fit and for reducing a memory fragmentation problem |
| US6603168B1 (en) * | 2000-04-20 | 2003-08-05 | Agere Systems Inc. | Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method |
| US6925546B2 (en) * | 2002-12-02 | 2005-08-02 | Wind River Systems, Inc. | Memory pool configuration system |
| CA2426619A1 (en) * | 2003-04-25 | 2004-10-25 | Ibm Canada Limited - Ibm Canada Limitee | Defensive heap memory management |
| US20050091459A1 (en) * | 2003-10-23 | 2005-04-28 | Nhon Quach | Flexible mechanism for enforcing coherency among caching structures |
| US7257693B2 (en) * | 2004-01-15 | 2007-08-14 | Intel Corporation | Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system |
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2004
- 2004-02-02 JP JP2004025349A patent/JP4164452B2/ja not_active Expired - Fee Related
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2005
- 2005-01-28 US US11/044,171 patent/US7428616B2/en not_active Expired - Fee Related