JP4146074B2 - Fail analysis device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fail analysis apparatus that displays a measurement result of a fail distribution state of a memory cell of a semiconductor memory.
[0002]
[Prior art]
The semiconductor test apparatus analyzes each memory cell for defects by reading and writing data to and from each memory cell in a semiconductor memory (hereinafter simply referred to as “memory”) as a device under test (DUT). In general, the semiconductor test apparatus compares the data read from the DUT with predetermined expected value data to determine pass / fail, and stores the result in the fail memory. The failure information stored in the failure memory in this manner is collected by a failure analysis apparatus constituted by a workstation or the like and examined for its contents, thereby performing various types of failure analysis on the DUT.
[0003]
For example, the fail analysis apparatus can display a fail distribution state of a large capacity DRAM as a physical map or a logical map by using a predetermined memory device evaluation tool. The physical map is a two-dimensional fail bit map using physical addresses X and Y as coordinates, and is used to confirm the physical arrangement of defective memory cells in the memory. The logical map is a three-dimensional fail bit map that uses the logical addresses X and Y and the I / O number as coordinates. When the logical address Z is used, the logical map may be four-dimensional. This logical map is generated based on the fail information read from the above-described fail memory.
[0004]
[Problems to be solved by the invention]
By the way, it is convenient if the logical maps and physical maps generated by the above-described conventional fail analysis apparatus can be overlapped with each other when comparing the tendency of failure. Such superposition of a plurality of bitmaps is not possible with a conventional fail analysis apparatus, or only simple superposition can be performed under limited restrictions. For example, even if two fail bitmaps can be overlaid, these two fail bitmaps are not associated with each other. It is necessary to change the display magnification for each of the two fail bitmaps. Also, when it is desired to move the display area of the fail bit map, the two fail bit maps do not move in conjunction with each other, so it is necessary to move the display area for each of the two fail bit maps. Further, when superimposing is performed by changing the combination of a plurality of fail bit maps, every time the combination is changed, the data is repeatedly read from all the fail bit maps to be superposed. In addition, when a plurality of fail bit maps are overlapped, it is impossible to change only the overlapping order, so that the order is changed and redrawing is performed. As described above, when fail bit maps are superimposed using a conventional fail analysis apparatus, there is a problem that an operation for making some changes becomes complicated.
[0005]
For example, when two fail bitmaps are compared to confirm how much the fail locations match, it is necessary to perform an operation on the overlapped fail bitmaps. It has been impossible for the analysis apparatus to perform operations between such fail bitmaps.
[0006]
The present invention has been created in view of such a point, and an object thereof is to provide a fail analysis apparatus capable of simplifying operations related to the overlapping of fail bit maps. Another object of the present invention is to provide a fail analysis apparatus capable of performing calculations using a plurality of superimposed bitmaps.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems, the fail analysis apparatus of the present invention generates a plurality of fail bit map images representing test results corresponding to a semiconductor memory when displaying the result of testing the semiconductor memory by the semiconductor test apparatus. A plurality of fail bitmap images, a layer management unit that associates each of the plurality of fail bitmap images with a plurality of layers and associates each layer, and a plurality of layers are associated by the layer management unit. An image superimposing unit that performs a process of superimposing a plurality of fail bit map images and a display unit that displays an image superimposed by the image superimposing unit are provided. Each of the superimposed fail bitmap images corresponds to a plurality of layers, and the layers are associated with each other. Therefore, when changing the content of the display image, for example, the display magnification is changed or the display range is changed. Or the like, the display contents can be changed while maintaining the mutual relationship between the fail bit map images. For this reason, it is not necessary to individually instruct each fail bitmap image and to instruct to change the display magnification, and the operation can be greatly simplified.
[0008]
Further, it is desirable that the layer management means described above manages the display / non-display state of the fail bitmap image for each layer. This eliminates the need to repeat the data reading and drawing process each time the display is erased or redisplayed for each superimposed fail bitmap, thus simplifying the processing and operation. .
[0009]
Further, it is desirable that the layer management means described above sets the contents of the logical operation for each of the plurality of layers by association. Since the content of the logical operation is set when the association between the layers is performed, the logical operation for each fail bitmap can be performed according to the set content.
[0010]
Further, the above-described operation means for instructing the change of the display range of the fail bit map, and a plurality of fail bits corresponding to the plurality of layers associated by the layer management means when the change of the display range is instructed by the operation means It is preferable to further include display range changing means for changing the display range for the map. Thereby, the display range of a plurality of fail bit maps can be changed at the same time by giving a change instruction once by the operation means.
[0011]
In addition, it is desirable that the above-described layer management unit associates each of a plurality of layers including images not related to the test result other than the plurality of fail bitmap images. For example, when an image of a predetermined frame, ruled line, character, or the like is considered, by adding this image to a plurality of superimposed fail bit map images, it is possible to improve the visibility of display contents.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a failure analysis apparatus according to an embodiment to which the present invention is applied will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor test apparatus to which the fail analysis apparatus of the present embodiment is connected. As shown in FIG. 1, the semiconductor test apparatus 100 includes a timing generator 110, a pattern generator 112, a waveform shaper 114, a logical comparator 116, an AFM (address fail memory) 118, a CFM (compact fail memory) 120, a tester. A processing unit 122, a communication control unit 124, and a physical conversion unit 126 are included.
[0013]
The address and data generated by the pattern generator 112 are waveform-shaped by the waveform shaper 114 and input to the DUT 130. The logical comparator 116 compares the data read from the DUT 130 with the expected value output from the pattern generator 112 to determine pass / fail.
[0014]
The AFM 118 stores fail information for each address based on the fail signal output from the logical comparator 116 and the address signal output from the pattern generator 112. All of these series of operations are performed in synchronization with the system clock input from the timing generator 110 to each unit. The fail information stored in the AFM 118 is logical fail bitmap data, and bit data (for example, pass) indicating whether or not each memory cell specified by the X address and Y address for each I / O number. Is stored in “0” and “fail” corresponds to “1”).
[0015]
The CFM 120 stores fail information obtained by reducing the content of the AFM 118. For example, for each I / O number, the X address is divided into n and the Y address is divided into m, and 1-bit data corresponding to each divided area is obtained. Specifically, the value of this 1-bit data is obtained by calculating a logical sum of a plurality of bit data of the AFM 118 corresponding to the corresponding divided area of the X address and the corresponding divided area of the Y address. That is, if even one of the plurality of bit data specified in each divided region includes “1” indicating failure, the corresponding bit data in the CFM 120 is set to “1” indicating failure. When all of the plurality of bit data specified in each divided area is “0” indicating a path, the corresponding bit data in the CFM 120 is set to “0” indicating a path. In the following description, data read from the AFM 118 is referred to as “AFM data” or “detailed logical data”, and data read from the CFM 120 is referred to as “CFM data” or “reduced logical data”.
[0016]
The physical conversion unit 126 generates physical fail bitmap data (hereinafter referred to as “detailed physical data”) by performing a physical conversion process based on the detailed logical data stored in the AFM 118. The physical conversion unit 126 is configured by dedicated hardware, and can execute physical conversion processing at high speed.
[0017]
The tester processing unit 122 controls the entire semiconductor test apparatus 100 in order to execute a predetermined test by executing a test program using an operating system (OS). For example, the tester processing unit 122 performs processing for generating CFM data based on AFM data. The communication control unit 124 transmits / receives various data to / from the fail analysis apparatus 10 connected to the semiconductor test apparatus 100.
[0018]
FIG. 2 is a diagram illustrating a detailed configuration of the failure analysis apparatus 10 according to the present embodiment. As shown in FIG. 2, the failure analysis apparatus 10 includes a communication control unit 12, a logical map storage unit 14, a physical conversion unit 16, a physical map storage unit 18, a reduction processing unit 20, a detailed data acquisition unit 30, and a reduced data acquisition unit. 40, main viewer creation unit 80, logical viewer creation unit 82, physical viewer creation unit 84, layer management unit 86, display range change unit 87, image composition unit 88, display control unit 90, display device 94, operation unit 96, GUI A processing unit 98 is provided.
[0019]
The communication control unit 12 transmits / receives various data to / from the semiconductor test apparatus 100. The logical map storage unit 14 stores detailed logical data and reduced logical data obtained by a test on the DUT 130.
The physical conversion unit 16 generates physical fail bitmap data (hereinafter referred to as “detailed physical data”) by performing physical conversion processing based on the detailed logical data. The physical map storage unit 18 stores detailed physical data obtained by physical conversion processing by the physical conversion unit 16. The reduction processing unit 20 performs a reduction process for generating bitmap data obtained by reducing the contents of the detailed physical data (hereinafter referred to as “reduced physical data”). This reduction process is the same as the process when the CFM data is generated from the AFM data in the semiconductor test apparatus 100 described above.
[0020]
The detailed data acquisition unit 30 acquires detailed logical data and detailed physical data. The fail analysis apparatus 10 according to the present embodiment performs various tests based on the “tester mode” in which various analyzes are performed while acquiring detailed logical data and reduced logical data directly from the semiconductor test apparatus 100, and the detailed logical data once stored. There are two types of analysis modes of “file mode” for performing analysis.
[0021]
Specifically, the detailed logical data is acquired by reading AFM data from the AFM 118 in the semiconductor memory 100 in the tester mode, and is acquired by reading the corresponding data from the logical map storage unit 14 in the file mode. The detailed physical data is acquired by reading the result of the physical conversion processing by the physical conversion unit 126 based on the detailed logical data stored in the AFM 118 in the semiconductor test apparatus 100 in the tester mode, and in the file mode. It is acquired by reading the corresponding data from the physical map storage unit 18.
[0022]
Further, the reduced data acquisition unit 40 acquires reduced logical data and reduced physical data. Specifically, the reduced logical data is acquired by reading CFM data from the CFM 120 in the semiconductor test apparatus 100 in the tester mode, and is read by reading the corresponding data from the logical map storage unit 14 in the file mode. The reduced physical data is acquired by performing reduction processing by the reduction processing unit 20 based on the detailed physical data obtained by physical conversion processing in the tester mode, and the detailed physical data read from the physical map storage unit 18 in the file mode. Acquired by performing a reduction process by the reduction processing unit 20 based on the data.
[0023]
The main viewer creation unit 80 creates drawing data necessary for displaying the main viewer window on the display device 94. The main viewer window includes a list of test results of a plurality of DUTs 130 to be tested.
[0024]
The logical viewer creation unit 82 creates drawing data necessary for displaying the logical viewer window on the display device 94. This logical viewer window includes a logical fail bitmap when a specific DUT 130 and an I / O number are designated.
[0025]
Further, the physical viewer creation unit 84 creates drawing data necessary for displaying the physical viewer window on the display device 94. The physical viewer window includes a physical fail bitmap when a specific DUT 130 is designated. Specific examples of the main viewer window, logical viewer window, and physical viewer window described above will be described later.
[0026]
By the way, in the failure analysis apparatus 10 of the present embodiment, a plurality of logical maps or a plurality of physical maps can be displayed in a superimposed manner, and the concept of a layer is used to superimpose such images. Has been introduced. Specifically, each of the fail bitmap images to be superimposed is associated with each of a plurality of layers, and the association between the layers is performed.
[0027]
The layer management unit 86 manages the setting contents for each layer and the association contents between the layers. The management information is set using a layer window displayed by the layer management unit 86. A specific example of the layer window will be described later.
[0028]
The display range changing unit 87, based on the management information set by the layer management unit 86 when the display range change such as movement or zoom is instructed, all the superimposed fail bits to be displayed. Change the display range of the map. Specifically, based on the management information, the fail bitmaps that are superimposed at the time when the change instruction is given are recognized, and the change of the display range of these fail bitmaps is created by the logical viewer creation unit 82 or the physical viewer. The unit 84 is instructed.
[0029]
Based on the management information set by the layer management unit 86, the image composition unit 88 creates drawing data necessary to display an image in which logical maps or physical maps are superimposed.
The display control unit 90 generates a video signal to be output to the display device 94 based on the drawing data created by each of the main viewer creation unit 80, the logical viewer creation unit 82, the physical viewer creation unit 84, and the image composition unit 88. To do. The display control unit 90 includes a VRAM (video RAM) 92 and stores drawing data of a window to be displayed at the top on the screen.
[0030]
The operation unit 96 is used by the user to input various instructions, and includes a mouse as a pointing device for designating an arbitrary position on the display screen of the display device 94, numeric keys, alphabet keys, or various symbol keys. A keyboard is included. As the pointing device, a device other than a mouse, such as an input tablet or a touch panel, may be used. A GUI (graphical user interface) processing unit 98 is for realizing GUI processing corresponding to the operation state of the operation unit 96. For example, when various commands or buttons included in the main viewer window or the like are clicked using the mouse, the corresponding process is determined and a request for this process is made.
[0031]
The main viewer creation unit 80, logical viewer creation unit 82, and physical viewer creation unit 84 described above serve as fail bitmap creation means, the layer management unit 86 serves as layer management means, the display range change unit 87 serves as display range change means, The combining unit 88 corresponds to the image superimposing unit, the display control unit 90 and the display device 94 correspond to the display unit, and the operation unit 96 and the GUI processing unit 98 correspond to the operation unit.
[0032]
The failure analysis apparatus 10 of this embodiment has such a configuration, and the operation thereof will be described next.
FIG. 3 is a flowchart showing the operation procedure of the fail analysis apparatus. The operation procedure for reflecting various setting contents mainly using the layer window on the display and changing the display range of the superimposed image is shown. It is shown.
[0033]
When the fail analysis apparatus 10 is activated, the layer management unit 86 determines whether a logical viewer window or a physical viewer window is displayed (step 100).
For example, the logical viewer window and the physical viewer window can be displayed by performing a predetermined operation while the main viewer window is displayed. Next, a specific method for starting a logical viewer window or a physical viewer window from the main viewer window will be described.
[0034]
FIG. 4 is a diagram showing a specific example of a main viewer window displayed after the failure analysis apparatus 10 is activated.
DUT data display area (a7)
This is used to display a result image showing each test result of the plurality of DUTs 130 to be tested. A number included in each result image indicated by a rectangle indicates a DUT number, and whether the DUT 130 specified by the DUT number is a pass or a fail is expressed by a color in the rectangle. For example, in the case of a pass (when all the reduced logical data corresponding to this DUT number is a pass), the inside of the rectangle is colored green, and in the case of a failure (at least one of the reduced logical data corresponding to this DUT number is included in the reduced logical data). When there is a failure), the inside of the rectangle is colored red. In the DUT data display area a7 shown in FIG. 4, DUT numbers 1 to 128 are shown. However, when the number of DUTs 130 actually mounted on the semiconductor test apparatus 100 is less than 128, the corresponding DUT 130 is displayed. Numbers in rectangles that do not exist are hidden or shadowed. For example, when a notification (Notify) is sent from the semiconductor test apparatus 100 to the fail analysis apparatus 10, the number of DUTs 130 and the following I / O numbers are read and updated. . Further, when the number of DUTs 130 actually mounted on the semiconductor test apparatus 100 exceeds 128, the pages including the result images of the 128 DUTs 130 are switched and displayed.
[0035]
I / O data display area (a8)
This is used to display a result image indicating a test result for each I / O number for a specific DUT 130 in which a DUT number is designated. A number included in each result image indicated by a rectangle indicates an I / O number, and whether the logical fail bitmap specified by the I / O number is a pass or a fail depends on the color in the rectangle. It is expressed. For example, in the case of a pass (when all the reduced logical data corresponding to this I / O number is a pass), the inside of the rectangle is colored green, and in the case of a failure (reduced logical data corresponding to this I / O number) If there is even one failure, the inside of the rectangle is colored red. In the I / O data display area a8 shown in FIG. 4, I / O numbers from 0 to 143 are shown. However, the maximum value of the I / O number of the DUT 130 actually mounted in the semiconductor test apparatus 100 is shown. If it is smaller than 143, the numbers in the rectangles that do not have corresponding I / O numbers are not displayed or shadowed. If the maximum value of the DUT number exceeds 143, the pages are switched and displayed.
[0036]
Display switching option menu (a9)
This is used to switch the display contents in the above-described DUT data display area a7 or I / O data display area a8. For the DUT data display area a7, display options of “Pass / Fail”, “CFM (All)”, “CFM (16 DUT)”, and “CFM (32 DUT)” are prepared. For the I / O data display area a8, display options of “Pass / Fail”, “CFM (All)”, “CFM (16 or 18 I / O)”, and “CFM (32 or 36 I / O)” are prepared. .
[0037]
“Pass / Fail” is an option for displaying the above-described result image indicating whether the test result is pass or fail. The initial screen of the main viewer window shown in FIG. 4 shows a state in which this display option is selected as a default at startup.
[0038]
Each of “CFM (All)”, “CFM (16 DUT)”, “CFM (32 DUT)”, “CFM (16 or 18 I / O)”, and “CFM (32 or 36 I / O)” corresponds to reduced logical data. This is an option for displaying a reduced image indicating a logical fail bitmap (hereinafter referred to as “reduced logical map”) by the number in parentheses. A specific display example of the reduced image will be described later.
[0039]
“Physical” button (a10)
This is used to instruct the display of a physical viewer window corresponding to a specific DUT 130 to which a DUT number is designated.
FIG. 5 is a diagram showing a specific example of a main viewer window including a list of reduced images showing reduced logical maps. For example, “CFM (16 DUT)” is selected as the display option corresponding to the DUT data display area a7, and “CFM (16 or 18 I / O)” is selected as the display option corresponding to the I / O data display area a8. Has been.
[0040]
In the DUT data display area a7, a rectangular area including a number has the same contents as when “Pass / Fail” is selected as a display option. Whether the DUT 130 designated by this number is a pass or a fail is determined. Corresponds to the result image shown. The rectangular area located at the upper part shows a reduced image showing the contents of the reduced logical map for each DUT 130. Since CFM data (reduced logical data) for each I / O number is read from the CFM 120 in the semiconductor test apparatus 100, the main viewer creation unit 80 performs each of the reduced logical data for all I / O numbers for each DUT 130. The reduced image is generated by calculating the logical sum of the bits.
[0041]
In the I / O data display area a8, a rectangular area including a number has the same contents as when “Pass / Fail” is selected as the display option, and the reduced logical data of this I / O number is passed. It corresponds to the result image indicating whether it is a failure or a failure. A rectangular area located at the upper part shows a reduced image indicating the contents of the reduced logical map for each I / O number.
[0042]
In the example shown in FIG. 5, both the DUT data display area a7 and the I / O data display area a8 are displayed. However, it is possible to increase the number of other displays that can be made non-displayed. it can.
When any of the I / O numbers included in the I / O data display area a8 is designated while the main viewer window is displayed, this indicates that the display of the logical viewer window has been instructed. Become.
[0043]
FIG. 6 is a diagram showing a specific example of the logical viewer window. This window includes a reduced logical map a11 and a logical fail bitmap a12 corresponding to part or all of the reduced logical map a11. The logical fail bitmap a12 is created based on the detailed logical data acquired by the detailed data acquisition unit 30.
[0044]
Further, when the “Physical” button a10 is selected in a state where the main viewer window is displayed, this indicates that the display of the physical viewer window has been instructed.
FIG. 7 is a diagram showing a specific example of the physical viewer window. This window includes a reduced physical map a13 and a logical fail bitmap a14 corresponding to part or all of the reduced physical map a13. The logical fail bitmap a14 is created based on the detailed logical data acquired by the detailed data acquisition unit 30.
[0045]
When the logical viewer window or the physical viewer window is displayed in this way, an affirmative determination is made in the determination in step 100, and then the GUI processing unit 98 determines whether or not the display of the layer window has been instructed. Determine (step 101). For example, a pull-down menu corresponding to “View” in the menu bar displayed at the top of the displayed logical viewer window or physical viewer window includes an item “Layers... It shall be. The GUI processing unit 98 determines whether or not the item “Layers...” Is clicked by the mouse or pointed by using the keyboard to determine in step 101 described above.
[0046]
If the display of the layer window is not instructed, a negative determination is made in the determination of step 101, and then the GUI processing unit 98 determines whether or not an instruction to change the display range of the fail bit map being displayed is instructed. (Step 102). When the change of the display range is not instructed, the process returns to step 100 and the process is repeated.
[0047]
If the display of the layer window is instructed, an affirmative determination is made in the determination of step 101, and then the layer management unit 86 creates an image of the layer window and displays it on the display device 94 (step 103). ).
FIG. 8 is a diagram showing a specific example of the layer window. This window includes a layer display area b1 and a button area b2. When a layer name (such as “Layer0”) included in the layer display area b1 is clicked by operating the mouse, a portion indicating this layer is highlighted and a logical viewer window or a physical viewer window corresponding to this layer is displayed. Operation becomes possible. The fail color designation box c1 is used for designating the color of the fail location when the fail location of the fail bitmap corresponding to this layer is included. If all the fail locations of the respective fail bitmaps to be overlapped have the same color, the fail distribution of each fail bitmap becomes unknown, so that the color of the fail location can be arbitrarily set using this fail color designation box c1. It has become. The check button c2 is for designating a layer to be processed when processing corresponding to various buttons included in the button area b1 is performed. The visible display mark c3 and the invisible mark c4 set the display state of the logical map or physical map corresponding to this layer and indicate the contents of the set display state. Each time the mouse is operated and clicked, the display of these marks is switched.
[0048]
The button area b2 includes a plurality of buttons for instructing various processing contents for a logical viewer window or the like corresponding to each layer. The “New” button is used to instruct the addition of a new layer. The display position of the added layer is the top (frontmost part). The “Del” button is used to delete the selected (highlighted) layer. The “Or” button is used to instruct execution of a logical sum operation using various fail bitmaps corresponding to the selected layer. The “And” button is used to instruct execution of a logical product operation using various fail bitmaps corresponding to the selected layer. The “Xor” button is used to instruct execution of an exclusive OR operation using a fail bitmap corresponding to each of the two layers. When three or more layers are selected, the two upper layers are automatically selected. The “Not” button is used to instruct execution of a logical negation operation for each of various fail bitmaps corresponding to the selected layer.
[0049]
With the above-described layer window displayed, the GUI processing unit 98 determines whether any item content included in the layer window has been changed (step 104). If no change is made and the layer window is closed, a negative determination is made, and the determination process of step 100 described above is repeated.
[0050]
If any item content in the layer window is changed, an affirmative determination is made in the determination in step 104, and the logical viewer creation unit 82 or the physical viewer creation unit 84 displays the reflected item content. (Step 105). After this display process is performed, the process returns to step 100 and the process is repeated.
[0051]
If the display range is instructed using the mouse while the logical viewer window or the physical viewer window is displayed, an affirmative determination is made in step 102. For example, by dragging while pressing the left mouse button on the reduced logical map a11 included in the logical viewer window, zoom processing for the dragged range is instructed. Alternatively, by dragging while pressing the center button of the mouse on the reduced logical map a11, the display range moving process is instructed in the dragged direction without changing the display magnification. The same applies to a case where a change of the display range is instructed while the physical viewer window is displayed.
[0052]
Next, the display range changing unit 87 sends an instruction to the logical viewer creating unit 82 or the physical viewer creating unit 84 to change the current display range (step 106). Then, it returns to step 100 and a process is repeated.
FIG. 9 is a diagram showing a specific example of overlapping of fail bit maps. For example, it is assumed that fail bit maps having different contents are associated with layer 0, layer 1, and layer 2, respectively. In the following description, the case of superimposing logical fail bitmaps will be described as an example, but the same applies to physical fail bitmaps.
[0053]
In this case, the contents of the reduced logical map a11 and the logical fail bitmap a12 in the logical viewer window shown in FIG. 6 are obtained by superimposing the three fail bitmaps corresponding to these three layers 0, 1, and 2. It becomes. At this time, if a different color is set for each layer using the fail color designation box c1 included in the layer display area b1 of the layer window, a different color is assigned to the fail location of each fail bitmap. Is done. Further, when there is a layer that is set to be invisible by setting the invisible mark c4 in the layer display area b1 of the layer window, as shown in FIG. Not used for superposition.
[0054]
Note that the order of overlaying the fail bitmaps corresponding to each layer corresponds to the layer number. For example, layer 0 is the lowest layer, the higher the layer number, the higher the layer, and the highest layer number corresponds to the foremost part. Therefore, the order of superposition can be easily changed by changing the layer number. The layer number is changed by clicking the arrow button arranged near the right end of the button area b2 of the layer window with the mouse. In order to change the overlay order of the fail bitmap corresponding to the inverted layer in the layer display area b1 to one up or down, it is only necessary to click the up arrow button or the down arrow button once.
[0055]
FIG. 11 is a diagram showing another specific example of overlapping of fail bit maps, and shows an outline in the case where the display range is changed by performing zoom processing. Various operations using the logical viewer window can be performed on the layer (for example, layer 1) inverted in the layer display area b1 of the layer window. However, in this embodiment, when zoom processing is instructed using the reduced logical map a11 in the logical viewer window, not only the logical map corresponding to the layer 1 but also the other associated with the layer window. The zoom processing is also performed on the logical maps corresponding to the layers 0 and 2 at the same time. As a result, in the logical viewer window after executing the zoom process, an image obtained by superimposing images obtained by individually zooming the logical maps corresponding to the layers 0, 1, and 2 is displayed.
[0056]
FIG. 12 is a diagram showing another specific example of overlaying fail bit maps, and shows an outline in the case where the display range is changed by performing a movement process. When movement processing is instructed using the reduced logical map a11 in the logical viewer window, not only the logical map corresponding to the layer 1 but also other layers 0 and 2 associated using the layer window are supported. Each logical map is also moved at the same time. As a result, an image obtained by superimposing images obtained by individually moving the logical maps corresponding to the layers 0, 1, and 2 is displayed in the logical viewer window after the movement processing is executed.
[0057]
FIG. 13 is a diagram showing another specific example of overlaying of fail bit maps. In the case where images are superimposed by associating an image not related to a test result such as a fail bit map with any layer. The outline is shown. As an image not related to the test result, for example, an image such as a predetermined frame, ruled line, or character can be considered. In the example shown in FIG. 13, an image including a frame and the character string “test result” is associated with the layer 4 arranged at the top, and this image and the image of each fail bitmap are superimposed. . Thereby, the visibility of the display content can be improved.
[0058]
As described above, in the fail analysis device according to the present embodiment, each of the plurality of overlapped fail bitmap images corresponds to a plurality of layers, and the layers are associated with each other using the layer window. When performing zoom processing or movement processing, the display content can be changed while maintaining the mutual relationship between the fail bitmap images. For this reason, it is not necessary to individually instruct the zoom processing and movement processing for each fail bitmap image, and the operation can be greatly simplified.
[0059]
Further, when the display is erased or redisplayed for each overlapped fail bitmap, it is only necessary to switch between the visible display mark c3 and the invisible mark c4 in the layer window. It becomes unnecessary to repeat the process, and the processing and operation can be simplified.
[0060]
Further, since the contents of the logical operation can be set when the layers are associated using the layer window, the logical operation for each fail bitmap can be performed according to the setting contents.
[0061]
【The invention's effect】
As described above, according to the present invention, each of the plurality of superimposed fail bitmap images corresponds to a plurality of layers, and the layers are associated with each other, so that the content of the display image is changed. In this case, the display content can be changed while maintaining the mutual relationship between the fail bit map images. For this reason, it is not necessary to individually instruct each fail bitmap image and to instruct to change the display magnification, and the operation can be greatly simplified.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a semiconductor test apparatus to which a fail analysis apparatus according to an embodiment is connected.
FIG. 2 is a diagram showing a detailed configuration of a fail analysis apparatus according to the present embodiment.
FIG. 3 is a flowchart showing an operation procedure of the fail analysis apparatus.
FIG. 4 is a diagram showing a specific example of a main viewer window displayed after the fail analysis apparatus is activated.
FIG. 5 is a diagram illustrating a specific example of a main viewer window including a list of reduced images indicating a reduced logical map.
FIG. 6 is a diagram showing a specific example of a logical viewer window.
FIG. 7 is a diagram showing a specific example of a physical viewer window.
FIG. 8 is a diagram illustrating a specific example of a layer window.
FIG. 9 is a diagram illustrating a specific example of overlapping of fail bit maps.
FIG. 10 is a diagram illustrating another specific example of overlaying fail bit maps;
FIG. 11 is a diagram showing another specific example of overlaying fail bit maps;
FIG. 12 is a diagram showing another specific example of overlaying fail bit maps;
FIG. 13 is a diagram showing another specific example of overlapping of fail bit maps.
[Explanation of symbols]
10 Fail analyzer
14 Logical map storage
16 Physical conversion part
18 Physical map storage
20 Reduction processing section
30 Detailed data acquisition unit
40 Reduced data acquisition unit
80 Main viewer creation part
82 Logical Viewer Creation Department
84 Physical Viewer Creation Department
86 Layer Management Department
87 Display range change part
88 Image composition unit
90 Display controller
94 Display device
96 Operation section
98 GUI processing section

Claims (5)

A failure analysis device for displaying a result of testing a semiconductor memory by a semiconductor test device,
Fail bit map creating means for generating a plurality of fail bit map images representing test results corresponding to the semiconductor memory;
A layer management unit that associates each of the plurality of fail bitmap images with a plurality of layers and associates the layers with each other;
Image superimposing means for performing processing for superimposing the plurality of fail bit map images in which the plurality of layers are associated by the layer management means;
Display means for displaying the image superimposed by the image superimposing means;
A failure analysis apparatus comprising: In claim 1,
The layer analysis means manages a display / non-display state of the fail bitmap image for each layer. In claim 1 or 2,
The failure analysis apparatus, wherein the layer management means sets the contents of a logical operation for each of the plurality of layers by the association. In any one of Claims 1-3,
An operation means for instructing a change of a display range of the fail bitmap;
Display for changing the display range for the plurality of fail bitmaps corresponding to the plurality of layers associated by the layer management unit when the operation unit is instructed to change the display range Range changing means;
A failure analysis apparatus further comprising: In any one of Claims 1-4,
The layer analysis means includes the image that is not related to the test result in addition to the plurality of fail bitmap images, and corresponds to each of the plurality of layers and performs the association.

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