JP4294848B2 - Fail analysis device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a fail analysis apparatus that displays a measurement result of a fail distribution state of a memory cell of a semiconductor memory.
[0002]
[Prior art]
The semiconductor test apparatus analyzes each memory cell for defects by reading and writing data to and from each memory cell in a semiconductor memory (hereinafter simply referred to as “memory”) as a device under test (DUT). In general, the semiconductor test apparatus compares the data read from the DUT with predetermined expected value data to determine pass / fail, and stores the result in the fail memory. The failure information stored in the failure memory in this manner is collected by a failure analysis apparatus constituted by a workstation or the like and examined for its contents, thereby performing various types of failure analysis on the DUT.
[0003]
For example, the fail analysis apparatus can display a fail distribution state of a large capacity DRAM as a physical map or a logical map by using a predetermined memory device evaluation tool. The physical map is a two-dimensional fail bit map using physical addresses X and Y as coordinates, and is used to confirm the physical arrangement of defective memory cells in the memory. The logical map is a three-dimensional fail bit map that uses the logical addresses X and Y and the I / O number as coordinates. When the logical address Z is used, the logical map may be four-dimensional. This logical map is generated based on the fail information read from the above-described fail memory.
[0004]
[Problems to be solved by the invention]
By the way, a general semiconductor test apparatus can simultaneously test a plurality of memories, thereby reducing the test time per memory. Therefore, when one test is completed, the fail information corresponding to each of the plurality of memories is stored in the above-described fail memory.
[0005]
However, in order to analyze the fail information obtained in this way, if a conventional fail analysis apparatus is to display the contents of a logical map or physical map, it is necessary to first specify the DUT. For this reason, if you want to know the outline of fail information for a plurality of DUTs to be tested, it is necessary to repeat the operation of displaying the contents of each DUT after specifying one DUT. Is necessary and takes time to operate.
[0006]
In particular, when displaying the contents of the logical map, it is necessary to specify the I / O number together with the DUT. Therefore, when it is desired to see the outline of the fail information for one DUT, it is necessary to repeat the operation for displaying the contents after designating one I / O number for each I / O number. In addition, the operation takes time.
[0007]
In addition, as described above, the conventional fail analysis apparatus can only specify the DUT and I / O number and display the contents of the physical map and logical map, so that each DUT tested at the same time can be displayed. When comparing fail information or comparing fail information of each I / O number of one DUT, it is necessary to remember the contents of each physical map and each logical map to be compared or to print on paper media There is a problem that it is not easy to grasp the outline of fail information for a plurality of DUTs or to grasp the outline of fail information for a plurality of I / O numbers of each DUT.
[0008]
The present invention was created in view of the above points, and an object of the present invention is to provide a fail analysis apparatus that can simplify the operation and shorten the operation time. Another object of the present invention is to provide a fail analysis apparatus that makes it easy to grasp the outline of fail information.
[0011]
[Means for Solving the Problems]
  To solve the above-mentioned problemsThe failure analysis apparatus of the present invention is for displaying a result of testing a semiconductor memory by a semiconductor test apparatus, and includes a test result acquisition means for acquiring a test result corresponding to the semiconductor memory, and the test result acquisition means. List image generating means for generating a list image in which the test results for each I / O number of the obtained semiconductor memory are included in one screen, and display means for displaying the list image generated by the list image generating means are provided. ing. Since test results corresponding to a plurality of I / O numbers included in the semiconductor memory are displayed in one screen, it is easy to grasp the outline of fail information corresponding to each I / O number.
[0012]
Specifically, it is desirable that the above-described list image includes a result image indicating whether the test result is a pass or a fail for each I / O number. Alternatively, it is desirable that the list image described above includes a reduced image of a fail bitmap for each I / O number as a test result. When the list image is viewed, it can be determined whether or not the fail bit map corresponding to each I / O number includes a fail part, or the approximate contents of the fail bit map corresponding to each I / O number are Therefore, it is possible to reliably grasp the outline of the fail information for the entire plurality of I / O numbers of the semiconductor memory.
[0013]
In addition, an operation unit that specifies any position in the list image displayed on the display unit described above, and a detailed image of the corresponding fail bitmap when any result image is specified by the operation unit. It is desirable to further include detailed image generating means for generating. By simply specifying one of the result images included in the list image, the corresponding detailed contents can be displayed, so that the detailed fail bit map corresponding to the semiconductor memory or I / O number including the fail location is displayed. The troublesome work required to confirm the contents of the file is reduced, and the operation can be simplified. Further, the operation time can be shortened with the simplification of the operation.
[0014]
Further, an operation means for designating any position in the list image displayed on the display means described above, and a detailed image of the corresponding fail bitmap when any reduced image is designated by the operation means. It is desirable to further include detailed image generating means for generating. If you want to check the detailed contents as a result of looking at the reduced display, you can display the corresponding detailed contents simply by specifying one of the multiple reduced images included in the list image. Actually, the troublesome work required to confirm the contents of the detailed fail bit map corresponding to the semiconductor memory or the I / O number is reduced, and the operation can be simplified. Further, the operation time can be shortened with the simplification of the operation.
[0015]
In addition, it is desirable to generate reduced fail bitmap data necessary for displaying a reduced image by the semiconductor test apparatus described above, and to generate a reduced image based on the reduced fail bitmap data by the list image generating means. Since the reduced fail bitmap data is generated by the semiconductor test apparatus, the fail analysis apparatus can read the generated reduced fail bitmap data and generate a reduced image. Therefore, it is possible to reduce the time required for reading the data necessary for generating the list image, as compared with the case where the fail analysis device reads detailed fail bitmap data and performs a predetermined reduction process to generate a reduced image. It is possible to shorten the time until the list image is displayed.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a failure analysis apparatus according to an embodiment to which the present invention is applied will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor test apparatus to which the fail analysis apparatus of the present embodiment is connected. As shown in FIG. 1, the semiconductor test apparatus 100 includes a timing generator 110, a pattern generator 112, a waveform shaper 114, a logical comparator 116, an AFM (address fail memory) 118, a CFM (compact fail memory) 120, a tester. A processing unit 122, a communication control unit 124, and a physical conversion unit 126 are included.
[0017]
The address and data generated by the pattern generator 112 are waveform-shaped by the waveform shaper 114 and input to the DUT 130. The logical comparator 116 compares the data read from the DUT 130 with the expected value output from the pattern generator 112 to determine pass / fail.
[0018]
The AFM 118 stores fail information for each address based on the fail signal output from the logical comparator 116 and the address signal output from the pattern generator 112. All of these series of operations are performed in synchronization with the system clock input from the timing generator 110 to each unit. The fail information stored in the AFM 118 is logical fail bitmap data, and bit data (for example, pass) indicating whether or not each memory cell specified by the X address and Y address for each I / O number. Is stored in “0” and “fail” corresponds to “1”).
[0019]
The CFM 120 stores fail information obtained by reducing the content of the AFM 118. For example, for each I / O number, the X address is divided into n and the Y address is divided into m, and 1-bit data corresponding to each divided area is obtained. Specifically, the value of this 1-bit data is obtained by calculating a logical sum of a plurality of bit data of the AFM 118 corresponding to the corresponding divided area of the X address and the corresponding divided area of the Y address. That is, if even one of the plurality of bit data specified in each divided region includes “1” indicating failure, the corresponding bit data in the CFM 120 is set to “1” indicating failure. When all of the plurality of bit data specified in each divided area is “0” indicating a path, the corresponding bit data in the CFM 120 is set to “0” indicating a path. In the following description, data read from the AFM 118 is referred to as “AFM data” or “detailed logical data”, and data read from the CFM 120 is referred to as “CFM data” or “reduced logical data”.
[0020]
The physical conversion unit 126 generates physical fail bitmap data (hereinafter referred to as “detailed physical data”) by performing a physical conversion process based on the detailed logical data stored in the AFM 118. The physical conversion unit 126 is configured by dedicated hardware, and can execute physical conversion processing at high speed.
[0021]
The tester processing unit 122 controls the entire semiconductor test apparatus 100 in order to execute a predetermined test by executing a test program using an operating system (OS). For example, the tester processing unit 122 performs processing for generating CFM data based on AFM data. The communication control unit 124 transmits / receives various data to / from the fail analysis apparatus 10 connected to the semiconductor test apparatus 100.
[0022]
FIG. 2 is a diagram illustrating a detailed configuration of the failure analysis apparatus 10 according to the present embodiment. As shown in FIG. 2, the failure analysis apparatus 10 includes a communication control unit 12, a logical map storage unit 14, a physical conversion unit 16, a physical map storage unit 18, a reduction processing unit 20, a detailed data acquisition unit 30, and a reduced data acquisition unit. 40, a main viewer creation unit 80, a logical viewer creation unit 82, a physical viewer creation unit 84, a display control unit 90, a display device 94, an operation unit 96, and a GUI processing unit 98.
[0023]
The communication control unit 12 transmits / receives various data to / from the semiconductor test apparatus 100. The logical map storage unit 14 stores detailed logical data and reduced logical data obtained by a test on the DUT 130.
The physical conversion unit 16 generates physical fail bitmap data (hereinafter referred to as “detailed physical data”) by performing physical conversion processing based on the detailed logical data. The physical map storage unit 18 stores detailed physical data obtained by physical conversion processing by the physical conversion unit 16. The reduction processing unit 20 performs a reduction process for generating bitmap data obtained by reducing the contents of the detailed physical data (hereinafter referred to as “reduced physical data”). This reduction process is the same as the process when the CFM data is generated from the AFM data in the semiconductor test apparatus 100 described above.
[0024]
The detailed data acquisition unit 30 acquires detailed logical data and detailed physical data. The fail analysis apparatus 10 according to the present embodiment performs various tests based on the “tester mode” in which various analyzes are performed while acquiring detailed logical data and reduced logical data directly from the semiconductor test apparatus 100, and the detailed logical data once stored. There are two types of analysis modes of “file mode” for performing analysis.
[0025]
Specifically, the detailed logical data is acquired by reading AFM data from the AFM 118 in the semiconductor memory 100 in the tester mode, and is acquired by reading the corresponding data from the logical map storage unit 14 in the file mode. The detailed physical data is acquired by reading the result of the physical conversion processing by the physical conversion unit 126 based on the detailed logical data stored in the AFM 118 in the semiconductor test apparatus 100 in the tester mode, and in the file mode. It is acquired by reading the corresponding data from the physical map storage unit 18.
[0026]
Further, the reduced data acquisition unit 40 acquires reduced logical data and reduced physical data. Specifically, the reduced logical data is acquired by reading CFM data from the CFM 120 in the semiconductor test apparatus 100 in the tester mode, and is read by reading the corresponding data from the logical map storage unit 14 in the file mode. The reduced physical data is acquired by performing reduction processing by the reduction processing unit 20 based on the detailed physical data obtained by physical conversion processing in the tester mode, and the detailed physical data read from the physical map storage unit 18 in the file mode. Acquired by performing a reduction process by the reduction processing unit 20 based on the data.
[0027]
The main viewer creation unit 80 creates drawing data necessary for displaying the main viewer window on the display device 94. The main viewer window includes a list of test results of a plurality of DUTs 130 to be tested.
[0028]
The logical viewer creation unit 82 creates drawing data necessary for displaying the logical viewer window on the display device 94. This logical viewer window includes a logical fail bitmap when a specific DUT 130 and an I / O number are designated.
[0029]
Further, the physical viewer creation unit 84 creates drawing data necessary for displaying the physical viewer window on the display device 94. The physical viewer window includes a physical fail bitmap when a specific DUT 130 is designated. Specific examples of the main viewer window, logical viewer window, and physical viewer window described above will be described later.
[0030]
The display control unit 90 generates a video signal to be output to the display device 94 based on the drawing data created by each of the main viewer creation unit 80, the logical viewer creation unit 82, and the physical viewer creation unit 84. The display control unit 90 includes a VRAM (video RAM) 92 and stores drawing data of a window to be displayed at the top on the screen.
[0031]
The operation unit 96 is used by the user to input various instructions, and includes a mouse as a pointing device for designating an arbitrary position on the display screen of the display device 94, numeric keys, alphabet keys, or various symbol keys. A keyboard is included. As the pointing device, a device other than a mouse, such as an input tablet or a touch panel, may be used. A GUI (graphical user interface) processing unit 98 is for realizing GUI processing corresponding to the operation state of the operation unit 96. For example, when various commands or buttons included in the main viewer window or the like are clicked using the mouse, the corresponding process is determined and a request for this process is made.
[0032]
The detailed data acquisition unit 30 and the reduced data acquisition unit 40 described above are the test result acquisition unit, the main viewer generation unit 80 is the list image generation unit, the operation unit 96, the GUI processing unit 98 is the operation unit, and the logical viewer generation unit 82. The physical viewer creation unit 84 corresponds to the detailed image generation unit, and the display control unit 90 and the display device 94 correspond to the display unit.
[0033]
The failure analysis apparatus 10 of this embodiment has such a configuration, and the operation thereof will be described next.
FIG. 3 is a flowchart showing an operation procedure of the fail analysis apparatus, and shows a series of operation procedures for displaying a main viewer window in the tester mode.
[0034]
When the fail analysis device 10 is activated, the main viewer creation unit 80 first creates a screen of the main viewer window and displays it on the display device 94 (step 100).
FIG. 4 is a diagram showing a specific example of the main viewer window. Hereinafter, each display content in the main viewer window will be described.
[0035]
“Start MPAT” button (a1)
The semiconductor test apparatus 100 connected to the fail analysis apparatus 10 is instructed to start the function test of one or a plurality of DUTs 130 that have been set, and is also instructed to capture AFM data and CFM data obtained by the function test. Used to do.
[0036]
“Read” button (a2)
This is used to instruct reading of the fail data when the function test has already been completed and the fail data is stored in the AFM 118 and the CFM 120. When this button is pressed, the AFM data is acquired by the detailed data acquisition unit 30 and the CFM data is acquired by the reduced data acquisition unit 40.
[0037]
DUT designation box and number designation push button (a4)
It is used to designate a specific DUT 130 or change the designation. A specific DUT 130 can be specified by directly entering a number in this box using the numeric keypad provided in the operation unit 96. Alternatively, a specific DUT 130 can be designated by operating this push button with a mouse provided in the operation unit 96 and pressing it down as many times as necessary. In order to display the fail map after changing the DUT number, it is necessary to press either the “Start MPAT” button a1 or the “Read” button a2 described above.
[0038]
Origin designation toggle button (a5)
Used to specify the origin position. An arbitrary origin position can be designated by pressing any of the four buttons. When a reduced image (described later) of a logical fail bitmap is included in the main viewer window, display is performed using this origin position. When a logical map viewer window or a physical map viewer window is started from the main viewer window, the origin position specified here is reflected.
[0039]
Axis change push button (a6)
Used to specify the X and Y axes of the fail bitmap. Each time this button is pressed, the X axis and the Y axis are switched. When a logical viewer window or a physical viewer window is activated from the main viewer window, the origin position specified here is reflected.
[0040]
DUT data display area (a7)
This is used to display a result image showing each test result of the plurality of DUTs 130 to be tested. A number included in each result image indicated by a rectangle indicates a DUT number, and whether the DUT 130 specified by the DUT number is a pass or a fail is expressed by a color in the rectangle. For example, in the case of a pass (when all the reduced logical data corresponding to this DUT number is a pass), the inside of the rectangle is colored green, and in the case of a failure (at least one of the reduced logical data corresponding to this DUT number is included in the reduced logical data). When there is a failure), the inside of the rectangle is colored red. In the DUT data display area a7 shown in FIG. 4, DUT numbers 1 to 128 are shown. However, when the number of DUTs 130 actually mounted on the semiconductor test apparatus 100 is less than 128, the corresponding DUT 130 is displayed. Numbers in rectangles that do not exist are hidden or shadowed. For example, when a notification (Notify) is sent from the semiconductor test apparatus 100 to the fail analysis apparatus 10, the number of DUTs 130 and the following I / O numbers are read and updated. . Further, when the number of DUTs 130 actually mounted on the semiconductor test apparatus 100 exceeds 128, the pages including the result images of the 128 DUTs 130 are switched and displayed.
[0041]
I / O data display area (a8)
This is used to display a result image indicating a test result for each I / O number for a specific DUT 130 in which a DUT number is designated. A number included in each result image indicated by a rectangle indicates an I / O number, and whether the logical fail bitmap specified by the I / O number is a pass or a fail depends on the color in the rectangle. It is expressed. For example, in the case of a pass (when all the reduced logical data corresponding to this I / O number is a pass), the inside of the rectangle is colored green, and in the case of a failure (reduced logical data corresponding to this I / O number) If there is even one failure, the inside of the rectangle is colored red. In the I / O data display area a8 shown in FIG. 4, I / O numbers from 0 to 143 are shown. However, the maximum value of the I / O number of the DUT 130 actually mounted in the semiconductor test apparatus 100 is shown. If it is smaller than 143, the numbers in the rectangles that do not have corresponding I / O numbers are not displayed or shadowed. If the maximum value of the DUT number exceeds 143, the pages are switched and displayed.
[0042]
Display switching option menu (a9)
This is used to switch the display contents in the above-described DUT data display area a7 or I / O data display area a8. For the DUT data display area a7, display options of “Pass / Fail”, “CFM (All)”, “CFM (16 DUT)”, and “CFM (32 DUT)” are prepared. For the I / O data display area a8, display options of “Pass / Fail”, “CFM (All)”, “CFM (16 or 18 I / O)”, and “CFM (32 or 36 I / O)” are prepared. .
[0043]
“Pass / Fail” is an option for displaying the above-described result image indicating whether the test result is pass or fail. The screen of the main viewer window shown in FIG. 4 shows a state in which this display option is selected as a default at the time of activation.
[0044]
Each of “CFM (All)”, “CFM (16 DUT)”, “CFM (32 DUT)”, “CFM (16 or 18 I / O)”, and “CFM (32 or 36 I / O)” corresponds to reduced logical data. This is an option for displaying a reduced image indicating a logical fail bitmap (hereinafter referred to as “reduced logical map”) by the number in parentheses. A specific display example of the reduced image will be described later.
[0045]
“Physical” button (a10)
This is used to instruct the display of a physical viewer window corresponding to a specific DUT 130 to which a DUT number is designated.
With the main viewer window shown in FIG. 4 displayed, next, the GUI processing unit 98 determines whether the display option has been changed (step 101), whether the DUT number has been changed (step 102), It is determined whether an I / O number has been designated (step 103) and whether physical conversion has been instructed (step 104).
[0046]
Display options other than “Pass / Fail” included in the display switching menu are for displaying a list of reduced logical maps. If these display options are selected, the determination in step 101 is affirmative. Next, the main viewer creation unit 80 changes the display content of the main viewer window based on the changed display option (step 105).
[0047]
FIG. 5 is a diagram showing a specific example of a main viewer window including a list of reduced images showing reduced logical maps. For example, “CFM (16 DUT)” is selected as the display option corresponding to the DUT data display area a7, and “CFM (16 or 18 I / O)” is selected as the display option corresponding to the I / O data display area a8. Has been.
[0048]
In the DUT data display area a7, a rectangular area including a number has the same contents as when “Pass / Fail” is selected as a display option. Whether the DUT 130 designated by this number is a pass or a fail is determined. Corresponds to the result image shown. The rectangular area located at the upper part shows a reduced image showing the contents of the reduced logical map for each DUT 130. Since CFM data (reduced logical data) for each I / O number is read from the CFM 120 in the semiconductor test apparatus 100, the main viewer creation unit 80 performs each of the reduced logical data for all I / O numbers for each DUT 130. The reduced image is generated by calculating the logical sum of the bits.
[0049]
In the I / O data display area a8, a rectangular area including a number has the same contents as when “Pass / Fail” is selected as the display option, and the reduced logical data of this I / O number is passed. It corresponds to the result image indicating whether it is a failure or a failure. A rectangular area located at the upper part shows a reduced image indicating the contents of the reduced logical map for each I / O number.
[0050]
In the example shown in FIG. 5, both the DUT data display area a7 and the I / O data display area a8 are displayed. However, it is possible to increase the number of other displays that can be made non-displayed. it can. FIG. 6 is a diagram showing a specific example of the main viewer window when the DUT data display area a7 is hidden and “CFM (All)” is selected as the display option of the I / O data display area a8. is there.
[0051]
Further, when the DUT number selected at that time is changed while the main viewer window is displayed, an affirmative determination is made in the determination of step 102, and then the main viewer creating unit 80 is changed. The display content of the I / O data display area a8 corresponding to the subsequent DUT number is changed (step 106).
[0052]
Further, when any I / O number included in the I / O data display area a8 is designated in a state where the main viewer window is displayed, an affirmative determination is made in the determination of step 103, and then the logical The viewer creation unit 82 creates a screen of a logical viewer window corresponding to the designated I / O number and displays it on the display device 94 (step 107).
[0053]
FIG. 7 is a diagram showing a specific example of the logical viewer window. This window includes a reduced logical map a11 and a logical fail bitmap a12 corresponding to part or all of the reduced logical map a11. The logical fail bitmap a12 is created based on the detailed logical data acquired by the detailed data acquisition unit 30.
[0054]
If the “Physical” button a10 is selected while the main viewer window is displayed, an affirmative determination is made in the determination of step 104, and then the physical viewer creation unit 84 is designated at that time. A screen of a physical viewer window corresponding to the DUT number is created and displayed on the display device 94 (step 108).
[0055]
FIG. 8 is a diagram showing a specific example of the physical viewer window. This window includes a reduced physical map a13 and a logical fail bitmap a14 corresponding to part or all of the reduced physical map a13. The logical fail bitmap a14 is created based on the detailed logical data acquired by the detailed data acquisition unit 30.
[0056]
As described above, in the failure analysis apparatus 10 of the present embodiment, the test results corresponding to the plurality of DUTs 130 are displayed in a list in the main viewer window, so that an overview of the failure information of each DUT 130 can be easily grasped. . In particular, the presence / absence of a failure can be easily grasped by displaying a list of result images, and an approximate failure distribution state can be understood from a list of reduced images in a fail bitmap. Therefore, for each DUT 130 or each I / O number. It is possible to reliably grasp the outline of the failure information.
[0057]
In addition, a list image can be displayed because a corresponding logical viewer window or physical viewer window can be displayed simply by specifying one of the list images (result image or reduced image) included in the main viewer window. As a result, it is difficult to confirm the detailed contents, and it is necessary to display the detailed fail bit map corresponding to the specific DUT 130 or the specific I / O number and confirm the contents. The labor is reduced and the operation can be simplified. Further, the operation time can be shortened with the simplification of the operation.
[0058]
In particular, since the reduced logical data (CFM data) necessary for displaying a list of reduced images included in the main viewer window is created by the semiconductor test apparatus 100, a main viewer window including such a list of reduced images is displayed. It is possible to shorten the time until display.
[0059]
【The invention's effect】
As described above, according to the present invention, test results corresponding to a plurality of semiconductor memories are displayed in one screen, so that it is easy to grasp the outline of fail information for each semiconductor memory. Further, the troublesome work required to confirm the contents of the semiconductor memory including the fail location or the detailed fail bit map corresponding to the I / O number is reduced, and the operation can be simplified.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a semiconductor test apparatus to which a fail analysis apparatus according to an embodiment is connected.
FIG. 2 is a diagram showing a detailed configuration of a fail analysis apparatus according to the present embodiment.
FIG. 3 is a flowchart showing an operation procedure of the fail analysis apparatus.
FIG. 4 is a diagram illustrating a specific example of a main viewer window.
FIG. 5 is a diagram showing a specific example of a main viewer window including a list of reduced images showing a reduced logical map.
FIG. 6 is a diagram showing another specific example of the main viewer window.
FIG. 7 is a diagram illustrating a specific example of a logical viewer window.
FIG. 8 is a diagram showing a specific example of a physical viewer window.
[Explanation of symbols]
10 Fail analyzer
14 Logical map storage
16 Physical conversion part
18 Physical map storage
20 Reduction processing section
30 Detailed data acquisition unit
40 Reduced data acquisition unit
80 Main viewer creation part
82 Logical Viewer Creation Department
84 Physical Viewer Creation Department
90 Display controller
94 Display device
96 Operation section
98 GUI processing section

Claims (6)

A failure analysis device for displaying a result of testing a semiconductor memory by a semiconductor test device,
Test result acquisition means for acquiring a test result corresponding to the semiconductor memory;
List image generating means for generating a list image in which test results for each I / O number of the semiconductor memory obtained by the test result acquiring means are included in one screen;
Display means for displaying the list image generated by the list image generation means;
A failure analysis apparatus comprising: In claim 1,
The fail analysis apparatus, wherein the list image includes a result image indicating whether the test result is a pass or a fail for each I / O number. In claim 1 or 2,
The list analysis image includes a fail bitmap reduced image for each I / O number as the test result. In claim 2,
Operation means for designating any position in the list image displayed on the display means;
Detailed image generation means for generating a detailed image of a corresponding fail bitmap when any of the result images is designated by the operation means;
The failure analysis apparatus further comprising: the detailed image generated by the detailed image generation means is displayed by the display means. In claim 3,
Operation means for designating any position in the list image displayed on the display means;
Detailed image generating means for generating a detailed image of a corresponding fail bitmap when any one of the reduced images is designated by the operating means;
The failure analysis apparatus further comprising: the detailed image generated by the detailed image generation means is displayed by the display means. In claim 3 or 5,
The semiconductor test apparatus generates reduced fail bitmap data necessary for displaying the reduced image,
The list image generation means generates the reduced image based on the reduced fail bitmap data.

Images