JP4135648B2 - Switch circuit having clamp function and analog multiplexer - Google Patents

Description

  The present invention relates to a switch circuit having a clamp function suitable for input of an analog voltage and an analog multiplexer using the switch circuit.

For example, in a CMOS device, the device breakdown voltage has decreased due to recent rapid miniaturization, and the need for a clamp circuit that regulates the input voltage is further increased. Patent Document 1 discloses an input interface circuit for an input terminal to which a voltage exceeding a power supply voltage may be applied. In this input interface circuit, MOS transistors are provided in two stages between the input terminal and the high potential side power supply line and the low potential side power supply line, and an intermediate potential is applied to the gate of the transistor on the input terminal side to be applied to the gate. This is intended to alleviate the generated voltage. Patent Document 2 discloses a clamp circuit that can clamp a terminal voltage to a desired clamp voltage with respect to an input of an overvoltage and has a small temperature variation of the clamp voltage.
JP 2002-043924 A JP 2003-2558581 A

  Since the input interface circuit described in Patent Document 1 gives an intermediate potential to the gates of the power supply side and ground side transistors connected across the input terminal, when an intermediate voltage is input to the input terminal, Both these transistors are turned off. Therefore, it is not suitable for analog voltage input. The clamp circuit described in Patent Document 2 can be applied to an analog voltage. However, since the voltage state is detected and clamped for each terminal, the circuit scale increases when there are multiple channel input terminals, and the layout area increases. It will increase.

  FIG. 5 shows an electrical configuration of a clamp circuit used together with a multiplexer in the signal input section of the multi-channel A / D converter. The clamp circuit 101 is provided between the input terminal 102 and the multiplexer 103 for each channel. Transistors Q101 and Q102 for clamping the input voltage are connected between the input terminal 102 and the power supply lines 104 and 105, and these transistors Q101 and Q102 use the clamp voltage (5.2V, On-off control is performed by comparators 106 and 107 for comparison with -0.2V). Transistors Q103 and Q104 for releasing surge current are also connected between the input terminal 102 and the power supply lines 104 and 105.

  Since the clamp circuit 101 can reliably regulate the voltage at the input terminal 102 within the range of the clamp reference voltage, a voltage exceeding the withstand voltage is applied to the analog switch (transistor) constituting the multiplexer 103. Can be prevented. However, since the clamp circuit 101 including the comparators 106 and 107 is required for each channel, the increase in the layout area and the variation in the clamp voltage between the channels due to the offset voltage of the comparators 106 and 107 become a problem.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a switch circuit having a clamp function that is suitable for analog voltage input and can reduce the layout area as much as possible, and an analog multiplexer using the switch circuit. It is to provide.

According to the means described in claim 1, an analog voltage is applied to the input terminal of the semiconductor integrated circuit device from the outside via the current limiting element, and the switch circuit is controlled to be closed. Then, the first to fourth transistors are turned on, and the voltage at the input terminal (input voltage) is directly applied to the circuit formed in the semiconductor integrated circuit device through the input line. In this case, the input voltage may be regulated by a clamp circuit separately provided on the input line.

  On the other hand, when the switch circuit is controlled to be in the open state, the first and second transistors and the third and fourth transistors connected in series between the input terminal and the input line, respectively. The second and fourth transistors are completely turned off, and the input terminal and the input line are electrically disconnected. That is, the second and fourth transistors are transistors that function as switches. Hereinafter, this open state will be described.

In the open state, the second and fourth transistors are protected against the input voltage by the clamping function of the switch circuit. In other words, the first clamp circuit performs a clamp operation on the input voltage on the high potential side, and the voltage VN1 at the first node is set to the upper limit voltage necessary for the second transistor to remain off. The clamp control is performed to a voltage lower than that of the second transistor and within a range not exceeding the gate breakdown voltage of the second transistor. The second clamp circuit clamps the input voltage on the low potential side. The second node voltage VN2 is the lower limit voltage necessary for the fourth transistor to remain off. Higher than that and within the range not exceeding the gate breakdown voltage of the fourth transistor.

Intermediate voltages VG1 and VG3 within a range that does not exceed the gate breakdown voltage of the first and third transistors are applied to the gates of the transistors Q1 and Q3, respectively, with respect to the voltage range that the input terminal can take. When the input voltage exceeds the threshold voltage of the transistor Q1 with respect to the intermediate voltage VG1, the transistor Q1 is turned on. When the input voltage becomes lower than the threshold voltage of the transistor Q3 with respect to the intermediate voltage VG3, the transistor Q3 is turned on. It becomes.

That is, the first transistor is turned on only when the input voltage is at least higher than the intermediate voltage VG1 , and the input voltage is supplied to the first node, so that the power supply voltage or a voltage close to the power supply voltage is used. The first clamp circuit and the second transistor are protected from the withstand voltage surface. Similarly, the second transistor is turned on only when the input voltage is at least lower than the intermediate voltage VG3 and applies the input voltage to the second node, whereby the ground voltage or a voltage close to the ground voltage is used. The second clamp circuit and the fourth transistor are protected from the withstand voltage surface.

  According to the present switch circuit, the second and fourth functions as a switch in an application in which a voltage higher than the power supply voltage or a voltage lower than the ground voltage may be input to the input terminal via the current limiting element. It is possible to open and close the input analog voltage while protecting the transistor of the above withstand voltage. In this case, the first and second clamp circuits do not need to use an operational amplifier, a comparator, or the like as means for limiting the voltages of the first and second nodes within a predetermined voltage range, respectively, and the layout area is minimized. Can be reduced.

Specifically , the power supply voltage Vdd, the ground voltage 0 V, and the intermediate voltages VG1 and VG3 are used for gate control of the transistors Q1 to Q4.
In the closed state, when the input voltage is in the range of the threshold voltages th1 and Vth2 of the first and second transistors, the first and second transistors are turned on, and the input voltage is (power supply voltage Vdd−third and second). In the range below the threshold voltages th3 and Vth4) of the fourth transistor, the third and fourth transistors are turned on. That is, at least one of the first and second nodes is turned on.

なる関係を満たす範囲内の中間電圧ＶG1、ＶG3が印加される。 On the other hand, in the open state, the gates of the first and third transistors are connected to the first and third transistors from the viewpoint of withstand voltage protection.

Intermediate voltages VG1 and VG3 within a range satisfying the following relationship are applied.

なる関係を満たす範囲内の電圧にクランプ制御する。 Further, the first and second clamp circuits respectively apply the voltages VN1 and VN2 of the first and second nodes from the viewpoint of not turning on the second and fourth transistors and from the viewpoint of withstand voltage protection.

Clamp control to a voltage within a range that satisfies the relationship

According to the means described in claim 2 , in the closed state, the transistors Q5, Q7, Q9, and Q11 are turned off, and the first and second clamp circuits do not operate. On the other hand, in the open state, transistors Q5, Q7, Q9, and Q11 are turned on. In this open state, when the voltage of the first node rises, the third clamp circuit is turned on before the P-channel second transistor is turned on, and the first node is turned on using the first clamp control voltage. Suppress voltage rise. On the other hand, when the voltage at the first node is lowered, the fourth clamp circuit is turned on before the gate voltage of the P-channel second transistor exceeds the gate breakdown voltage, and the second clamp control voltage is used to turn on the second node. 1 to suppress the voltage drop of the node.

  Similarly, when the voltage of the second node decreases in the open state, the fifth clamp circuit is turned on before the N-channel fourth transistor is turned on, and the second clamp control voltage is used to set the second clamp voltage. Reduces node voltage drop. On the other hand, when the voltage at the second node rises, the sixth clamp circuit is turned on before the gate voltage of the N-channel fourth transistor exceeds the gate breakdown voltage, and the fourth clamp control voltage is used to 2 suppresses the rise in voltage at the node.

  That is, the third and fifth clamp circuits function to clamp the input voltage from the viewpoint of device breakdown voltage and not to turn on the second and fourth transistors. The fourth and sixth clamp circuits It functions to fix the potential of the nodes 1 and 2 so as not to be indefinite and to protect the second and fourth transistors withstand voltage. Since the first and second clamp circuits have very simple circuit configurations, the layout area can be reduced.

なる関係を満たす範囲内の電圧に設定し、
第３、第４のクランプ制御電圧Ｖc3、Ｖc4を、それぞれ

なる関係を満たす範囲内の電圧に設定する。なお、トランジスタのしきい値電圧は製造上ばらつくため、マージンを持たせることが好ましい。 Specifically, when the power supply voltage Vdd and the ground voltage 0 V are applied to the gates of the second and fourth transistors in the open state, the first and second clamp control voltages Vc1 and Vc2 are respectively set to

Set the voltage within a range that satisfies the relationship
The third and fourth clamp control voltages Vc3 and Vc4 are respectively

Set the voltage within the range that satisfies the following relationship. Note that it is preferable to provide a margin because the threshold voltage of the transistor varies in manufacturing.

According to the means described in claim 3 , in the closed state, the thirteenth and fourteenth transistors are turned on in the same manner as the transistors Q1 to Q4. On the other hand, in the open state, the power supply voltage and the ground voltage are applied to the gates of the thirteenth and fourteenth transistors, respectively. Therefore, the thirteenth and fourteenth transistors are turned off, and the fourth clamp circuit The current flowing into the third clamp circuit and the current flowing from the fifth clamp circuit into the sixth clamp circuit can be cut off. That is, the thirteenth and fourteenth transistors have a function of preventing interference between the third and fourth clamp circuits and between the fifth and sixth clamp circuits, respectively.

  However, when the input voltage becomes higher than the threshold voltage with respect to the gate voltage (power supply voltage) of the thirteenth transistor, the thirteenth transistor is turned on and a clamp operation is performed by the third clamp circuit. When the input voltage becomes lower than the threshold voltage by the threshold voltage or more than the gate voltage (ground voltage) of the fourteenth transistor, the fourteenth transistor is turned on and the clamp operation is performed by the fifth clamp circuit. Therefore, even if the thirteenth and fourteenth transistors are provided, the clamping function is not hindered.

According to the means described in claim 4 , it is possible to input only the analog voltage applied to the input terminal of the selected channel to the common input line (common line). Since this analog multiplexer performs the clamping operation by itself for the open channel, it is not necessary to provide a clamp circuit using an operational amplifier or a comparator for each input terminal of each channel, and it is sufficient to provide a common clamp circuit for the common line. . As a result, the layout size when configured as a semiconductor integrated circuit device can be reduced, and the clamp voltage does not vary between the selected channels.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
FIG. 3 shows a schematic electrical configuration of an IC 1 (semiconductor integrated circuit device) incorporating a multi-channel A / D converter. The IC 1 is a CMOS one-chip microcomputer mounted on, for example, a control board in a vehicle ECU (Electronic Control Unit). In addition to the A / D converter 2, a CPU, a memory, a digital peripheral circuit, and an analog peripheral circuit (None of them are shown).

  This A / D conversion device 2 converts an input voltage Vin applied to an input terminal 3 of each channel from a signal output means such as a sensor through a resistor R1 (corresponding to a current limiting element) into an analog multiplexer 4 (hereinafter simply referred to as a multiplexer). 4), and the A / D converter 5 performs A / D conversion on the selected voltage. The signal output means may output a voltage exceeding the power supply voltage Vdd of IC1 or a voltage lower than 0V.

  The input terminal 3 of each channel is connected to the input terminal of the multiplexer 4 through the surge voltage protection circuit 6, and the common line 7 (corresponding to the input line) from the output terminal of the multiplexer 4 to the A / D converter 5. ) Is provided with a common clamp circuit 8. The control circuit 9 that receives a command from the CPU controls the channel switching of the multiplexer 4 and the conversion operation of the A / D converter 5. Similarly to the circuit shown in FIG. 5, the clamp circuit 8 includes a transistor provided between the common line 7 and the power supply line, a transistor provided between the common line 7 and the ground line, and the voltage of the common line 7. It comprises a comparator that compares the clamp reference voltage.

  FIG. 1 shows an electrical configuration of a switch circuit 10 provided between each input terminal and a common output terminal in the multiplexer 4. The voltage state shown in FIG. 1 shows a case where the switch circuit 10 is controlled to an off state as will be described later, and FIG. 2 shows a case where the switch circuit 10 is controlled to an on state. 1 and 2 use transistors Q1 to Q14. These transistors Q1 to Q14 correspond to the first to fourteenth transistors of the present invention, respectively. Among the transistors Q1 to Q14, the substrate potential of the P-channel transistor is set to the power supply voltage Vdd, and the N-channel substrate potential is set to the ground potential of 0V.

  P-channel transistors Q1, Q13, and Q2 are connected in series between the input terminal 10a and the output terminal 10b of the switch circuit 10, and in parallel with these, N-channel transistors Q3, Q14, and Q4 are connected. Connected in series. Here, the node from the transistors Q1 to Q13 to Q2 corresponds to the first node in the present invention, and the node from the transistors Q3 to Q4 to Q4 corresponds to the second node in the present invention. .

  The clamp circuit 11 (corresponding to the first clamp circuit) regulates the voltage of the first node within a predetermined voltage range, and the clamp circuit 12 (corresponding to the second clamp circuit) is the second node. Is regulated within a predetermined voltage range. The clamp circuit 11 includes clamp circuits 13 and 14 (corresponding to third and fourth clamp circuits) and the transistor Q13. The clamp circuit 12 includes clamp circuits 15 and 16 (fifth and sixth clamp circuits). Equivalent to a clamp circuit) and the transistor Q14.

  The clamp circuit 13 is configured by a series circuit of an N-channel transistor Q5 connected to a node 17 which is a common connection point between the transistors Q13 and Q2, and a P-channel transistor Q6 connected between the gate and the drain. Yes. The drain of the transistor Q6 is connected to a node (first clamp control node) having a clamp control voltage Vc1 (corresponding to the first clamp control voltage). The clamp circuit 14 is constituted by a series circuit of an N-channel transistor Q7 connected to a node 18 which is a common connection point between the transistors Q1 and Q13, and a P-channel transistor Q8 connected between the gate and the drain. Has been. The source of the transistor Q8 is connected to a node (second clamp control node) having a clamp control voltage Vc2 (corresponding to a second clamp control voltage).

  The clamp circuit 15 is configured by a series circuit of a P-channel transistor Q9 connected to a node 19 which is a common connection point between the transistors Q14 and Q4, and an N-channel transistor Q10 connected between the gate and the drain. Yes. The drain of the transistor Q10 is connected to a node (third clamp control node) having a clamp control voltage Vc3 (corresponding to a third clamp control voltage). The clamp circuit 16 is constituted by a series circuit of a P-channel transistor Q11 connected to the node 20 which is a common connection point between the transistors Q3 and Q14, and an N-channel transistor Q12 connected between the gate and the drain. Has been. The source of the transistor Q12 is connected to a node (fourth clamp control node) having a clamp control voltage Vc4 (corresponding to a fourth clamp control voltage).

  FIG. 4 shows a circuit configuration of the surge voltage protection circuit 6. Between the input terminal 3 and the power supply line 21, a P-channel transistor Q15 and a P-channel transistor Q16 connected between the gate and the drain are connected in series. Further, between the input terminal 3 and the ground line 22, an N-channel transistor Q17 and an N-channel transistor Q18 connected between the gate and the drain are connected in series.

  The substrate potentials of the P-channel transistors Q15 and Q16 are set to the power supply voltage Vdd, and the substrate potentials of the N-channel transistors Q17 and Q18 are set to the ground potential 0V. An intermediate voltage of 3.3 V is applied to the gates of the transistors Q15 and Q17. In the surge voltage protection circuit 6, a diode having the input terminal 3 side as an anode is connected between the input terminal 3 and the power supply line 21, and the input terminal 3 side is connected as a cathode between the input terminal 3 and the ground line 22. This is an equivalent circuit to which a diode is connected.

Next, the operation of this embodiment will be described.
In the following description, specific voltage values are shown as an example, but the circuit conditions in that case are as follows.
・ Power supply voltage Vdd = 5V (assuming there is a fluctuation up to 5.5V)
-Threshold voltages Vth1 to Vth14 of transistors Q1 to Q14 = 1V (shown in absolute values)
・ Gate breakdown voltage VGSS1 to VGSS14 of transistor Q1 to Q14 = 5.5V
・ Pn junction forward voltage Vf = 1V

  First, in FIG. 3, upon receiving a command from the CPU, the control circuit 9 turns on the switch circuit 10 of one channel in the multiplexer 4 and switches off the switch circuit 10 of the other channels. For example, when channel 1 is selected, the input voltage Vin1 applied to the input terminal 3 is supplied to the A / D converter 5 through the switch circuit 10 and the clamp circuit 8 provided in the common line 7. When the switching of the multiplexer 4 is completed, the control circuit 9 outputs a conversion start signal to the A / D converter 5.

  The clamp reference voltage of the clamp circuit 8 is set to 5.2V on the high potential side and -0.2V on the low potential side, and the input voltage Vin of the selected channel is limited to -0.2V or more and 5.2V or less. And applied to the A / D converter 5. On the other hand, in the other channels that are not selected, the switch circuit 10 itself can ensure that the switch circuit 10 can be maintained in an OFF state and that a voltage exceeding the withstand voltage is not applied to the transistors constituting the switch circuit 10. Perform clamping operation.

  The surge voltage protection circuit 6 is a circuit whose main purpose is to suppress a surge voltage inputted from the outside, and the input voltage Vin is set to Vin (min (min) under the condition that the power supply voltage Vdd fluctuates to 5.5V. ) (= −Vf) to Vin (max) (= Vdd + Vf), that is, clamp in the range of −1V to 6.5V.

Next, the operation of the switch circuit 10 will be described.
FIG. 2 shows a state where the switch circuit 10 is turned on (closed state). The L level (0 V) is input to the gates of the P-channel transistors Q1, Q13, and Q2, and the H level (Vdd) is input to the gates of the N-channel transistors Q3, Q14, and Q4. As a result, the transistors Q1, Q13, Q2, Q3, Q14, and Q4 are all turned on, and the voltage Vin at the input terminal 10a is output from the output terminal 10b while maintaining the voltage value as it is. In this case, the input voltage Vin is limited to a range of −0.2V to 5.2V by the clamp circuit 8 at the subsequent stage.

  Further, the L level is input to the gates of the N-channel transistors Q5 and Q7, and the H level is input to the gates of the P-channel transistors Q9 and Q11. As a result, the transistors Q5, Q7, Q9, and Q11 are all turned off to prevent interference between the input voltage Vin and the voltages Vc1 to Vc4.

  FIG. 1 shows a state where the switch circuit 10 is turned off (open state). The H level is input to the gates of the P-channel transistors Q13 and Q2, and the L level is input to the gates of the N-channel transistors Q14 and Q4. Thereby, the transistors Q13, Q2, Q14, and Q4 are turned off. The transistors Q2 and Q4 function as switches that are the main body of the switch circuit 10.

Intermediate voltages VG1 and VG3 (= 2.5 V) are input to the gates of the transistors Q1 and Q3, respectively. Thereby, the transistors Q1 and Q3 are turned on only when the conditions of the following expressions (1) and (2) are satisfied, respectively.

  That is, the transistor Q1 has a function of protecting the clamp circuit 11 withstand voltage by preventing the low input voltage Vin of less than 3.5V from entering the nodes 17 and 18. Similarly, the transistor Q3 has a function of protecting the clamp circuit 12 withstand voltage by preventing the nodes 19 and 20 from receiving a high input voltage Vin exceeding 1.5V.

  The intermediate voltages VG1 and VG3 are set to voltages at which the gates of the transistors Q1 and Q3 do not exceed the gate breakdown voltages VGSS1 and VGSS3, respectively. That is, since the input voltage Vin changes within the range of Vin (min) (= −Vf) to Vin (max) (= Vdd + Vf), it is assumed that the input voltage Vin reaches the maximum value Vin (max). It is necessary to set the voltage to Vin (max) −VGSS1 or more and Vin (max) −VGSS3 or more, respectively. On the other hand, assuming that the input voltage Vin becomes the minimum value Vin (min), it is necessary to set the voltages to Vin (min) + VGSS1 or less and Vin (min) + VGSS3 or less, respectively. In summary:

書き直すと以下のようになる。

When rewritten, it becomes as follows.

  When the switch circuit 10 is turned off, the H level is input to the gates of the transistors Q5 and Q7, and the L level is input to the gates of the transistors Q9 and Q11. Thereby, the transistors Q5, Q7, Q9, and Q11 are turned on, and the clamp circuits 13, 14, 15, and 16 become operable. Hereinafter, operations of the clamp circuits 13, 14, 15, and 16 will be described.

Since the transistor Q2 is a P-channel type, the transistor Q2 cannot be kept off when the voltage VN17 at the node 17 increases. The voltage VN17 at the node 17 at which the transistor Q2 can be kept off is expressed by the following equation (5).

Therefore, the clamp circuit 13 performs clamp control so that the voltage VN17 (the voltage of the first node) at the node 17 is lower than the voltage necessary for maintaining the transistor Q2 in the off state. The clamp control voltage Vc1 is set so as to satisfy the following expression (6) (for example, 1 V).

Further, when the input voltage Vin decreases, the transistor Q1 is turned off, so that the nodes 17 and 18 are floated. At this time, in order that the gate voltage of the transistor Q2 does not exceed the gate breakdown voltage VGSS2, the voltage VN17 of the node 17 needs to satisfy the following equation (7).

Therefore, the clamp circuit 14 clamps and controls the voltage VN17 at the node 17 (the voltage at the first node) to a voltage that does not exceed the gate breakdown voltage VGSS2 of the transistor Q2. The clamp control voltage Vc2 is set so as to satisfy the following equation (8) (for example, 2.5 V).

The clamp circuit 15 functions in the same manner as the clamp circuit 13. That is, since the transistor Q4 is an N-channel type, the transistor Q4 cannot maintain the OFF state when the voltage VN19 at the node 19 decreases. The voltage VN19 at the node 19 at which the transistor Q4 can be kept off is expressed by the following equation (9).

Therefore, the clamp circuit 15 performs clamp control so that the voltage VN19 (second node voltage) at the node 19 is higher than the voltage necessary for the transistor Q4 to maintain the off state. The clamp control voltage Vc3 is set so as to satisfy the following expression (10) (for example, 3.3 V).

The clamp circuit 16 functions in the same manner as the clamp circuit 14. That is, when the input voltage Vin rises, the transistor Q3 is turned off, so that the nodes 19 and 20 are floated. At this time, in order for the gate voltage of the transistor Q4 not to exceed the gate breakdown voltage VGSS4, the voltage VN19 of the node 19 needs to satisfy the following equation (11).

Therefore, the clamp circuit 16 clamps and controls the voltage VN19 (second node voltage) at the node 19 to a voltage within a range not exceeding the gate breakdown voltage VGSS4 of the transistor Q4. The clamp control voltage Vc4 is set so as to satisfy the following equation (12) (for example, 2.5 V).

  Next, functions of the transistors Q13 and Q14 provided in the clamp circuits 11 and 12 will be described. In the numerical example shown in FIG. 1, that is, in the case of the clamp control voltage Vc1 = 1.0V, Vc2 = 2.5V, Vc3 = 3.3V, Vc4 = 2.5V, even if the transistors Q13 and Q14 are not provided, the transistors The return current does not flow through Q8, Q7, the first node, the path of transistors Q5, Q6, the transistors Q10, Q9, the second node, and the paths of transistors Q11, Q12.

However, when the clamp control voltages Vc1 and Vc2 and the clamp control voltages Vc3 and Vc4 satisfy the following expressions (13) and (14), a reflux current flows.

Therefore, in order to prevent this return current, transistors Q13 and Q14 are provided at the first and second nodes, respectively. The transistor Q13 is turned off when the input voltage Vin is lower than Vdd + Vth13. However, the transistor Q13 is turned on when the input voltage Vin is higher than Vdd + Vth13, so that the clamp operation of the clamp circuit 13 is not hindered. Similarly, the transistor Q14 is turned off when the input voltage Vin is higher than -Vth14. However, the transistor Q14 is turned on when the input voltage Vin is lower than this, so that the clamping operation of the clamp circuit 15 is not hindered. Note that the transistors Q13 and Q14 may be omitted when the clamp control voltages Vc1 to Vc4 are set within a voltage range in which the expressions (13) and (14) are not satisfied.
By such voltage setting, the transistors Q1 to Q14 constituting the switch circuit 10 in the off state can be protected from an excessive voltage, and the transistors Q2 and Q4 can be reliably maintained in the off state.

  As described above, the multiplexer 4 according to the present embodiment outputs the input voltage Vin to the common line 7 as it is in the on state, shuts off the input and output and regulates the input voltage Vin to the element withstand voltage or less in the off state. Since there is no need to provide a clamp circuit using an operational amplifier or a comparator for each input terminal 3 of each channel, if the common clamp circuit 8 is provided on the common line 7, the multiplexer 4 and The A / D converter 5 can be protected from an excessive input voltage Vin.

  By providing the multiplexer 4, a voltage higher than the power supply voltage Vdd (for example, the battery voltage VB) or an analog signal voltage that is a negative voltage can be directly input to the input terminal 3 via the resistor R1. . Further, in IC1, the layout size related to the clamp circuit can be reduced. Further, the clamp voltage at the time of input to the A / D converter 5 does not differ for each selected (turned on) channel.

In the switch circuit 10 of each channel, transistors Q1 and Q3 are provided between the input terminal 10a and the first and second nodes, respectively, and intermediate voltages VG1 and VG3 are applied to their gates in the off state. The transistors Q2, Q5, Q7, and Q13 to which the H level gate voltage is applied and the transistors Q4, Q9, Q11, and Q14 to which the L level gate voltage is applied can be protected in terms of breakdown voltage. The intermediate voltages VG1 and VG3 used here are also set so that the gates of the transistors Q1 and Q3 do not exceed the gate breakdown voltage.

  Clamp circuits 13 and 15 are provided at the first node and the second node, respectively, so that the clamp control voltages Vc1 and Vc2 satisfy the conditions of the expressions (6) and (8), respectively, when switched to the OFF state. Since it is set, it is possible to reliably prevent the transistors Q2 and Q4 from being turned on regardless of the magnitude of the input voltage Vin. In addition, since the clamp circuits 14 and 16 are provided and the clamp control voltages Vc3 and Vc4 are set so as to satisfy the conditions of the expressions (10) and (12) when switched to the OFF state, the magnitude of the input voltage Vin is increased. Regardless of this, the transistors Q2 and Q4 can be protected against breakdown voltage. Further, since the transistors Q13 and Q14 are provided at the first and second nodes, respectively, the return current from the clamp circuit 14 to the clamp circuit 13 and the return current from the clamp circuit 15 to the clamp circuit 16 are blocked in the off state. be able to.

The present invention is not limited to the embodiment described above and shown in the drawings. For example, the present invention can be modified or expanded as follows.
The above description and the voltage values shown in FIGS. 1 and 2 are examples, and can be appropriately changed under the above-described conditions.
The switch circuit 10 may be used alone or in combination with other circuits, not as a multiplexer.
The surge voltage protection circuit 6 is preferably provided in order to remove the surge voltage, but is not necessarily provided in the case of a system in which no surge voltage is generated or when a separate surge elimination measure is taken outside the IC 1. Also good.

The figure which is one Embodiment of this invention, and shows the voltage state of each part in the structure of the switch circuit in a multiplexer, and an OFF state The figure which shows the structure of a switch circuit, and the voltage state of each part in an ON state Schematic electrical configuration diagram of an IC incorporating a multi-channel A / D converter Diagram showing the configuration of the surge voltage suppressor The figure which shows the circuit structure of the analog voltage input part of a multichannel A / D converter about a prior art.

Explanation of symbols

  1 is an IC (semiconductor integrated circuit device), 3 is an input terminal, 4 is an analog multiplexer, 7 is a common line (input line), 10 is a switch circuit, 11 to 16 are clamp circuits (first to sixth clamp circuits) , Q1 to Q14 are transistors (first to fourteenth transistors), and R1 is a resistor (current limiting element).

Claims (4)

Formed in a semiconductor integrated circuit device having an input terminal to which an analog voltage is applied via a current limiting element, and the analog voltage applied to the input terminal and the input terminal is formed in the semiconductor integrated circuit device. In the switch circuit having a clamp function provided between the input line for inputting to the circuit,
P-channel first and second transistors connected in series between the input terminal and the input line;
N-channel third and fourth transistors connected in series between the input terminal and the input line;
When the input terminal and the input line are closed, a ground voltage, a ground voltage, a power supply voltage, and a power supply voltage are applied to the gates of the first , second, third, and fourth transistors, respectively. Is applied,
The power supply voltage is Vdd, the absolute value of the gate breakdown voltage of the first to fourth transistors is VGSS1 to VGSS4, the absolute value of the threshold voltage of the first to fourth transistors is Vth1 to Vth4, and the minimum of the input terminal When the voltage is expressed as Vin (min) and the maximum voltage of the input terminal is expressed as Vin (max),
When opening between the input terminal and the input line, the gates of the first and third transistors are respectively connected to the gates of the first and third transistors.

Intermediate voltages VG1 and VG3 within a range satisfying the above relationship are applied, and a power supply voltage and a ground voltage are applied to the gates of the second and fourth transistors, respectively.
further,
In the open state, a voltage VN1 at the first node, which is a common connection point between the first transistor and the second transistor, is

A first clamp circuit that performs clamp control to a voltage within a range that satisfies the relationship :
In the open state, a voltage VN2 at the second node, which is a common connection point between the third transistor and the fourth transistor, is

And a second clamp circuit that performs clamp control to a voltage within a range that satisfies the above relationship . The first clamp circuit includes:
An N-channel fifth transistor connected in series between the first node and a first clamp control node having a first clamp control voltage and a P-channel type connected between the gate and drain. A third clamping circuit comprising a sixth transistor;
An N-channel seventh transistor connected in series between the first node and a second clamp control node having a second clamp control voltage, and a P-channel type connected between the gate and drain A fourth clamp circuit comprising an eighth transistor,
The second clamp circuit includes:
A P-channel type ninth transistor connected in series between the second node and a third clamp control node having a third clamp control voltage and an N-channel type connected between the gate and drain A fifth clamp circuit comprising a tenth transistor;
An eleventh P-channel transistor connected in series between the second node and a fourth clamp control node having a fourth clamp control voltage and an N-channel type connected between the gate and drain A sixth clamp circuit composed of a twelfth transistor,
When the absolute values of the threshold voltages of the first to twelfth transistors are represented by Vth1 to Vth12,
The first and second clamp control voltages Vc1 and Vc2 are respectively

Is set to a voltage within a range that satisfies the relationship
The third and fourth clamp control voltages Vc3 and Vc4 are respectively

Is set to a voltage within a range that satisfies the relationship
A ground voltage is applied to each gate of the fifth and seventh transistors in the closed state, and a power supply voltage is applied in the open state.
2. The clamping function according to claim 1 , wherein a power supply voltage is applied to the gates of the ninth and eleventh transistors in the closed state and a ground voltage is applied in the open state. A switch circuit. The first clamp circuit includes a P-channel thirteenth transistor connected between a connection point with the third clamp circuit and a connection point with the fourth clamp circuit at the first node. With
The second clamp circuit includes an N-channel fourteenth transistor connected between a connection point with the fifth clamp circuit and a connection point with the sixth clamp circuit at the second node. With
In the closed state, a ground voltage and a power supply voltage are applied to the gates of the thirteenth and fourteenth transistors,
3. The switch circuit having a clamp function according to claim 2, wherein in the open state, a power supply voltage and a ground voltage are applied to the gates of the thirteenth and fourteenth transistors, respectively . Formed in a semiconductor integrated circuit device having an input terminal to which an analog voltage is applied via a current limiting element, and the analog voltage applied to the input terminal and the input terminal is formed in the semiconductor integrated circuit device. A plurality of switch circuits having a clamp function according to any one of claims 1 to 3 provided between input lines for inputting to the circuit, and input lines corresponding to the switch circuits are connected in common. An analog multiplexer characterized by having

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