JPH0774316A - Analog input channel circuit - Google Patents

Abstract

PURPOSE:To absorb the interference voltage generated on the first protective circuit by the second protective circuit which is formed leasing sufficient space from the diffusion for formation of the first protective circuit. CONSTITUTION:The second protective circuit 16 is provided independent of the first protective circuit, to be used for the ESD, consisting of the P4, N4, P5 and N5 formed on the region from an input terminals IN1 to IN2. A P- channel MOSFETP 11 is connected between the node 21, located in the vicinity of the CH1 pattern from the input terminal IN1 to input channel CH1, namely, on the pattern position of the CH1 separated from the input terminal, and an N-channel MOSFETN 11 is connected between the node 21 and an earth VSS. The gates of both of them are connected to source side. A P-channel MOSFETP 12, and an N-channel MOSFETN 12 are provided on the side of the input terminal IN2 in the same manner above. The second protective circuit 16 is the circuit used for absorption of the interference voltage of the first protective circuit, and a sufficient interval is provided from the diffusion generated by a parasitic bipolar transistor (NB2).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention particularly relates to an A / D which is composed of a MOS type integrated circuit and which is provided with a plurality of analog input terminals.
The present invention relates to an analog input channel circuit in a converter.

[0002]

2. Description of the Related Art An analog input channel circuit provided in an A / D converter also has a function of reliably blocking noise when an analog signal input from an input terminal has noise. This leads to improvement in A / D conversion accuracy.

FIG. 2 is a circuit diagram showing the configuration of a conventional analog input channel circuit. P channel MOS FET P1,
P2 and N-channel MOS FETs N1 and N2 are respectively connected in two stages in series. The two stages in series are connected in parallel so as to face each other. The control signal PHI-1 is supplied to the gates of N1 and N2, and the control signal BPHI-1 obtained by inverting PHI-1 is supplied to the gates of P1 and P2.

An N-channel MOS FET N is provided between the node 13 at the connection point of the MOS FETs P1 and P2 and the ground voltage VSS.
3 current paths are connected. The control signal BPHI-1 is supplied to the gate of this N3. Also, the above MOS FET N1
, N2 connected in series between the node 14 and the power supply voltage VCC, the current path of the P-channel MOS FET P3 is connected. The control signal PHI-1 is supplied to the gate of P3.

One node 11 of the parallel connection points of the two stages of the MOS FET series is connected to the input terminal IN1 and the other terminal 12 is connected to the common line 15. Such a structure constitutes one input channel CH1 to which an analog signal is input to the input terminal IN1. CH adjacent to this
Multiple input channels similar to 1 are formed. For example, in CH2, a predetermined analog signal is input from the input terminal IN2 via the node 11, control signals PHI-2 and BPHI-2 are supplied, and the analog signal is connected to the common line 15 through the other terminal 12. .

The operation of the above circuit is as follows. For example, when the channel CH2 is selected, the channel CH1 is closed. That is, the control signals PHI-1, BPHI-1
Causes P3 and N3 to turn on and N1, N2, P1 and P2 to turn off, and node 14 is set to VCC and node 13 is set to VSS. When selecting channel CH1, select channel C
H2 was closed in the same manner as above, and the analog input from the selected channel was taken into the common line 15.

According to the circuit having the above-mentioned configuration, even if a voltage exceeding the power supply voltage range is input to the input channel in the non-selected state, the parasitic lateral bipolar transistor operates in the MOS FETs P1 and N1 to input the non-selected input. The effect on the common line 15 from the channel was canceled.

By the way, the analog switch pin is ES
A D (electro-static discharge) protection circuit is connected, for example, as shown in FIG. 3 from the input terminals IN1 to IN2. Each channel CH1, C
H2 was blocked.

In FIG. 3A, a P-channel MOS FETP4 and an input terminal IN1 are provided between the input terminal IN1 and the power supply VCC.
An N-channel MOS FET N4 is connected between the ground and VSS. In both cases, the gate is connected to the respective source side. Similarly, on the input terminal IN2 side, a P-channel MOS FET P5 is connected to the power supply VCC, and an N-channel MOS FET N5 is connected to the ground VSS, and the gates of both are connected to their respective source sides. There is a problem that the protection circuit having such a configuration directly affects the input terminals instead of the common line 15, which will be described below.

A voltage Vin lower than VSS is applied to the input terminal IN1.
(<0V) is input and the other input terminal IN2
Take 0V as an example (Fig. 3). In this case, the input channel CH1 connected to IN1 is not selected, and the input channel CH2 connected to IN2 is selected. Then, the parasitic lateral bipolar transistor NB1 of the protection transistor N4 operates to generate the current I1 to absorb the influence on the input channel.

However, at the same time, another lateral bipolar transistor NB2 is formed between the drain of N5 on the IN2 side and operates. This gives I
A current path of 2 occurs and the pad potential of IN2 drops below 0V. Further, FIG. 3B is the same as FIG.
It is sectional drawing which showed the part which the parasitic bipolar transistor of (a) generate | occur | produces as a more concrete structure.

At this time, since the input channel on the IN2 side is selected, the common line on which 0V should be originally transmitted.
The potential of 15 drops below 0V. In addition, this phenomenon occurs more prominently as the protection transistors are closer to each other.

[0013]

As described above, in the related art, the protection transistors of the analog signal input terminals interfere with each other between adjacent selected and non-selected input terminals, and an interference voltage is generated on the common line of the analog signals. It has the drawback of appearing.

The present invention has been made in view of the above circumstances, and an object thereof is to provide an analog input channel circuit having a function of preventing an interference voltage in the operation of protection transistors.

[0015]

An analog input channel circuit according to the present invention includes a plurality of analog signal input terminals, and analog input circuits respectively provided between the analog signal input terminals and the common transmission path led into the circuit from the input terminals. A first protection circuit including a MOS transistor added in parallel to the input terminal, and a pattern provided between the first protection circuit and the analog input circuit and having the same pattern as the analog input circuit The second protection circuit having the same circuit configuration as the first protection circuit existing at the position is provided.

[0016]

According to the present invention, the interference voltage generated in the first protection circuit is absorbed by the second protection circuit which is sufficiently spaced from the diffusion forming the first protection circuit.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing the configuration of an analog input channel circuit according to an embodiment of the present invention. The configuration of each input channel CH1 and CH2 to which an analog signal is input to the input terminals IN1 and IN2 is similar to that of FIG.

In this embodiment, the input terminal IN1 shown in FIG.
To MOSFETs P4, N4, P5 constructed from
, N5, a second protection circuit 16 is provided separately from the ESD protection circuit.

That is, in FIG. 1, the P-channel MO is provided between the node 21 and the power supply VCC in the vicinity of the pattern of CH1 in which the input channel CH1 is connected to the input terminal IN1, that is, in the pattern position of CH1 distant from the input terminal IN1.
S FET P11, N channel MO between node 21 and ground VSS
S FET N11 is connected. In both cases, the gate is connected to the respective source side. Similarly, on the input terminal IN2 side, a P-channel MOS FET is provided between the node 21 and the power supply VCC at the pattern position of CH2 which is near the CH2 pattern where the input channel CH2 is connected from the input terminal IN2.
N channel MOS FET between P12, node 21 and ground VSS
N12 is connected. In both cases, the gate is connected to the respective source side.

The second protection circuit 16 is a circuit for absorbing the interference voltage of the first protection circuit, and it is necessary to keep a sufficient distance from the diffusion generated by the parasitic bipolar transistor (NB2) when the noise voltage is applied. . Specifically, the input terminal IN
The same distance as between 1 and IN2 pads (eg 100μ
m) Yes.

The operation of the second protection circuit 16 is as follows. When noise lower than VSS, for example, is applied to N1 in FIG. 1, a parasitic lateral bipolar transistor NB2, which causes a problem as in the case of FIG. Descends.

Since N12 in the second protection circuit 16 which is not affected by NB2 is also connected to IN2,
A parasitic lateral bipolar transistor NB3 is generated. As a result, the potential drop to the internal CH12 is absorbed starting from the node 21 on the CH12 side.

In this case, however, N12 is sufficiently V to promote the generation of the parasitic lateral bipolar transistor NB3.
It is necessary that B> VD (VB is the substrate voltage and VD is the drain voltage). Further, the MOS FE which constitutes the second protection circuit 16
Since the effect can be obtained without increasing the gm (transconductance) of T so much, there is not much change compared with the conventional pattern area, so there is no difficulty in forming.

[0024]

As described above, according to the present invention,
Since the interference voltage generated in the first protection circuit is absorbed by the second protection circuit, if the A / D converter is used, the A / D
An analog input channel circuit that contributes to improvement of conversion accuracy can be provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional analog input channel circuit.

FIG. 3 is a circuit diagram showing the configuration of a part of the protection circuit in FIG.

[Explanation of symbols]

15 ... Common line, 16 ... Second protection circuit, P1, P2, P
3, P4, P5, P11, P12 ... P-channel MOS FET, N
1, N2, N3, N4, N5, N11, N12 ... P-channel MOS FET, CH1, CH2 ... Input channel, IN1
, IN2… Input channel.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03K 17/08 D 9184-5J H03M 1/12 A

Claims (1)

[Claims] 1. A plurality of analog signal input terminals, an analog input circuit introduced from the input terminals into the circuit and provided between a common transmission path, and a MOS transistor added in parallel to the input terminals. And a first protection circuit which is provided between the first protection circuit and the analog input circuit and which is present at the same pattern position as the analog input circuit. An analog input channel circuit comprising a second protection circuit having a circuit configuration.