JP4121732B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gaming machine, and more particularly to a gaming machine including a sub-control board having a memory for writing command data from a main control board.
[0002]
[Prior art]
In general, gaming machines may malfunction due to the influence of static electricity or external noise. When this malfunction occurs, it is necessary to detect it at an early stage, and to take measures to restore the normal operation and continue the game. As this countermeasure, for example, there is one using a known watchdog circuit.
A return countermeasure in a conventional gaming machine will be described with reference to FIG. As shown in the figure, the conventional gaming machine includes a main control board 100 provided with a main control CPU 10, and a sub control board 200 provided with a sub control CPU 20, ROM 21, RAM 22, and a watchdog circuit 23. , Including.
[0003]
In the ROM 21, data necessary for the operation of the sub control CPU 20 is written in advance. Various data are written into the RAM 22 during the operation of the sub-control CPU 20. Data transfer between the sub-control CPU 20 and the ROM 21 and RAM 22 is performed via the data bus B.
The sub-control CPU 20 receives the command data CMD output from the main control CPU 10 and the command strobe signal STB indicating that the command data CMD is valid, and controls to write the contents of the command data CMD into the RAM 22. . When the sub-control CPU 20 is operating normally, the write signal WR1 is given to the RAM 22, and correct command data is written to the RAM 22. The command data CMD is, for example, 8-bit data.
[0004]
The watchdog circuit 23 includes a timer circuit (not shown) therein, and the time value of this timer circuit is reset by a watchdog timer pulse signal P sent from the sub-control CPU 20. When the time value of the timer circuit reaches a predetermined value without being reset, the watchdog circuit 23 outputs a reset signal RST. When the reset signal RST is input to the sub control CPU 20, the sub control CPU 20 is reset.
[0005]
In such a configuration, when the watchdog timer pulse signal P is normally sent from the sub control CPU 20 to the watchdog circuit 23, the watchdog circuit 23 is reset at predetermined time intervals. For this reason, the watchdog circuit 23 does not output a reset signal RST for resetting the sub control CPU 20. Therefore, the sub-control CPU 20 can continue normal operation as it is.
[0006]
On the other hand, when the sub control CPU 20 is not operating normally, such as when the control CPU 20 runs away, the watch dog timer pulse signal P is not normally sent from the sub control CPU 20 to the watch dog circuit 23. In this case, the watchdog circuit 23 is not reset by the watchdog timer pulse signal P. For this reason, the watchdog circuit 23 outputs a reset signal RST. When the reset signal RST is input to the sub control CPU 20, the sub control CPU 20 is reset. The reset sub-control CPU 20 outputs a read signal (not shown), reads the command data stored in the RAM 22, and returns the operation according to the stored contents.
[0007]
Similarly, Japanese Patent Laid-Open No. 11-99252 also shows a configuration for returning a gaming machine to normal operation by a watchdog circuit.
[0008]
[Problems to be solved by the invention]
In the above-described conventional gaming machine, when runaway is detected by the watchdog circuit, the initial activation is performed by a reset signal, and when returning to the state by the previously received command, the stored contents of the RAM are destroyed due to erroneous writing due to CPU runaway. However, there is a drawback that it may not be able to return to normal. This disadvantage cannot be solved even by the technique described in the above patent publication.
[0009]
The present invention has been made to solve the above-described drawbacks of the prior art, and an object of the present invention is to provide a gaming machine that can return its operation normally and easily even if it malfunctions.
[0010]
[Means for Solving the Problems]
A gaming machine according to the present invention includes a main control unit that outputs a signal indicating command data and a command signal that enables writing of the command data to a memory, a signal indicating the command data output by the main control unit, and the A command signal is input, a write signal for enabling writing of the command data to the memory is output based on the input command signal, and the command data indicated by the input signal indicating the command data is output as the command data. A sub-control unit that writes to a memory, wherein the command signal output by the main control unit and the write signal output by the sub-control unit are input, the input command signal and the When both the write signals indicate that the command data is valid to be written to the memory, the memory in the memory is Characterized in that it comprises a write control means for permitting the writing of the command data by the control unit. Then, the write control means calculates a logical product of the command signal indicating a state in which writing of the command data to the memory is effective and the write signal indicating a state in which writing of the command data to the memory is effective. It is characterized by comprising an output AND gate .
[0011]
By doing so, it is possible to prevent the command data in the RAM from being destroyed due to erroneous writing due to the runaway of the CPU, and to easily return the gaming machine to normal operation.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. In each drawing referred to in the following description, the same reference numerals are given to the same parts as in the other drawings.
FIG. 1 is a block diagram showing a configuration of a main part of a gaming machine according to an embodiment of the present invention. As shown in the figure, unlike the conventional gaming machine, the gaming machine according to the present embodiment has a dedicated command storage memory 24 for storing the command data CMD received by the sub-control CPU 20, and this An AND gate 25 is provided to enable writing to the command storage memory 24 only when command data CMD is received.
[0013]
The AND gate 25 receives a command strobe signal STB output from the main control CPU and a write signal WR1 output from the sub control CPU 20. The AND gate 25 makes the write signal WR2 to the command storage memory 24 valid only when both the command strobe signal STB and the write signal WR1 are valid. Even if the sub control CPU 20 malfunctions and outputs the write signal WR1 by the AND operation by the AND gate 25, the command storage memory is not used unless the command strobe signal STB indicating the validity of the command data is valid. No writing to 24 is performed.
[0014]
In other words, this gaming machine is a gaming machine including a sub-control board having a memory for writing command data from the main control board, and the command data write operation is input to a command from the main control board. An AND gate is provided as a write control means to be permitted accordingly. The command from the main control board is a command strobe signal, and the AND gate performs the write operation only when the command is input and the write signal is output from the control circuit in the sub control board. It outputs a signal to allow.
[0015]
Therefore, if the configuration shown in FIG. 1 is adopted, command data is not destroyed, and valid command data is always stored in the command storage memory 24. Therefore, by using this effective command data, the operation of the gaming machine can be restored normally and easily.
In this example, command data is stored in a dedicated memory 24. Although an area in the RAM 22 can be used for storing commands, using the dedicated memory 24 as in this example has the advantage that the circuit configuration is not complicated.
[0016]
Further, description will be made with reference to FIG. This figure is a timing chart showing the operation of the gaming machine shown in FIG. In the figure, a command strobe signal STB, command data CMD, command data to the command storage memory 24, and write signals WR1 and WR2 are shown.
In the figure, the sub control CPU 20 starts a reception interrupt at the rising edge (t1) of the command strobe signal STB from the main control CPU 10. While the command strobe signal STB being high level (HIGH level) is being input to the AND gate 25, the sub control CPU 20 can write to the memory 24.
[0017]
In this state, the sub control CPU 20 receives the command data CMD from the main control CPU 10 and writes the received command data CMD into the command storage memory 24. In this case, the write signal WR2 becomes high level only during the period t2 when the write signal WR1 is high level, and the command data CMD is written into the command storage memory 24 only during this period t2.
Thereafter, when the command strobe signal STB from the main control CPU 10 becomes a low level (LOW level) (t3), the write signal WR2 remains at a low level due to the logical product in the AND gate 25. For this reason, the sub control CPU 20 cannot write to the memory 24. Therefore, even if the sub-control CPU 20 malfunctions and outputs the write signal WR1, the write signal WR2 remains at the low level, so that the command storage memory 24 is not written. Therefore, the command data is not destroyed, and valid command data is always stored in the command storage memory 24.
[0018]
As described above, when storing the command data used for returning the operation of the gaming machine in the dedicated memory, write to the memory is permitted only when the strobe signal is output from the main control board side. Accordingly, it is possible to prevent the command data written in the memory from being destroyed and to restore the operation of the gaming machine normally and easily.
[0019]
【The invention's effect】
As described above, the present invention provides a main control unit that outputs a command data signal and a command signal that enables writing of the command data to the memory, and a signal that indicates the command data output by the main control unit. And a command signal that is input by the command signal, outputs a write signal that validates the writing of the command data to the memory based on the input command signal, and is indicated by a signal indicating the input command data A sub-control unit that writes the command signal to the memory, the command signal output from the main control unit and the write signal output from the sub-control unit are input, and the command signal is input And when the write signal indicates that the command data is effectively written to the memory, By providing a write control means for permitting the writing of the command data by serial sub-control unit, even when the gaming machine malfunctions, there is an effect that it is possible to return the operation successfully and easily.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration for countermeasures against malfunctions in a gaming machine according to the present invention.
FIG. 2 is a timing chart showing the operation of each part in FIG. 1;
FIG. 3 is a block diagram showing a configuration for countermeasures against malfunctions in a conventional gaming machine.
[Explanation of symbols]
10 Main control CPU
20 Sub-control CPU
21 ROM
22 RAM
23 Watchdog circuit 24 Command storage memory 25 AND gate 100 Main control board 200 Sub control board B Data bus CMD Command data P Watchdog timer pulse signal RST Reset signal STB Command strobe signals WR1, WR2 Write signal

Claims (2)

A main control unit for outputting a signal indicating command data and a command signal for enabling writing of the command data to the memory;
A signal indicating the command data output by the main control unit and the command signal are input, and a write signal for enabling writing of the command data to the memory is output based on the input command signal, and input A sub-control unit that writes command data indicated by the signal indicating the command data to the memory;
A gaming machine comprising
The command signal output from the main control unit and the write signal output from the sub-control unit are input, and both the input command signal and the write signal are valid to write the command data to the memory , A gaming machine comprising a writing control means for permitting writing of the command data by the sub-control unit in the memory . The write control means outputs a logical product of the command signal indicating a state where writing of the command data to the memory is valid and the write signal indicating a state where writing of the command data to the memory is valid. The gaming machine according to claim 1, wherein the gaming machine is configured by an AND gate .

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