JPH1063584A - Cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent MPU(microprocessor) from malfunction even when a cache memory erroneously recognizes noise inputted to an address bus to be an address signal. SOLUTION: A register 9 returning an output address signal OA inputted to the cache memory 17 through the address bus 12 to MPU 16 as it is as a return address signal RA is provided in the cache memory 17, and a comparing controller 11 preventing the fetching of a data signal DQ read from the cache memory 17 unless the return address signal RA is coincident with the output address signal OA actually outputted by MPU 16 is provided within MPU 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a cache memory system, and more particularly, to a cache memory system having a function of preventing malfunction due to address noise.

[0002]

2. Description of the Related Art A typical conventional cache memory system includes a microprocessor (M) as shown in FIG.
PU) 1 and a static random access memory (S
A random access memory (DRAM); and a cache memory 2 composed of a dynamic random access memory (DRAM). The MPU 1, the cache memory 2, and the main memory 4 are interconnected by an address bus 5 and a data bus 6. The cache memory system further includes a bridge 3 for synchronizing the MPU 1 operating at 133 MHz with the main memory 4 operating at 66 MHz.

The MPU 1 outputs an address signal for reading / writing data. If there is data at a corresponding address in the cache memory 2, the cache memory 2
The data is read from. If there is no data at the corresponding address in the cache memory 2, the main memory 4
The data is read from.

[0004]

By the way, in the future, MP
It is expected that the operating frequency of U1 will be higher and the amplitude of the address signal will be smaller. Therefore, when noise enters the address bus 5, the cache memory 2 may erroneously recognize the noise as an address signal. In this case, the cache memory 2 outputs an erroneous data signal in response to the noise, and the MPU 1
However, there may arise a problem that the erroneous data signal is captured.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a cache memory system which does not malfunction in response to address noise.

[0006]

A cache memory system according to the present invention comprises an MPU for outputting an address signal.
A cache memory that outputs a data signal in response to an address signal output from the MPU, and an address bus for transferring the address signal output from the MPU to the cache memory; The cache memory includes an output unit that outputs a signal input via an address bus to the MPU,
The MPU includes a prohibition unit that prohibits the input of the data signal output from the cache memory when the signal output from the output unit does not match the address signal.

The output means preferably includes a first register circuit for temporarily storing a signal input via the address bus.

[0008] The prohibiting means preferably includes a comparing means for comparing a signal output from the output means with an address signal;
The input of the data signal output from the cache memory is permitted when the signal output from the output means matches the address signal, and the data signal output from the cache memory when the signal output from the output means does not match the address signal. Means for prohibiting the input of a password.

The comparing means preferably includes an exclusive-OR circuit for receiving one bit of the signal output from the output means and one bit of the address signal corresponding to the one bit, and an output from the exclusive-OR circuit. A second register circuit for temporarily storing the output signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to FIGS. In the drawings, the same reference numerals indicate the same or corresponding parts.

Referring to FIG. 1, a cache memory system according to an embodiment of the present invention includes a plurality of basic blocks 15 each including an MPU 16 and a cache memory 17, a main memory 4, and an operating frequency of the basic block 15. A bridge 3 for synchronizing with the operating frequency of the memory 4. The plurality of basic blocks 15 and the main memory 4 are interconnected by the address bus 5 and the data bus 6 via the bridge 3.

Each basic block 15 includes an output address bus 12 for connecting the MPU 16 to the cache memory 17 in addition to the MPU 16 and the cache memory 17.
A return address bus 13 and a data bus 14 are included. The output address bus 12 transfers the output address signal OA from the MPU 16 to the cache memory 17. The return address bus 13 transfers a later-described return address signal RA from the cache memory 17 to the MPU 16. Data bus 14 transfers data signal DQ between MPU 16 and cache memory 17 mutually.

The MPU 16 has a register 10 for temporarily storing an output address signal OA to be output, and a comparison controller 1 for inhibiting input of the data signal DQ when the return address signal RA does not match the output address signal OA.
1 is included.

The cache memory 17 receives an address signal OA in response to an address status signal / ADS, and an SRA which outputs a data signal DQ in response to the output address signal OA.
It includes an M core 8 and a register 9 for temporarily storing the taken output address signal OA and returning it to MPU 16 as a return address signal RA. SRAM
The core 8 includes a static memory cell array and its peripheral circuits.

The above-described comparison controller 11 is, for example, shown in FIG.
2, a plurality of exclusive OR (EXOR) circuits 18, a NOR circuit 19 receiving output signals from the plurality of EXOR circuits 18, and a NOR circuit 19 in response to a control signal CT. And a data fetch control unit 21 for temporarily accepting or inhibiting the input of the data signal DQ from the cache memory 17 in response to the output signal from the register 20. Here, each EXOR circuit 18 outputs a corresponding one-bit output address signal OAi (i = 0 to n) and a corresponding one-bit return address signal RAi (i = 0 to i).
n).

Next, the operation of the cache memory system configured as described above will be described with reference to the timing chart of FIG.

The cache memory 17 operates in response to the clock signal CLK shown in FIG. Therefore, the cycle of clock signal CLK (for example, T1-T0) corresponds to the operation cycle of cache memory 17.

The register 10 in the MPU 16 is shown in FIG.
Output address signal OA as shown in FIG. 3 and address status signal / as shown in FIG.
When ADS is activated to L (logic low) level, address buffer 7 takes in output address signal OA during the activation period of address status signal / ADS. Address buffer 7 applies the received output address signal OA to SRA
The signal is supplied to the M core 8 and also to the register 9. In response to the output address signal OA, the SRAM core 8 outputs the data signal DQ at time T3 as shown in FIG.

Prior to outputting the data signal DQ, the register 9 outputs a return address signal RA at time T2 as shown in FIG. Therefore, not only the output address signal OA from the register 10 but also the return address signal RA from the register 9 is supplied to the comparison controller 16. The return address signal RA completely matches the output address signal OA supplied from the register 10, since the output address signal OA is supplied as it is via the address buffer 7 and the register 9.

Therefore, the comparison controller 1 shown in FIG.
All the output signals of the EXOR circuit 18 in 1 become L level. Therefore, H (logic high) from the NOR circuit 19
The output signal of the level is stored in the register 20. In response to the H-level output signal from register 20, data capture control unit 21 is closed. Therefore, the data signal DQ from the SRAM core 8 is supplied to the arithmetic unit in the MPU 16 via the data acquisition control unit 21.

On the other hand, even if the register 10 in the MPU 16 does not output the output address signal OA, if noise enters the address bus 12 at time T1, the address buffer 7
Supplies the noise to the SRAM core 8 and the register 9 similarly to the output address signal OA described above. Therefore, M
Although the PU 16 is not outputting the output address signal OA, the SRAM core 8 outputs an erroneous data signal DQ in response to the noise.

Prior to the output of the erroneous data signal DQ, the register 9 in the cache memory 17 outputs the noise as it is as the return address signal RA.
The return address signal RA is supplied to the comparison controller 11, but the register 10 does not output the output address signal OA.
Does not match the output address signal from OA. Therefore, the EXOR circuit 1 in the comparison controller 11 shown in FIG.
At least one output signal from H.8 goes to H level.
Therefore, an L-level output signal from NOR circuit 19 is stored in register 20. Data acquisition control unit 21
Is opened in response to an L level output signal from the register 20. Therefore, the erroneous data signal DQ from the cache memory 17 is cut off by the data acquisition control unit 21 and is not supplied to the inside of the MPU 16.

According to the above-described embodiment, the signal input via the address bus 12 is output to the MPU, and it is confirmed whether the signal is the actual output address signal OA output from the MPU 16 or not. As a result, the data signal DQ output from the cache memory 17 is not input to the MPU 16 unless it is the actual output address signal OA. Therefore, even if noise enters address bus 12, erroneous data signal DQ from cache memory
It is not input to PU16. With this, MPU
16 does not malfunction in response to an erroneous data signal.

The output address signal OA is supplied to the register 9
Is temporarily output as a return address signal RA after being temporarily stored in the register 10, so that the output address signal OA from the register 10 always returns to the corresponding return address signal R
A is compared with A.

In the comparison controller 11, the output signal of the NOR circuit 19 is temporarily stored in the register 20, so that the input of the data signal DQ corresponding to the compared output address signal OA and return address signal RA is controlled. Is done.

[0026]

According to the cache memory system of the present invention, the signal input to the cache memory via the address bus is output to the MPU, and the signal is output to the MPU.
If the address signal does not match the output signal, the input of the data signal output from the cache memory is prohibited.
Even if noise enters the address bus, the MPU does not take in an erroneous data signal and does not malfunction.

Since the signal input to the cache memory via the address bus is temporarily stored in the register circuit, the signal input to the cache memory via the address bus is always compared with the corresponding address signal. Is done.

The signal input to the cache memory via the address bus is compared with the address signal output from the MPU. If the signal matches, the input of the data signal from the cache memory is permitted. Input of the data signal from the MPU is prohibited, so that even if noise enters the address bus, the MPU does not take in the wrong data signal and malfunction.

The signal input to the cache memory via the address bus is output from the exclusive OR circuit to the MPM.
Since the output signal from the exclusive OR circuit is temporarily stored in the register circuit, the data signal corresponding to the address signal is always accurately transferred from the cache memory to the MPU. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a cache memory system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a comparison controller in FIG. 1;

FIG. 3 is a timing chart showing an operation of the cache memory system of FIG. 1;

FIG. 4 is a block diagram showing a configuration of a conventional cache memory system.

[Explanation of symbols]

5 address bus, 8 SRAM core, 9, 10, 20
Register, 11 comparison controller, 12 address bus,
16 MPU, 17 cache memory, 18 EXOR
Circuit, 21 data acquisition control unit, OA output address signal, RA return address signal DQ data signal.

Claims (4)

[Claims] An MPU that outputs an address signal; a cache memory that outputs a data signal in response to the address signal output from the MPU; and an MPU that transfers the address signal output from the MPU to the cache memory. A cache memory system comprising: an output bus that outputs a signal input through the address bus to the MPU, wherein the MPU is output from the output unit. A cache memory system including a prohibition unit for prohibiting the input of a data signal output from the cache memory when the signal does not match the address signal. 2. The cache memory system according to claim 1, wherein said output means includes a first register circuit for temporarily storing a signal input via said address bus. 3. The prohibition means includes: a comparison means for comparing a signal output from the output means with the address signal; and an output from the cache memory when a signal output from the output means matches the address signal. And means for permitting input of the data signal output from the cache memory when the signal output from the output unit does not match the address signal. Cache memory system. 4. The exclusive OR circuit receiving one bit of the signal output from the output means and one bit of the address signal corresponding to the one bit, and the exclusive OR circuit. And a second register circuit for temporarily storing an output signal from the cache memory.