JP4121582B2 - Circuit member for semiconductor device, semiconductor device using the same, and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a circuit member for a surface-mount type resin-encapsulated semiconductor device having a circuit portion thinly formed by plating, a semiconductor device using the circuit member, and a method of manufacturing the same. The present invention relates to a circuit member for a PBGA (Plastic Ball Grid Array) type semiconductor device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, semiconductor devices have become increasingly highly integrated and highly functional, as represented by LSI ASICs, due to the trend toward higher performance and lighter and thinner electronic devices (current).
In a highly integrated and highly functional semiconductor device, for high-speed signal processing, the inductance in the package cannot be ignored. In order to reduce the inductance in the package, the power supply and ground We have responded by increasing the number of connection terminals and reducing the substantial inductance.
For this reason, higher integration and higher functionality of semiconductor devices have resulted in an increase in the total number of external terminals (pins), and more and more terminals (pins) have been required.
For semiconductor devices such as multi-terminal (pin) ICs, particularly ASICs typified by gate arrays and standard cells, microcomputers, DSPs (Digital Signal Processors), etc., QFP (Quad Flat Package) ) And the like are used, and in the QFP, even a 300-pin class package has come into practical use. QFP uses a single-layer lead frame 1310 shown in FIG. 14B. As shown in a sectional view of FIG. 14A, a semiconductor element 1320 is mounted on a die pad 1311, and silver plating, gold plating is performed. The inner lead tip portion 1312A subjected to the treatment such as plating and the terminal (electrode pad) 1321 of the semiconductor element 1320 are connected by a wire 1330, then sealed with a resin 1340, the dam bar portion is cut, and the outer lead 1313 portion Is made by bending it into a gull wing shape. Such a QFP has a structure in which outer leads for electrical connection with an external circuit are provided in four directions of the package, and has been developed as one that can cope with the increase in the number of terminals (pins). The single-layer lead frame 1310 used here is usually an etching using a photolithographic technique for a metal plate having excellent conductivity and high strength such as Kovar, 42 alloy (42% Ni-iron), copper-based alloy and the like. It was fabricated by processing into a shape as shown in FIG. 14B by a processing method, a stamping method, or the like.
[0003]
However, the recent increase in signal processing speed and performance (function) of semiconductor elements requires more terminals.
On the other hand, QFP can cope with further increasing the number of terminals by narrowing the external terminal pitch. However, when the external terminals are narrowed, it is necessary to reduce the width of the external terminals themselves, thereby reducing the strength of the external terminals. Will be allowed to. As a result, a problem occurs in the position accuracy or flatness accuracy of terminal molding (gull wing). Also, in QFP, as the pitch of the outer leads is further reduced to 0.4 mm and 0.3 mm, the mounting process of these narrow pitches becomes difficult, and advanced board mounting technology must be realized. Have a disability (problem).
[0004]
In order to avoid the mounting efficiency and mountability problems associated with these conventional QFP packages, a plastic package semiconductor device called BGA (Ball Grid Array), which is a surface mount type package in which solder balls are replaced with external terminals of the package, has been developed. It has been.
BGA is a general term for a surface mount semiconductor device (plastic package) in which external terminals are solder balls arranged in a matrix (array) on the back surface.
Usually, in order to increase the number of input / output terminals, this BGA has a semiconductor element mounted on one side of a double-sided wiring board, an external terminal electrode having a spherical solder attached on the other side, and the semiconductor element through the through hole. It was connected to the external terminal electrode. By arranging the spherical solder in an array, the terminal pitch interval can be made wider than that of a conventional semiconductor device using a lead frame. As a result, the mounting process of the semiconductor device is not made difficult and the number of input / output terminals is increased. We were able to cope with.
The BGA generally has a structure as shown in FIG. FIG. 9B is a view as seen from the back surface (substrate) side of FIG. 9A, and FIG. 9C shows the through-hole 850 portion. This BGA is electrically connected to a die pad 805 on which a semiconductor element 801 is mounted on one side of a base 802 of a heat-resistant flat plate (resin plate) typified by BT resin (bismaleimide resin) and a bonding wire 808 from the semiconductor element 801. An external connection terminal 806 formed by a solder ball arranged in a lattice shape or a staggered manner for electrical and physical connection between an external circuit and a semiconductor device is provided on the other surface. In this structure, the external connection terminal 806 and the bonding pad 810 are electrically connected by the wiring 804, the through hole 850, and the wiring 804A.
However, in this BGA, a circuit for connecting wires to a semiconductor element to be mounted and an external terminal electrode for mounting on a printed circuit board after being formed into a semiconductor device are provided on both surfaces of the base material 802, and these are provided through holes 850 The through hole 850 may be disconnected due to the effect of thermal expansion of the resin, and there are many problems in terms of production reliability.
[0005]
For this reason, in order to simplify the manufacturing process and avoid a decrease in reliability, in addition to the structure shown in FIG. 9 described above, PBGA (Plastic Ball Grid Array) in which a circuit is formed using a lead frame as a core material has recently been developed. Various proposals have been made.
A PBGA package using these lead frames generally fixes the entire lead frame 910 on an insulating fixing film 960 in which predetermined holes are formed at locations corresponding to the external terminal portions 914 of the lead frame 910. Then, the structure as shown in FIG. 10A with resin sealing or the structure as shown in FIG. 10B with the inner leads fixed with a fixing tape 960A was adopted.
[0006]
In the lead frame 910 used here, both the external terminal portion 913 and the inner lead 912 are made to the thickness of the lead frame material, and after the outer shape processing by etching, as shown in FIG. The support lead 915 for supporting the external terminal portion and the dam bar is provided with a connecting portion 917 that is integrally connected to the inner lead and is connected to the inner lead and is fixed to each other. (Frame part) 914 was connected.
In the case of the semiconductor device 900 shown in FIG. 10A, as shown in FIG. 11, the entire lead frame (FIG. 11A) is fixed with the fixing film 960 (FIG. 11B). Then, the connecting portion 917 for connecting the inner leads which are originally unnecessary is removed by pressing to obtain a lead frame member 970 including a lead frame 910 and a fixing film 960 as shown in FIG. It was. Reference numeral 920 denotes an opening. For this reason, an expensive metal mold is required to produce the lead frame member 970, and the productivity is not good.
On the other hand, in the case of the semiconductor device 900A shown in FIG. 10B, not only the entire lead frame but also a part including the inner lead is fixed by the fixing tape 960A and the inner leads are connected to each other (not shown). The lead frame member 970A composed of the lead frame 910 and the fixing tape 960A is obtained, but an expensive mold is necessary for the production of the lead frame member 970A, and the productivity is reduced. But it was n’t good.
Further, when the lead frame member 970 shown in FIG. 11C is used, or when the lead frame member 970A (FIG. 10B) in which a part of the lead frame is fixed is used, the semiconductor device is manufactured. As shown in FIG. 12, it is necessary to remove the dam bar (frame portion) 914 after resin sealing and separate the support leads 915 supporting the external terminal portion from each other, and the frame portion is cut and removed by a mold. Therefore, expensive molds are also necessary, and productivity is not good.
[0007]
In such a BGA type resin-encapsulated semiconductor device using a lead frame as a core material, an external circuit is connected with the same number of terminals as compared to the semiconductor device using a single-layer lead frame shown in FIG. The external terminal pitch for connection could be widened, and the mounting process of the semiconductor device was not made difficult, and it was possible to cope with the increase in the number of input / output terminals. The response was required.
In order to cope with this, an etching processing method has been proposed in which the inner lead portion is formed thinner than the lead frame material to achieve a narrow pitch.
An example of this etching method will be described with reference to FIG.
For simplicity, here, a case where a lead frame in which only the inner lead is made thinner than a lead frame material made of a copper alloy will be described.
FIG. 13 is a cross-sectional view of each step of the inner lead tip portion formed in a thin shape.
In addition, about the part which carries out an external shape process with the thickness of a lead frame raw material, the resist pattern of substantially the same shape and size is formed on both surfaces of a lead frame raw material, and it etches.
In FIG. 13, 1210 is a lead frame material, 1210A is a thin portion, 1220A, 1220B is a resist pattern, 1230 is a first opening, 1240 is a second opening, 1250 is a first recess, and 1260 is a second portion. A recess, 1270 is a flat surface, 1280 is an etching resistance layer (filler layer), and 1290 is an inner lead.
First, after cleaning and degreasing both sides of a lead frame material made of a strip-like plate with a thickness of 0.15 mm, a resist made of a mixed solution of casein aqueous solution using potassium dichromate as a photosensitizer is applied on both sides. After applying and drying the resist, predetermined areas of the resist on both sides of the lead frame material are exposed using a predetermined pattern plate, and development processing is performed, so that first openings 1230 and second openings having predetermined shapes are formed. Resist patterns 1220A and 1220B having 1240 are formed. (Fig. 13 (a))
The first opening 1230 is for corroding the lead frame material 1210 in a solid form from the opening in a later etching process and thinner than the lead frame material 1210. The second opening 1240 of the resist is This is for forming the shape of the tip of the inner lead.
Next, using a ferric chloride solution having a liquid temperature of 50 ° C. and a specific gravity of 46 Baume, a spray pressure of 3.0 kg / cm ² Then, the both sides of the lead frame material 1210 on which the resist pattern is formed are etched, and the etching is performed when the depth h of the first recess 1250 corroded in a solid shape (flat shape) reaches a predetermined depth. stop. (Fig. 13 (b))
The reason for simultaneously etching from both sides of the lead frame material 1210 in the first etching is to shorten the second etching time to be described later by etching from both sides, so that the one-side etching only from the resist pattern 1220B side is performed. Compared to the case, the total time of the first etching and the second etching is shortened.
[0008]
Next, an etching-resistant resin as an etching resistance layer 1280 was applied to the corroded first concave portion 1250 on the first opening 1230 side using a die coater, and was etched into a solid shape (flat shape). Embedded in the first recess 1250. The resist pattern 1220B is also applied to the etching resistance layer 1280. (Fig. 13 (c))
Although it is not necessary to apply the etching resistance layer 1280 to the entire surface of the resist pattern 1220B, it is difficult to apply the etching resistance layer 1280 only to a part including the first recess 1250. Therefore, as shown in FIG. The etching resistance layer 1280 is applied to the entire surface of the first opening 1230 together with the recess 1250.
The resin of the etching resistance layer 1280 is basically resistant to an etching solution and preferably has a certain degree of flexibility during etching, and may be a UV curable type.
Thus, by embedding the etching resistance layer 1280 in the corroded first concave portion 1250 on the surface side where the pattern for forming the shape of the inner lead tip portion is formed, the first concave portion is formed at the time of etching in a later process. 1250 is corroded to prevent it from becoming large, and mechanical strength reinforcement for high-definition etching is performed, and the spray pressure is increased (3.0 kg / cm ² This makes it easier for the etching to proceed in the depth direction.
Thereafter, the second etching is performed, the lead frame material 1210 is etched from the side of the second recess 1260 opposite to the first recess 1250 formation surface corroded in a solid shape (flat shape), and penetrated. The tip thin portion of the inner lead 1290 is formed. (Fig. 13 (d))
The etching formation surface parallel to the lead frame surface produced by the first etching process is flat, but the two surfaces sandwiching this surface are concave shapes recessed toward the inner lead side.
Next, cleaning, removal of the etching resistance layer 1280, and removal of the resist film (resist patterns 1220A, 1220B) are performed to obtain a lead frame in which the inner lead 1290 is thinly processed. (Fig. 13 (e))
The etching resistance layer 1280 and the resist films (resist patterns 1220A and 1220B) are removed by dissolution with a sodium hydroxide aqueous solution.
[0009]
Note that, as described above, the etching processing method in which etching is performed in two stages is generally called a two-stage etching processing method, and is a processing method particularly excellent in accuracy.
In the manufacture of the lead frame shown in FIG. 13, a two-step etching method and a method of processing the outer shape while partially thinning the lead frame material by devising the pattern shape are employed. .
The method for forming the inner lead of the lead frame to be thin is not limited to the etching method described above.
[0010]
The refining process in which the inner lead is thinned by the above method depends on the shape of the second concave portion 1260 and the thickness t of the inner lead tip portion finally obtained. When the thickness is reduced to 50 μm, the flat width W1 shown in FIG. 13E is set to 100 μm, and the inner lead tip portion pitch p can be finely processed to 0.15 mm. If the plate thickness t is reduced to about 30 μm and the flat width W1 is set to about 70 μm, the inner lead tip pitch p can be finely processed to about 0.12 mm. However, depending on how the plate thickness t and the flat width W1 are taken, the inner leads The tip pitch p can be made even narrower.
[0011]
However, in the lead frame obtained by the process of FIG. 13 and the like, the inner lead portion becomes unstable as the inner lead is thinned, and the connecting portion 917 that connects the inner lead end portions is removed as shown in FIG. As shown in FIG. 12, it is necessary to cut and remove the dam bar (frame portion) 914, which is not only problematic in terms of productivity and cost, but also maintains the positional accuracy and quality of the inner lead. Was becoming difficult, so the response was required.
[0012]
[Problems to be solved by the invention]
As described above, the BGA using the double-sided wiring board shown in FIG. 9 has a complicated structure and has many problems in terms of manufacturing and reliability. The BGA provided with a circuit using the lead frame shown in FIG. 10 as a core material. Has problems in terms of productivity and cost, but also has difficulty in maintaining the position accuracy and quality of the inner leads.
The present invention is to cope with these, and can cope with further increase in the number of terminals. In terms of production, cost, and quality, the conventional lead frame member shown in FIG. 11 (c) is shown in FIG. An object of the present invention is to provide a circuit member and a semiconductor device that are more advantageous than a semiconductor device.
At the same time, an object of the present invention is to provide a method for manufacturing the circuit member and a method for manufacturing a semiconductor device.
[0013]
[Means for solving the problems]
A circuit member for a semiconductor device according to the present invention is a circuit member for a semiconductor device having a circuit portion or the like that is formed at least two-dimensionally by a conductive gold layer formed by plating on a conductive substrate. Has at least a lead for electrical connection with a semiconductor element and an external terminal part for electrical connection with an external circuit, and is composed of an integrally connected lead and an external terminal part. A plurality of sets are provided independently, and the external terminal part of the circuit part is formed directly on one surface of the conductive substrate by electrolytic plating, and the lead of the circuit part is formed by the transfer mold. It is characterized in that it is formed on the insulating epoxy resin layer through an insulating epoxy resin layer directly provided on the conductive substrate so as to exclude the external terminal formation region.
Then, the surface of the conductive substrate having the circuit portion is subjected to a surface treatment for providing unevenness, and the surface having the unevenness is subjected to a peeling treatment for imparting peelability. It is characterized by being.
Examples of the conductive substrate include iron-nickel-chromium metal, iron-chromium metal, iron-nickel metal, or iron-carbon metal, and the conductive metal plating includes copper plating or nickel. The thing which is copper plating used as the foundation | substrate etc. is mentioned.
Note that a plurality of semiconductor elements may be mounted as the semiconductor device circuit member.
Moreover, the meaning that only the external terminal part of the circuit part is directly formed on one surface of the conductive substrate by plating means that one surface of the conductive substrate is oxidized or one surface of the conductive substrate is here. This includes the case where a thin release layer of stearic acid or the like is provided on the substrate and electrolytic plating is performed thereon. Similarly, an insulating epoxy resin layer provided directly on a conductive substrate is an oxidation treatment on one surface of the conductive substrate or a thin peeling layer such as stearic acid provided on one surface of the conductive substrate. An insulating epoxy resin layer provided on the substrate is also included.
[0014]
The method for manufacturing a circuit member for a semiconductor device according to the present invention is for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate. In the circuit member, the circuit part has at least a lead for electrical connection with a semiconductor element and an external terminal part for electrical connection with an external circuit, and is an integrally connected lead And the external terminal portion of the circuit portion is formed directly on one surface of the conductive substrate by electrolytic plating, and the lead of the circuit portion is provided. Is a circuit member for a semiconductor device formed on an insulating epoxy resin layer via an insulating epoxy resin layer directly provided on the conductive substrate so as to exclude the external terminal formation region by transfer molding. Manufacturing of (A) a step of applying a surface treatment to make a portion of the conductive substrate uneven, and (b) a peelable surface of the conductive substrate on the side having the unevenness. And (c) an insulating epoxy resin layer formed by transfer molding so that only the external terminal portion formation region is exposed on one surface of the conductive substrate subjected to the surface treatment and the peeling treatment. And (d) by electroplating so that the plating thickness is substantially the same as the thickness of the insulating epoxy resin layer in the exposed area of the conductive substrate that is not covered by the insulating epoxy resin layer. A step of performing metal plating, (e) a plate making process in which an insulating resist is applied on the plating surface, and only an area for creating a circuit part is exposed; and (f) plating only in an area for creating an exposed circuit part, Or with conductive paint It is characterized in that a step of forming a circuit portion conductivity imparted.
In addition, a method for manufacturing a circuit member for a semiconductor device according to the present invention includes a conductive substrate, and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate. The circuit part has at least a lead for electrical connection with the semiconductor element and an external terminal part for electrical connection with the external circuit, and is integrally connected. A plurality of pairs each including a lead and an external terminal portion, and the external terminal portion of the circuit portion is formed directly on one surface of the conductive substrate by electrolytic plating, The lead for the semiconductor device is formed on the insulating epoxy resin layer through the insulating epoxy resin layer directly provided on the conductive substrate so as to exclude the external terminal forming region by transfer molding. Circuit member A manufacturing method, at least in order, (g) a step of performing a surface treatment for forming irregularities on one surface of a conductive substrate, and (h) having peelability on one surface of the conductive substrate on which the irregularities are provided. And (i) providing an insulating epoxy resin layer with a transfer mold so as to expose only the external terminal portion forming region on one surface of the conductive substrate subjected to the surface treatment and the peeling treatment. And (j) conductive metal plating by electrolytic plating so that the plating thickness is substantially the thickness of the insulating epoxy resin layer on the exposed region of the conductive substrate that is not covered with the insulating epoxy resin layer. And (k) a conductive gold layer on the entire surface by applying only electroless plating to the entire surface on the first plating surface side or by applying electroplating after electroless plating. Plating consisting of (L) a step of applying an insulating resist on the plating surface created by electroless plating, and making a plate so as to cover only the region for creating the circuit portion; And a step of etching a plating layer formed by electroless plating using the resist as an etching resistant mask.
And above either Before the plate-making process, a jig hole preparation step for forming a registration jig hole is provided.
And also above either The surface treatment in is a blast treatment by sand blasting.
Also, above either The peeling process in is a process for forming an oxide film on the surface of the conductive substrate.
In the above, examples of the conductive substrate include iron-nickel-chromium-based metals, iron-chromium-based metals, iron-nickel-based metals, and iron-carbon-based metals. Further, the conductive metal plating in the first plating process is copper plating or copper plating with nickel as a base, and the conductive metal plating in the second plating process is generally copper plating.
Here again, only the external terminal portion of the circuit portion is formed directly on one surface of the conductive substrate by plating means that one surface of the conductive substrate is oxidized or thin on one surface of the conductive substrate. This includes the case where a release layer such as stearic acid is provided and electroplated thereon.
Similarly, an insulating epoxy resin layer provided directly on a conductive substrate is an oxidation treatment on one surface of the conductive substrate or a thin peeling layer such as stearic acid provided on one surface of the conductive substrate. An insulating epoxy resin layer provided on the substrate is also included.
[0015]
A method of manufacturing a semiconductor device according to the present invention is a circuit member for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate. The circuit part has at least a lead for electrical connection with the semiconductor element and an external terminal part for electrical connection with the external circuit, and the integrally connected lead and external terminal A plurality of sets of parts each independently, and only the external terminal part of the circuit part is formed directly on one surface of the conductive substrate by plating, and the other part of the circuit part Is a method of manufacturing a semiconductor device using a circuit member for a semiconductor device formed through an insulating epoxy resin layer provided by transfer molding, and at least in order (a) a circuit on a conductive substrate On the department, (B) a semiconductor device lead so as to cover the entire circuit portion of the semiconductor element, the wire, and the lead member for the semiconductor device; It comprises a resin sealing step for molding one side of the member, and (c) a substrate peeling step for peeling the conductive substrate of the lead member for a semiconductor device.
And after the board | substrate peeling process in the above, it has (d) the process of attaching a solder ball to the exposed external terminal part, It is characterized by the above-mentioned.
[0016]
The present invention Related to The semiconductor device is manufactured by the method for manufacturing a semiconductor device of the present invention.
[0017]
[Action]
The circuit member for a semiconductor device of the present invention can cope with the further increase in the number of terminals of the semiconductor device by having the configuration as described above, and provides a circuit member that is excellent in terms of production, cost, and quality. It is possible.
Specifically, a circuit member for a semiconductor device having a conductive substrate and a circuit portion or the like formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate, the circuit portion Has at least a lead for electrical connection with a semiconductor element and an external terminal part for electrical connection with an external circuit, and is composed of an integrally connected lead and an external terminal part. A plurality of sets are provided independently, and the external terminal part of the circuit part is formed directly on one surface of the conductive substrate by electrolytic plating, and the lead of the circuit part is formed by the transfer mold. This is achieved by being formed on the insulating epoxy resin layer via an insulating epoxy resin layer directly provided on the conductive substrate so as to exclude the external terminal forming region.
Then, the surface of the conductive substrate having the circuit portion is subjected to a surface treatment for providing unevenness, and the surface having the unevenness is subjected to a peeling treatment for providing peelability, thereby providing a semiconductor device. In production, the conductive substrate is easily peeled off.
In addition, as shown in FIGS. 5 and 6 to be described later, in the semiconductor device manufacturing process, the solder ball external electrode can be formed simply by peeling off the conductive substrate.
The semiconductor device manufacturing process can be simplified.
In addition, the entire circuit can be miniaturized by producing the lead portion of the circuit by plating.
In addition, by arranging and providing a plurality of semiconductor elements, it can be applied to a multi-chip semiconductor device. Furthermore, it can be applied to CSP.
[0018]
Also, in the conventional lead frame member shown in FIG. 13C, when a lead frame in which the inner leads are finely processed is used, the inner leads are connected and fixed as shown in FIG. 13A. After etching with the connecting portion 917 provided, a complicated process for attaching the inner lead fixing film 960 (FIG. 13B) and removing the connecting portion 917 is required. When the semiconductor device is manufactured using the conventional lead frame member shown in FIG. 14, the support lead 915 for supporting the external terminal portion 913 is sealed with a resin as shown in FIG. 914 has to be removed with a press, and this has been a problem in terms of productivity and cost. However, the circuit member for a semiconductor device of the present invention is externally integrated with a lead. A set of terminal portion, as it has in a state of being separated, respectively, are those that can address these problems.
[0019]
The method of manufacturing a circuit member for a semiconductor device according to the present invention can cope with further increase in the number of terminals of the semiconductor device by adopting the above-described configuration, and is excellent in terms of production, cost, and quality. Is possible.
Specifically, by forming a circuit portion with a conductive metal formed by plating on a conductive substrate, it is possible to form a fine circuit portion with less deformation and excellent accuracy.
After performing a surface treatment to give unevenness to one surface of the conductive substrate and performing a peeling treatment to give the peelability, the processability when forming a semiconductor device ( The peelability of the conductive substrate is improved.
For example, a semiconductor element is mounted on a lead made of a conductive metal formed by plating on a conductive substrate via an insulating adhesive tape, and after wire bonding, only the semiconductor element side is molded. When manufacturing a semiconductor device, the conductive substrate and the conductive metal formed by plating can withstand the pressure of the sealing resin at the time of molding, and the semiconductor device after molding can be surely adhered. The whole is easily peeled off from the conductive substrate. This is because the conductive metal formed by plating due to the surface treatment that gives unevenness is strong on the lateral force and is formed on the conductive substrate, and the vertical force is applied by the peeling treatment. This is because it is easy to peel off.
In addition, the plate making accuracy is ensured by having a jig hole preparation step for forming a registration jig hole before the plate making step.
[0020]
The peeling treatment includes an oxidation treatment in which the surface of the conductive substrate is oxidized with chromic acid or the like to form an oxide film, and a metal bond between the conductive metal formed by plating and the conductive substrate is less likely to occur. . Further, the surface treatment includes a blasting method using sand blasting, but a blasting method in which abrasive grains are mixed with a liquid and sprayed on a workpiece may be used.
In addition, the conductive substrate is an iron-nickel-chromium-based metal or iron-chromium-based metal, and the conductive metal plating is copper plating or copper plating with nickel as a base, so that the above-described surface treatment is applied. In addition, the peeling treatment for imparting peelability is made more effective.
[0021]
The semiconductor device manufacturing method of the present invention can provide a manufacturing method capable of achieving the multi-terminal of the semiconductor device and ensuring the quality of the manufacturing of the semiconductor device by adopting the configuration as described above. Yes.
[0022]
The present invention Related to The semiconductor device is manufactured by the semiconductor device manufacturing method of the present invention using the semiconductor device circuit member of the present invention, the entire manufacturing process of the semiconductor device is simplified, and the cost of productivity is reduced. In addition, it is possible to manufacture a BGA type resin-encapsulated semiconductor device that can cope with a further increase in the number of terminals.
It is also possible to provide a multi-chip semiconductor device or a CSP (Chip Scale Package) on which a plurality of semiconductor elements are mounted.
Needless to say, a complicated manufacturing process as in the case of the conventional BGA using a printed circuit board shown in FIG. 9 is not required, and there is no problem of moisture resistance.
[0023]
【Example】
Examples of the circuit member for a semiconductor device of the present invention will be described with reference to the drawings.
First, examples of the circuit member for a semiconductor device of the present invention will be given.
1A is a plan view showing a simplified circuit member for a semiconductor device according to the first embodiment, and FIG. 1B is a cross-sectional view taken along line A1-A2 of FIG. c) is an enlarged plan view of only the circuit unit 110 in FIGS. 1 (a) and 1 (b), and shows approximately 1/4 of the whole.
In FIG. 1A, the number of leads and external terminal portions is reduced for easy understanding.
In FIG. 1, 100 is a semiconductor device circuit member, 110 is a circuit part, 111 is a die pad, 112 and 112A are leads, 113 is an external terminal part 120 is a conductive substrate, 130 is a jig hole, 140 is an epoxy resin layer, Reference numeral 170 denotes silver plating, and 180 denotes a release layer.
The circuit member 100 for a semiconductor device according to the present embodiment is a circuit member for a BGA type resin-encapsulated semiconductor device. As shown in FIG. 1, the conductive substrate 120 made of stainless steel (SUS430) and the conductive substrate 120 are provided. And a circuit part 110 made of conductive copper formed by plating, and an insulating epoxy resin layer 140 provided by transfer molding, and a jig for ensuring positional accuracy in the manufacturing process. A hole 130 is also provided.
In the semiconductor device circuit member 100 of this embodiment, the semiconductor element is mounted on the circuit portion 110 side of the conductive substrate 120 in this state, and only the semiconductor element mounting side is molded with a sealing resin. Is manufactured on the conductive substrate 120 and then separated from the conductive substrate 120 to obtain a semiconductor device.
In this embodiment, the circuit unit 110 includes a die pad 111, leads 112 and 112 A, and an external terminal unit 113 that is integrally connected to the lead 112. Each set of the lead 112, the external terminal portion 113, and the lead 112A is independent, and is arranged two-dimensionally along the surface of the circuit portion 110.
In the plan view shown in FIG. 1A, the lead 112 is provided on the outer side from the external terminal 113 and the lead 112A is provided on the inner side from the external terminal 113. In this embodiment, Since the lead 112A is electrically connected to the terminal of the semiconductor element by wire bonding at the inner end of the lead 112A, the lead 112 outside the external terminal 113 may not be necessary.
The external terminal portion 113 is used for electrical connection with an external circuit. When manufacturing a BGA type semiconductor device, a solder ball is provided on the opposite side of the semiconductor element mounting side. Connect to an external circuit via the unit.
The silver plating part 170 is for electrically connecting the terminals (bumps) of the semiconductor element and the circuit part 110 by wire bonding when the semiconductor element is mounted on the die pad 111 of the circuit part 110. The lead 112A is provided on the inner tip of the lead 112A.
[0024]
The conductive substrate 120 is made of stainless steel (SUS430) having a thickness of 0.1 mm, but the surface of the conductive substrate 120 on which the circuit part 110 is formed is uneven by sandblasting, and the surface is oxidized. In addition, a stearic acid peeling layer 180 is provided on the oxide film. When a semiconductor element is mounted and molded only on the circuit portion 110 in manufacturing a semiconductor device, the conductive substrate 120 and Adhesion with the circuit part 110 is maintained, and after the molding, the entire semiconductor device is easily peeled from the conductive substrate 120.
[0025]
As described above, the circuit unit 110 is a circuit member for a BGA type semiconductor device using copper formed by plating as a raw material. However, since the circuit unit 110 is fixed to the conductive substrate 120, the conventional BGA shown in FIG. A connecting portion 717 and an external terminal portion for fixing the inner leads integrally connected to the inner lead 712, which are necessary in the lead frame portion (circuit member) 710 shown in FIG. The support lead 715 and the dam bar (frame) 714 are not required.
In the present embodiment, the thickness of the circuit portion 110 is as thin as 40 μm, and the pitch of the tips of the leads 112 is as narrow as 0.12 mm, so that the number of terminals of the semiconductor device can be increased.
[0026]
Next, modifications of the lead frame member 100 of the embodiment will be described.
FIG. 2A is a plan view of a modified lead frame member 200, FIG. 2B is a cross-sectional view taken along B1-B2 of FIG. 2A, and FIG. 2 (a) and FIG. 2 (b), only the circuit part 210 is shown in an enlarged plan view, and shows about 1/4 of the whole.
In FIG. 2A, the number of leads and external terminal portions is reduced for easy understanding.
In FIG. 2, 200 is a semiconductor device circuit member, 210 is a circuit portion, 212 and 212A are leads, 213 is an external terminal portion, 220 is a conductive substrate, 230 is a jig hole, 240 is an epoxy resin layer, and 270 is silver. Plating 280 is a release layer.
The modified lead frame member 200 does not have a die pad, and is provided with a lead 212 outside the external terminal 213 and a plating part 270 for wire bonding.
The lead 212A is provided on the inner side from the external terminal 213, and its length is adjusted as necessary to facilitate mounting of the semiconductor element.
The silver plating portion 270 is provided to electrically connect the terminal (bump) of the semiconductor element and the circuit portion by wire bonding when the semiconductor element is mounted on the circuit portion 210, and is provided outside the external terminal 213. The lead 212 is provided at the outer tip.
[0027]
Next, an embodiment of a method for producing a circuit member for a semiconductor device according to the present invention will be described with reference to the drawings.
First, Example 1 of the manufacturing method of the circuit member for semiconductor devices of this invention is given and demonstrated based on FIG.
This embodiment is a method of manufacturing the semiconductor device circuit member 100 of the above embodiment shown in FIG. 1, and the entire circuit portion is directly produced by plating.
First, a conductive substrate 120 made of stainless steel (SUS430) is prepared (FIG. 3A), and a jig hole for securing alignment is prepared for the conductive substrate 120 (FIG. 3B). The surface of the conductive substrate 120 on which the circuit portion is to be formed was subjected to a surface treatment to make unevenness by sandblasting (FIG. 3C), and then the surface was oxidized with a chromic acid solution to generate an oxide film. The metal substrate with the mark was dipped in stearic acid to form a release layer (template film) 180 (FIG. 3 (d)).
Next, an insulating epoxy resin layer 140 (MP-19OM manufactured by Nitto Denko) was formed to a thickness of 4 Om by a transfer molding method so that a region to be an external terminal portion was exposed. (Fig. 3 (e))
The epoxy resin 140 is not limited to this, and the thickness is also selected as necessary from 40 to 6 [mu] m.
Next, conductive metal plating 110A by electrolytic plating is applied to an exposed region of the conductive substrate 120 that is not covered with the insulating epoxy resin layer 140 so that the plating thickness is substantially the thickness of the insulating epoxy resin layer. The external terminal portion 113 was formed. (Fig. 3 (f))
Next, an insulative resist 190 was applied on the plated surface, and a plate making process was performed in which only the region for creating the circuit portion was exposed. (Fig. 3 (g))
Thereafter, electroless plating 110B is applied only to the region where the exposed circuit portion is to be formed (FIG. 3 (h)), and further electrolytic plating 110A is applied (FIG. 3 (i)) to form the circuit portion (FIG. 3). (J))
In the method of manufacturing the circuit member for a semiconductor device according to the first embodiment shown in FIG. 3, the external terminal portion (bump) and the circuit portion may be formed at a time by only electroless plating without performing electroplating.
[0028]
Next, a second embodiment of the method for manufacturing a circuit member for a semiconductor device according to the present invention will be described with reference to FIG.
This embodiment is a method of manufacturing the semiconductor device circuit member 200 of the above-described modification shown in FIG. 2, and directly produces the entire circuit portion by selectively etching the plated portion formed by plating. is there.
First, a conductive substrate 120 made of stainless steel (SUS430) was prepared (FIG. 4 (a)), and a jig hole for ensuring alignment was prepared for the conductive substrate 120 (FIG. 4 (b) and then conductive). The surface of the conductive substrate 120 on the side where the circuit portion is to be formed was subjected to a surface treatment to provide unevenness by sandblasting (FIG. 4C), and then the surface was oxidized with a chromic acid solution to generate an oxide film. The metal substrate with the mark was dipped in stearic acid to form a release layer (template film) 280 (FIG. 4D).
Next, an insulating epoxy resin layer 240 (Nitto Denko MP-19OM) was formed to a thickness of 4 O μm by a transfer molding method so that a region serving as an external terminal portion was exposed. (Fig. 4 (e))
The epoxy resin is not limited to this, and the thickness is also selected as necessary from 40 to 6 μm. Next, conductive metal plating 210A by electroplating is applied to the exposed area of the conductive substrate that is not covered with the insulating epoxy resin layer so that the plating thickness is substantially the thickness of the insulating epoxy resin layer 240. The external terminal part 213 was formed. (Fig. 4 (f))
Next, conductive gold layer plating 210B was applied to the entire surface on the plating surface side formed by electrolytic plating 210A by electroless plating (FIG. 4G), and a plating layer was formed on the entire surface only by electroless plating. (Fig. 4 (h))
Next, after applying a resist 290 on the plating layer 210B made by electroless plating, the resist is made into a circuit (FIG. 4 (i)), and this is made by electroless plating using this as an anti-etching mask. The plated layer 210B was etched to form the circuit portion 210. (Fig. 4 (j))
[0029]
Compared to the BGA using the double-sided substrate shown in FIG. 9 and the BGA substrate in which the circuit is formed using the lead frame shown in FIG. 10 as a core material, the production method of the above embodiment is superior in terms of productivity and cost. In addition, it is possible to provide a circuit member for a BGA type semiconductor device that can cope with a further increase in the number of terminals.
[0030]
Next, an example of a method for manufacturing a semiconductor device according to the present invention will be described.
First, a method for manufacturing the semiconductor device of Example 1 will be described.
FIG. 5 is a process diagram of the semiconductor device manufacturing method according to the first embodiment.
The manufacturing method of the semiconductor device of this example is manufactured by resin-sealing using the semiconductor device circuit member 100 of the example shown in FIG.
First, the semiconductor device circuit member 100 is prepared (FIG. 5A), and the semiconductor element 510 is mounted on the exposed die pad 111 via the insulating adhesive layer 530 with the terminal 511 side facing up. And the plating part 170 at the tip of the lead 112A were wire-bonded. (Fig. 5 (b))
The insulating adhesive layer 530 can be formed by screen printing, dispensing, or the like. In place of the insulating adhesive layer 530, an insulating double-sided tape may be used.
Next, one surface of the conductive substrate 120 is resin-sealed with a sealing resin 540 so as to cover the semiconductor element 510, the wire 520, and the entire circuit portion 110, and the semiconductor device 500 </ b> A is manufactured on one surface of the conductive substrate 120. did. (Fig. 5 (c))
Next, the conductive substrate 120 was separated from the semiconductor device 500 </ b> A together with the release layer 180. (Fig. 5 (d))
Thereafter, solder balls 560 were provided so as to be integrally connected to the external terminal portion 113 of the external terminal portion of the circuit portion 110 exposed by the separation of the semiconductor device 500A, whereby the semiconductor device 500 was obtained. (Fig. 5 (e))
[0031]
Next, a method for manufacturing the semiconductor device of Example 2 will be described and described with reference to FIG.
The semiconductor device manufacturing method of this example is manufactured by resin-sealing using the semiconductor device circuit member 200 of the modification shown in FIG.
First, a semiconductor device circuit member 200 is prepared (FIG. 6A), and a semiconductor element 610 is mounted on the exposed lead 112 with an insulating adhesive layer 630 facing the terminal 611 side. 611 and the plating part 270 of the lead 112 were wire-bonded. (Fig. 6 (b))
The insulating adhesive layer 630 can be formed by screen printing, dispensing, or the like. In place of the insulating adhesive layer 630, an insulating double-sided tape may be used.
Next, one surface of the conductive substrate 120 is resin-sealed with a sealing resin 640 so as to cover the semiconductor element 610, the wire 620, and the entire circuit portion 110, and the semiconductor device 600 </ b> A is manufactured on one surface of the conductive substrate 120. did. (Fig. 6 (c))
Next, the conductive substrate 120 was separated from the semiconductor device 600 </ b> A together with the peeling layer 280. (Fig. 6 (d))
Thereafter, the solder ball 660 was provided so as to be integrally connected to the external terminal portion 213 of the circuit portion 210 exposed by the separation of the semiconductor device 600A, whereby the semiconductor device 600 was obtained. (Fig. 6 (e))
[0032]
Next, the present invention Related to Semiconductor device Reference Example 1 Will be described with reference to FIG.
In FIG. 7A, 500 is a semiconductor device, 110 is a circuit portion, 111 is a die pad, 112 and 112A are leads, 113 is an external terminal portion, 510 is a semiconductor element, 511 is a terminal, 520 is a wire, and 530 is insulating. An adhesive layer, 540 is a sealing resin, and 560 is a solder ball.
Book Reference example 1 is produced by the semiconductor device manufacturing method shown in FIG. 5 using the semiconductor device circuit member 100 shown in FIG. 1. The circuit member 100 produced by plating is used as the sealing resin 540. In addition, solder balls 560 are provided on the side of the external terminal 113 that is not on the semiconductor element mounting side to serve as external electrodes.
Book Reference example Since the semiconductor device 500 uses the semiconductor device circuit member 100 that can be finely processed, it can sufficiently cope with the increase in the number of terminals of the semiconductor device and is manufactured by the manufacturing method as described above. And the quality is also excellent.
[0033]
In addition, the present invention Related to Semiconductor device Reference Example 2 Is shown in FIG. In FIG. 7B, 600 is a semiconductor device, 210 is a circuit portion, 212 and 212A are leads, 213 is an external terminal portion, 610 is a semiconductor element, 611 is a terminal, 620 is a wire, 630 is an insulating adhesive layer, 640 Is a sealing resin, and 660 is a solder ball.
Book Reference example Is manufactured by the semiconductor device manufacturing method shown in FIG. 4 using the semiconductor device circuit member 200 shown in FIG.
Book Reference example Since the semiconductor device 600 also uses the semiconductor device circuit member 200 that can be finely processed, it can sufficiently cope with the increase in the number of terminals of the semiconductor device and is manufactured by the manufacturing method as described above. And the quality is also excellent.
[0034]
【The invention's effect】
As described above, the circuit member for a semiconductor device of the present invention can be formed thin by producing a circuit portion with a conductive metal formed by plating, thereby enabling fine processing of the circuit. .
Further, the circuit member for a semiconductor device of the present invention makes it possible to produce a solder external electrode on an external terminal portion by simply peeling off a conductive substrate in a semiconductor device production process. It is assumed that there is no need to cut and separate dam bars, frames, etc. by pressing.
In addition, since the lead part of the circuit part is formed through an insulating epoxy resin layer provided by transfer molding, the process itself for producing the circuit member for the semiconductor device is simplified, and its production It is also excellent in terms of properties and cost.
Furthermore, since the lead part of the circuit part is formed on the conductive substrate through the insulating epoxy resin layer provided by transfer molding, the lead deformation is small and the quality is excellent. Yes.
As a result, in particular, it is possible to provide a BGA type semiconductor device that is superior in productivity and cost as compared with the prior art and can cope with further increase in the number of terminals.
The method for manufacturing a circuit member for a semiconductor device of the present invention, as described above, can produce the entire circuit with a conductive metal formed by plating on the surface of the conductive substrate, so that the entire circuit can be held without deformation, In addition, stable manufacturing is possible in manufacturing a semiconductor device.
The semiconductor device of the present invention is manufactured by the method for manufacturing a semiconductor device of the present invention using the circuit member for a semiconductor device of the present invention, and can sufficiently cope with the increase in the number of terminals of the semiconductor device and in terms of quality. Is also certain.
[Brief description of the drawings]
FIG. 1 is a schematic view of a circuit member for a semiconductor device according to a first embodiment.
FIG. 2 is a schematic view of a modified circuit member for a semiconductor device.
FIG. 3 is a process diagram of Embodiment 1 of a method for producing a circuit member for a semiconductor device of the present invention.
FIG. 4 is a process diagram of Embodiment 2 of a method for producing a circuit member for a semiconductor device of the present invention.
FIG. 5 is a process diagram of Embodiment 1 of a semiconductor device manufacturing method of the present invention;
FIG. 6 is a process diagram of Embodiment 2 of a semiconductor device manufacturing method of the present invention.
[Fig. 7] Reference example Sectional view of a semiconductor device
FIG. 8 is a plan view of a conventional circuit unit.
FIG. 9 is a diagram for explaining a BGA semiconductor device;
FIG. 10 is a cross-sectional view of a BGA type semiconductor device using a conventional lead frame as a core material.
FIG. 11 is a view for explaining a conventional lead frame member;
FIG. 12 is a diagram for explaining a process of a BGA type semiconductor device using a conventional lead frame as a core material;
FIG. 13 is a process diagram of two-stage etching.
FIG. 14 is a diagram of a single-layer lead frame and a semiconductor device using the same.
[Explanation of symbols]
100 Circuit members for semiconductor devices
110 Circuit part
111 die pad
112, 112A Lead
113 External terminal
120 conductive substrate
130 Jig hole
140 Epoxy resin layer
170 Silver plating
180 release layer
190 resist
200 Circuit member for semiconductor device
210 Circuit part
212, 212A Lead
213 External terminal
220 conductive substrate
230 Jig hole
240 Epoxy resin layer
270 silver plating
280 release layer
290 resist
500, 500A semiconductor device
510 Semiconductor device
511 terminal
520 wire
530 Insulating adhesive layer
540 Resin for sealing
600, 600A semiconductor device
610 Semiconductor device
611 terminal
620 wire
630 Insulating adhesive layer
640 Resin for sealing
710 Lead frame part
711 die pad
712 Lead
713 External terminal
714 Dam Bar (Frame)
715 Lead
801 Semiconductor device
802 Base material
803 Mold Resin
804, 804A wiring
805 die pad
806 External connection terminal
808 Bonding wire
810 Bonding pad
818 Plating part
850 Through Hole
851 Thermal Conductive Via
900, 900A BGA package
910 Lead frame
911 die pad
912 Inner lead
913 External terminal
914 Dam Bar (Frame)
915 Support lead
917 Connecting part
920 Semiconductor device
921 terminal
930 wire
940 Resin for sealing
950 Solder ball
960 Film for fixing
960A fixing tape
970, 970A Lead frame member
1210 Lead frame material
1220A, 1220B resist pattern
1230 First opening
1240 Second opening
1250 First recess
1260 Second recess
1270 flat surface
1280 Etching resistance layer (filler layer)
1290 inner lead
1300 Semiconductor device
1300 Semiconductor device
1310 (single layer) lead frame
1311 Die pad
1312 Inner lead
1313 Outer lead
1314 Dam Bar
1315 Frame part
1320 Semiconductor elements
1321 Electrode (pad)
1330 wire
1340 Sealing resin

Claims (9)

  A circuit member for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate, wherein the circuit portion is at least a semiconductor It has a lead for electrical connection with the element and an external terminal part for electrical connection with the external circuit, and each set of the integrally connected lead and external terminal part is independent of each other. And the external terminal part of the circuit part is formed directly on one surface of the conductive substrate by electrolytic plating, and the lead of the circuit part is formed by transfer molding the external terminal forming region. A circuit member for a semiconductor device, which is formed on an insulating epoxy resin layer through an insulating epoxy resin layer directly provided on a conductive substrate so as to be excluded.   The surface on the side having the circuit portion of the conductive substrate according to claim 1 is subjected to a surface treatment for providing unevenness, and the surface on the side having the unevenness is subjected to a peeling treatment for imparting peelability. A circuit member for a semiconductor device.   A circuit member for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate. The circuit portion includes at least a semiconductor element It has a lead for electrical connection and an external terminal part for performing electrical connection with an external circuit, and a plurality of sets each consisting of an integrally connected lead and external terminal part are independently provided. The external terminal part of the circuit part is formed by electrolytic plating directly on one surface of the conductive substrate, and the lead of the circuit part is excluded from the external terminal formation region by transfer molding. A method for producing a circuit member for a semiconductor device formed on an insulating epoxy resin layer via an insulating epoxy resin layer directly provided on a conductive substrate, comprising a small number of (A) Conductivity A step of performing a surface treatment for providing irregularities on a portion of the substrate; (b) a step of performing a peeling treatment for imparting peelability to one surface of the conductive substrate on the side having the irregularities; and (c) the surface treatment. A step of providing an insulating epoxy resin layer with a transfer mold so as to expose only the external terminal portion forming region on one surface of the conductive substrate subjected to the peeling treatment; and (d) an insulating epoxy of the conductive substrate. A step of conducting conductive metal plating by electrolytic plating so that the plating thickness is substantially the thickness of the insulating epoxy resin layer on the exposed area not covered with the resin layer; and (e) insulating on the plated surface. A plate making process in which a resist is applied and only the region for creating the circuit part is exposed, and (f) only the region for creating the exposed circuit part is given conductivity by plating or conductive paint, etc. Forming the process Method of manufacturing a circuit member for a semiconductor device which is characterized in that.   A circuit member for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate. The circuit portion includes at least a semiconductor element It has a lead for electrical connection and an external terminal part for performing electrical connection with an external circuit, and a plurality of sets each consisting of an integrally connected lead and external terminal part are independently provided. The external terminal part of the circuit part is formed by electrolytic plating directly on one surface of the conductive substrate, and the lead of the circuit part is excluded from the external terminal formation region by transfer molding. A method of manufacturing a circuit member for a semiconductor device formed on an insulating epoxy resin layer via an insulating epoxy resin layer directly provided on a conductive substrate, wherein at least (g ) Conductive A step of performing a surface treatment for forming irregularities on one surface of the substrate; (h) a step of performing a peeling treatment for imparting releasability to one surface of the conductive substrate on the side having the irregularities; and (i) the surface treatment, A step of providing an insulating epoxy resin layer by transfer molding so that only the external terminal portion forming region is exposed on one surface of the conductive substrate subjected to the peeling treatment; and (j) an insulating epoxy resin of the conductive substrate. (K) a first plating step in which conductive metal plating is performed by electrolytic plating so that the plating thickness is substantially the thickness of the insulating epoxy resin layer in an exposed region that is not covered by the layer; A second plating step of forming a plating layer made of a conductive gold layer on the entire surface by applying only electroless plating to the entire surface on the plating surface side or by applying electroplating after electroless plating; l) Electroless plating A step of applying an insulating resist on the plating surface created by the above, and making a plate so as to cover only the region for creating the circuit portion; and (m) plating created by electroless plating using the resist as an etching resistant mask. And a step of etching the layer. A method for manufacturing a circuit member for a semiconductor device. 5. A method of manufacturing a circuit member for a semiconductor device, comprising a jig hole preparation step of forming a registration jig hole before the plate making process according to claim 3 or 4. 6. The method of manufacturing a circuit member for a semiconductor device, wherein the surface treatment according to claim 3 is a blast treatment by sand blasting. 7. The method for manufacturing a circuit member for a semiconductor device, wherein the peeling process according to claim 3 is a process of generating an oxide film on the surface of the conductive substrate.   A circuit member for a semiconductor device having a conductive substrate and a circuit portion formed at least two-dimensionally by a conductive gold layer formed by plating on the conductive substrate. The circuit portion includes at least a semiconductor element It has a lead for electrical connection and an external terminal part for performing electrical connection with an external circuit, and a plurality of sets each consisting of an integrally connected lead and external terminal part are independently provided. And only the external terminal part of the circuit part is formed directly on one surface of the conductive substrate by plating, and the other part of the circuit part is an insulating material provided by transfer molding. A method of manufacturing a semiconductor device using a circuit member for a semiconductor device formed via an epoxy resin layer, wherein at least, in order, a semiconductor element is placed on a circuit portion on a conductive substrate with a terminal on the upper side Mounted A step of wire bonding the terminals and leads of the semiconductor element, and (b) a resin sealing step of molding one surface of the semiconductor device lead member so as to cover the entire circuit portion of the semiconductor element, the wire, and the semiconductor device lead member. And (c) a substrate peeling process for peeling the conductive substrate of the lead member for a semiconductor device.   9. A method of manufacturing a semiconductor device, comprising: (d) attaching a solder ball to the exposed external terminal portion after the substrate peeling step in claim 8.

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