JP4120342B2 - Charge pump type booster circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a charge pump type booster circuit that obtains a higher voltage source from a low voltage source such as a battery, and more particularly to a booster circuit technique for reducing radio noise generated during a charge pump operation.
[0002]
[Prior art]
For example, many on-vehicle electronic devices use a battery as a drive source, and among them, there are devices that require a drive voltage higher than the battery voltage, such as an EL display panel. Also, portable electronic devices such as video cameras, digital cameras, and mobile phones require a voltage higher than that of the battery in order to display liquid crystal. In order to obtain such a high voltage, a booster circuit is required. Although the booster circuit for use as described above has a disadvantage that output voltage fluctuation is slightly large, a booster circuit using a charge pump circuit that can adopt a transformer-less structure and can reduce the size of the circuit is often employed. .
[0003]
FIG. 3 shows an example of a circuit configuration of a conventional booster circuit that obtains a high voltage using such a charge pump circuit. The booster circuit 1 includes a charge pump circuit 2, a comparator circuit 3, and a boost pulse generation circuit. 4.
The charge pump circuit 2 is a circuit that boosts the external power supply voltage Vin, and includes diodes D21 to D25, capacitors C21 to C25, an inverter Q21, a first non-inverting buffer Q22, and a second non-inverting buffer Q23. .
[0004]
An external power supply voltage Vin is supplied to the anode of the diode D21. The cathodes of the diodes D21 to D24 are connected to the anodes of the diodes D22 to D25, respectively. The anodes of the diodes D22 to D25 are connected to the first terminals of the capacitors C21 to C24, respectively. The second terminals of the capacitors C21 and C23 are connected to the output terminal of the first non-inverting buffer Q22. The second terminals of the capacitors C22 and C24 are connected to the output terminal of the second non-inverting buffer Q23. The second non-inverting buffer Q23 buffers the boost pulse signal φ1 of the boost pulse generation circuit 4 and drives the second terminals of the capacitors C22 and C24. The first non-inverting buffer Q22 buffers a pulse obtained by inverting the boost pulse signal φ1 of the boost pulse generation circuit 4 by the inverter Q21, and drives the second terminals of the capacitors C21 and C23. The cathode of the diode D25 is connected to the output node Nout. This is an output voltage obtained by boosting the voltage Vout of the output node Nout. An output voltage smoothing capacitor C25 is connected between the cathode of the diode D25 and the ground node Vss.
[0005]
In the charge pump circuit 2, the electric charge supplied from the external power supply voltage Vin through the diode D 21 is transferred to the subsequent stages sequentially with the capacitors C 21, C 22 and C 23 in synchronization with the boost pulse signal φ 1 of the boost pulse generation circuit 4. Along with this charge transfer, the charging voltage of each capacitor becomes higher toward the subsequent capacitor, and a boosted output voltage Vout expressed by the following equation is obtained at the output node Nout.
Vout = Vin + (Vφ−VF) × N−VF− (Iout × N) / (C × f)
Here, Vφ is the output voltage of the non-inverting buffers Q22 and Q23, VF is the forward voltage of the diode, Iout is the output current, C is the capacitance of the capacitors C21 to C24, f is the frequency of the boost pulse signal φ1, and N is the diode This is the number of booster circuits (for example, C21 and D22) to which one capacitor is connected. The number of stages N is adjusted according to the degree of boosting required.
[0006]
The obtained output voltage Vout is guided to the comparator circuit 3 and divided by resistors R31 and R32 connected in series. The divided voltage is input to the inverting input terminal of the comparator COMP31 as the feedback voltage Vf. The reference voltage Vref generated by the reference voltage generation circuit 31 is input to the non-inverting input terminal of the comparator COMP31. When the output voltage Vout decreases and the feedback voltage Vf becomes lower than the reference voltage Vref, the comparator COMP31 outputs a “High” level (logic “1”) signal as an active signal, while the output voltage Vout increases. When the feedback voltage Vf becomes higher than the reference voltage Vref, an operation of generating a “Low” level (logic “0”) signal as an inactive signal and sending it to the boost pulse generating circuit 4 is performed.
[0007]
The boost pulse generation circuit 4 basically generates a boost pulse signal φ1 to cause the charge pump circuit 2 to perform a boost operation when the output of the comparator COMP31 is at “High” level. On the contrary, when the output of the comparator COMP31 is at the “Low” level, the circuit stops the generation of the boost pulse signal φ1 and stops the boost operation of the charge pump circuit 2.
[0008]
The boost pulse generation circuit 4 shown in FIG. 3 includes a shift register 42 composed of master-slave D-type flip-flops DF41, DF42, and DF43, a 3-input OR circuit Q41, a 2-input AND circuit Q42, a non-inverting buffer Q43, an inverter Q44.
Immediately after the circuit power is turned on, a reset signal RST is output from a reset pulse generation circuit (not shown). Then, it is inverted by the inverter circuit Q44 and added to the reset terminals of the three flip-flops DF41 to DF43 to return each flip-flop to the initial state.
[0009]
On the other hand, the clock signal CLOCK generated by the clock pulse generation circuit 41 is buffered by the non-inverting buffer Q43 and then input to the clock input terminals CL of the flip-flops DF41 to DF43. Each of the flip-flops DF41 to DF43 reads the logic state of the data input terminal D at the moment when the clock pulse is applied to the clock input terminal CL, and reads the logic state at the falling edge of the clock pulse. The operation of outputting to each output terminal Q is performed. The flip-flops DF41 to DF43 are subordinately connected (the output terminal Q of the previous stage is connected to the data input terminal D of the flip-flop of the next stage) to constitute the shift register 42. Therefore, every time a clock pulse of the clock signal CLOCK is input, an operation is performed in which data read from the data input terminal D of the first-stage flip-flop DF41 is successively shifted to the subsequent flip-flop. In FIG. 4, the shift register 42 is configured by three flip-flops DF41 to DF43. However, this is an example, and the number of flip-flops (the number of bits of the shift register 42) is increased or decreased as necessary.
[0010]
The output signals of the flip-flops DF41 to DF43 are applied to the input terminal of the 3-input OR circuit Q41, and the output signal is applied to the first input terminal of the 2-input AND circuit Q42 and to the second input terminal of Q42. Clock signal CLOCK is input. The output of Q42 is a boost pulse signal φ1. Accordingly, if there is at least one “High” level signal among the signals at the output terminals D of DF41 to DF43, the output of Q41 becomes the “High” level. In this state, when the next clock pulse is input as the clock signal CLOCK, a boost pulse having the same waveform as the clock pulse appears as the boost pulse signal φ1. Then, the boost pulse is input to the charge pump circuit 2 to perform a boost operation.
[0011]
Since the shift register 42 composed of the flip-flops DF41 to DF43 is provided, when the output of the comparator COMP31 becomes “High” level and the signal is latched in the DF41 in synchronization with the clock pulse, at least thereafter Three boost pulses are output as the boost pulse signal φ1. Further, even after the output of the comparator COMP31 continues to be at the “Low” level after continuing the “High” level for a long time, at least three boosting pulses are output as the boosting pulse signal φ1 thereafter.
[0012]
If the shift register 42 is provided and the output signal of the comparator COMP 31 is extended, the operation of the charge pump circuit 2 generates a short pulse at the output of the comparator COMP 31 when not doing so. Noise and cause malfunctions in other circuits. Since the short pulse is not synchronized with the clock pulse, if the AND of the signal and the clock signal CLOCK is directly ANDed by the 2-input AND circuit Q42, the boost pulse is narrower than the clock pulse width of the clock signal CLOCK. This is because, for example, the signal φ1 may be generated and the operation of the charge pump circuit 2 may become unstable.
[0013]
For this reason, the normal operation of the circuit of FIG. 3 is as shown in the timing chart of the main signal in FIG. The timing chart of FIG. 4 is a diagram when a constant output current Iout is supplied from the output node Nout to the load.
[0014]
Since the output current Iout is supplied from the smoothing capacitor C25, the output voltage Vout decreases as the output current Iout flows. Since the reference voltage Vref is set so that the feedback voltage Vf obtained by dividing the output voltage Vout becomes lower than the reference voltage Vref when the output voltage Vout becomes lower than the predetermined threshold voltage Vth, the output of the comparator COMP31 is Immediately changes to “High” level.
[0015]
Then, the flip-flop DF41 latches the “High” level signal and outputs the “High” level to the output terminal D by the clock pulse of the clock signal CLOCK immediately after that. Thus, when the output of DF41 becomes "High" level, the output of Q41 also becomes "High" level, and the boost pulse having the same waveform as the clock pulse appears as the boost pulse signal φ1 of the output of Q42 by the next clock pulse. When this boost pulse is input to the charge pump circuit 2 and the boost operation is performed once, the output voltage Vout rises and exceeds a predetermined threshold voltage Vth.
When the output voltage Vout exceeds the threshold voltage Vth, the feedback voltage Vf becomes larger than the reference voltage Vref, and the output of the comparator COMP31 immediately returns to the “Low” level. Therefore, in the next clock pulse, the DF 41 latches the “Low” level, the output returns to the “Low” level, and the logic state is shifted by the subsequent clock pulse.
[0016]
However, the “High” level signal latched in the flip-flop DF1 by the clock pulse immediately after the output of the comparator COMP31 first becomes “High” level is lost after being shifted to DF42 and DF43 by the subsequent clock pulse. Therefore, while the “High” level signal is held in any one of DF1 to DF3, the output of Q41 continues to be maintained at the “High” level. Three boost pulses appear.
[0017]
The charge pump circuit 2 receives these three boost pulses and performs a boost operation, and the output voltage Vout is boosted to a voltage higher than the threshold voltage Vth. The boosting operation is stopped by stopping the generation of the boosting pulse. Thereafter, the output current Iout again flows, so that the output voltage Vout starts to decrease. When the output voltage Vout drops below the predetermined threshold voltage Vth, the comparator COMP31 outputs the “High” level signal again. Thereby, the same boosting operation as described above is started again. As a result of such an operation, an operation of repeating a periodic waveform as shown in the timing chart of FIG. 4 is performed.
[0018]
[Problems to be solved by the invention]
A problem in the step-up operation as described above is current noise generated when the charge pump circuit 2 performs the step-up operation. Whenever the output of the non-inverting buffers Q22 and Q23 performs an inverting operation in response to the boosting pulse, a large charge transfer instantaneously occurs in each part in the charge pump circuit 2. Then, current noise caused by the instantaneous movement of the electric charge is generated at the timing as shown in (4) of FIG.
[0019]
When the output current Iout is substantially constant, the current noise during the boosting operation is intermittently repeatedly generated at a cycle T1 as shown in (4) of FIG. The noise spectrum of current noise having such a waveform exhibits a spectrum composed of a plurality of harmonics having a fundamental period of T1. Therefore, when an AM radio in the medium wave band (535 to 1605 kHz) exists around the booster circuit 1 that generates such noise, those harmonics are mixed into the AM radio as radio noise and interfere with the broadcast radio wave. Cause a problem of generating beat sound.
[0020]
The present invention has been made in view of such circumstances, and an object thereof is to reduce the magnitude of the radio noise generated by the boosting operation of the booster circuit 1 when the output current is substantially constant. is there.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 This is a charge pump type booster circuit including a charge pump circuit, a comparator circuit, and a boost pulse generation circuit. The charge pump circuit is configured to boost an external power supply voltage in response to a boost pulse from the boost pulse generation circuit. The comparator circuit compares the output voltage boosted by the charge pump circuit with a predetermined threshold voltage. When the output voltage is lower than the threshold voltage, the comparator circuit compares the active signal with the output voltage. When the voltage is higher than the threshold voltage, an inactive signal is output. Further, the boost pulse generation circuit is a circuit that receives the output signal of the comparator circuit and generates the boost pulse, and the information that the first stage flip-flop latches in synchronization with the clock pulse generated by the internal clock pulse generation circuit. The first and second shift registers differing in the number of bits for shifting the signal, and a flip-flop whose output state is inverted every time an active signal is received from the comparator circuit. When the output of the flip-flop is inactive and the output of the comparator circuit is active, the first shift register synchronizes the active signal and the second shift register synchronizes the inactive signal with the clock pulse. On the contrary, when the output of the flip-flop is active and the output of the comparator circuit is active, the first shift register uses the inactive signal and the second shift register uses the active signal as the clock pulse. It is configured to latch synchronously. Further, when the bit output of either the first or second shift register is active, the boost pulse is generated in synchronization with the clock pulse. This is a charge pump type booster circuit.
[0022]
With this configuration, the minimum number of boosting pulses generated by the boosting pulse generation circuit when a signal is detected that the output voltage has dropped below the threshold voltage, every time a detection signal is received. , It will be different from the previous minimum number of occurrences. Therefore, since the cycle of the generated current noise waveform is different each time, the peak value of the noise spectrum is reduced and the effect of reducing radio noise can be obtained.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an electrical configuration diagram showing an example of an embodiment of the present invention. 3 that are the same as or equivalent to those in FIG. 3 are denoted by the same reference numerals, and description thereof is not repeated.
[0026]
The charge pump type booster circuit 1 of FIG. 1 includes a charge pump circuit 2, a comparator circuit 3, and a boost pulse generation circuit 4. The configurations of the charge pump circuit 2 and the comparator circuit 3 are the same as those of the charge pump circuit 2 and the comparator circuit 3 in FIG. 3 described in the section “Prior Art”, and the operations are also the same.
[0027]
Hereinafter, the configuration and operation of the boost pulse generation circuit 4 in FIG. 1 different from that in FIG. 3 will be described in detail. DF44 to DF49 in FIG. 1 are master-slave D-type flip-flops. DF45 to DF47 constitute a 3-bit shift register 42, and the operation thereof is the same as that of the shift register 42 composed of DF41 to DF43 in FIG. Similarly, DF48 and DF49 constitute a 2-bit shift register 43, and the operation is the same only when the number of bits is one bit less than that of the 3-bit shift register 42 composed of DF45 to DF47. A clock signal CLOCK generated by the clock pulse generation circuit 41 is buffered and applied to each clock input terminal of DF45 to DF49 by a non-inverting buffer Q43.
[0028]
A signal obtained by inverting the reset signal RST for resetting DF45 to DF49 at the time of turning on the circuit power by the inverter Q44 is applied to each reset terminal (negative logic input terminal) of DF45 to DF49.
[0029]
The outputs of the flip-flops DF45 to DF47 constituting the 3-bit shift register 42 are input to the 3-input OR circuit Q47. When at least one output of the DF45 to DF47 is at "High" level, the output of Q47 is “High” level. Similarly, the outputs of DF48 and DF49 are input to the 2-input OR circuit Q48. When at least one of the outputs of DF48 and DF49 is at "High" level, the output of Q48 is at "High" level. The outputs of Q47 and Q48 are input to a two-input OR circuit Q46. When at least one of the outputs of Q47 and Q48 is at “High” level, the output of Q46 is also at “High” level. With such a circuit configuration, the output of Q46 becomes a “High” level when at least one of the outputs DF45 to DF49 is at the “High” level.
[0030]
The output signal of the comparator COMP31 is input to the clock input terminal CL of the flip-flop DF44 and the first input terminals of the two-input AND circuits Q50 and Q51. The output signal of the DF 44 is input to the second input terminal of the 2-input AND circuit Q51 and the inverter Q49. The output signal of the inverter Q49 is input to the data input terminal D of the DF 44 and the second input terminal of the 2-input AND circuit Q50. With such a circuit configuration, the output of the DF 44 repeats the operation of inverting the output state each time a clock pulse is input to the clock input terminal CL.
[0031]
A “High” level signal is applied to the input terminal D of the DF 45 when the comparator COMP 31 outputs an “High” level signal that is an active signal when the output of the DF 44 is in a “Low” level state that is inactive. On the contrary, a signal of “High” level is applied to the input terminal D of the DF 48 when the comparator COMP 31 outputs “High” level when the output of the DF 44 is in the “High” level state which is an active state.
[0032]
Next, the normal operation of the booster circuit 1 under such a circuit configuration will be described with reference to the time chart of main signals shown in FIG. The normal operation means a state in which a substantially constant output current Iout is supplied from the output node Nout to the load. Since the output current Iout is supplied from the smoothing capacitor C25, the output voltage Vout decreases as the output current Iout flows. When the output voltage Vout becomes lower than the predetermined threshold voltage Vth, the feedback voltage Vf obtained by dividing the output voltage Vout becomes lower than the reference voltage Vref, and the comparator COMP31 outputs an “High” level signal that is an active signal. Output.
[0033]
Since the output state of the flip-flop DF44 may start from either the "High" level or the "Low" level, it is assumed here that the output of the DF44 is initially at the "Low" level. Then, when the output of the comparator COMP31 becomes “High” level, the output of Q50 becomes “High” level, and the “High” level which is an active signal is latched in the DF45 by the first clock pulse which comes after the clock signal CLOCK. Is done. On the other hand, since the output signal of DF44 is at the “Low” level, the output of Q51 remains at the “Low” level, and the “Low” level that is an inactive signal is latched in DF48.
[0034]
Since the output of the flip-flop DF45 becomes “High” level, the outputs of Q47 and Q46 also become “High” level. Therefore, a boosting clock pulse appears in the boosting pulse signal φ1 which is the output signal of Q42 by the clock pulse next to the clock signal CLOCK. When this boost pulse is input to the charge pump circuit 2, the boost operation is performed once, whereby the output voltage Vout rises and exceeds the threshold voltage Vth. Then, the feedback voltage Vf exceeds the reference voltage Vref, and the output of the comparator COMP31 falls to the “Low” level. By such an operation, the output waveform of the comparator COMP31 becomes a pulse-like waveform that immediately returns to the “Low” level after being “High” level for a short time as shown in the first waveform of FIG. Become.
[0035]
While the output of the comparator COMP31 is at the “Low” level, the outputs of Q50 and Q51 are both maintained at the “Low” level. Therefore, in the subsequent clock pulse of the clock signal CLOCK, both the DF45 and DF48 latch the “Low” level. To do. The logic state is shifted to the subsequent flip-flop each time a clock pulse is applied. However, the “High” level signal latched in DF45 immediately after the comparator COMP31 first outputs the “High” level due to the decrease in the output voltage Vout is shifted to DF46 and DF47 by the subsequent clock pulse and disappears. When at least one output of DF46 to DF47 is at "High" level, the output of Q46 is maintained at "High" level. Therefore, three boost pulses are shown in the boost pulse signal φ1 that is the output signal of Q42. It appears as the first pulse group in (3) of 2.
[0036]
In response to the three boosting pulses, the charge pump circuit 2 performs the boosting operation three times, so that the output voltage Vout rapidly rises as shown by the waveform (2) in FIG. The boosting is stopped when the generation of the boosting pulse is stopped. Thereafter, due to the outflow of the load current Iout, the output voltage Vout begins to decrease with a slope determined by the value of the smoothing capacitor C25 and the value of the output current Iout.
[0037]
Here, the operation of the flip-flop DF44 will be described. The first pulse waveform of (1) in FIG. 2 is applied from the comparator COMP31 to the clock input terminal CL of the DF44. A signal obtained by inverting the signal of the output terminal Q by the inverter 49 is input to the data input terminal D of the DF 44. Initially, since the output of the DF 44 was at the “Low” level, a signal at the “High” level is applied to the data input terminal D. Accordingly, the “High” level signal is read at the rising edge of the pulse signal applied from the comparator COMP 31 to the clock input terminal CL, and the “High” level signal read at the falling edge of the pulse signal is applied to the output terminal Q. Transferred. Thus, the output of the DF 44 is inverted to the “High” level. After that, when the next pulse signal is applied to the clock input terminal D, the output returns to the original “Low” level. That is, the flip-flop DF44 repeats the operation in which the output state is inverted every time the comparator COMP31 generates a pulse signal.
[0038]
If the output current Iout continues to flow out after the boosting operation is stopped and the output voltage Vout continues to decrease, the output voltage after the elapse of T1 from the start of boosting as shown in the first sawtooth waveform of (2) in FIG. Vout again becomes lower than the threshold voltage Vth. Then, the comparator COMP31 outputs “High” level again. This time, contrary to the above case, the output of DF44 is at "High" level, so DF48 latches "High" level and DF45 is at "Low" level by the next clock pulse of clock signal CLOCK. Latch. As a result, the outputs of Q48 and Q46 become "High" level, and a boost pulse appears in the boost pulse signal φ1 by the next clock pulse. The charge pump circuit 2 performs the boosting operation again by this boosting pulse, whereby the output voltage Vout exceeds the threshold voltage Vth. The output of the comparator COMP31 returns to the “Low” level again. By such an operation, the output waveform of the comparator COMP31 becomes the pulse-like waveform shown in the second part of (1) in FIG.
[0039]
From the next clock pulse, both DF45 and DF48 latch the “Low” level and shift it as before. However, the signal latched as “High” level in the DF 48 disappears after being shifted to the DF 49. Therefore, two boost pulses are generated in the boost pulse signal φ1, which is the output of Q42, this time as in the second pulse group in (3) of FIG. The value of the output voltage Vout after boosting with the two boosting pulses is lower than the voltage value after boosting with the previous three boosting pulses. Therefore, the time T2 until the output voltage Vout decreases due to the boosted output current Iout and becomes equal to or lower than the threshold voltage Vth is shorter than the previous time T1. By such an operation, the output voltage Vout draws a second sawtooth waveform as shown in (2) of FIG.
[0040]
After the time T2 has elapsed, the output of the DF 44 is re-inverted and returned to the initial "Low" level state, so the subsequent operation is the same as the operation during the first time T1 described above. By repeating such an operation, the circuit of FIG. 1 performs an operation in which two waveforms having periods T1 and T2 as shown in the timing chart of FIG. 2 are alternately repeated. The current noise accompanying the boosting operation existing during such an operation process has a waveform as shown in (4) of FIG.
[0041]
Here, let us consider the difference in magnitude between the radio noise due to the current noise waveform in the present embodiment and the radio noise due to the current noise waveform in the case of the conventional circuit shown in FIG. In the case of the conventional circuit, the current noise has a single waveform with a basic period of T1. On the other hand, in the case of the present embodiment, the current noise has a waveform in which a waveform having a cycle T1 and two waveforms having a cycle T2 are alternately repeated. That is, the number of waveforms has increased to two. However, the frequency of occurrence of each of these waveforms is ½ that of the conventional circuit.
[0042]
Considering the noise spectrum of these current noise waveforms, in the case of the conventional circuit, the spectrum is composed of a plurality of harmonics having a fundamental period of T1. On the other hand, the noise spectrum in the present embodiment is a spectrum obtained by combining a spectrum composed of a plurality of harmonics whose fundamental period is T1 and a spectrum composed of a plurality of harmonics whose fundamental period is T2. That is, the noise spectrum has a shape having peaks at two places.
[0043]
Since the noise spectrum has peaks at two places, in the case of this embodiment, the width of the frequency band having a noise level above a certain level is slightly wider than that of the conventional circuit. However, on the contrary, the noise level of each peak is lower than the case of one peak of the conventional circuit because the frequency of occurrence of each waveform is reduced to ½. For this reason, in the case of the booster circuit according to the present embodiment, the noise frequency is dispersed and the amplitude is reduced, so that the radio noise is reduced as compared with the conventional circuit.
[0044]
In the description so far, it is assumed that the load current Iout is constant. This is because the radio noise is generated most strongly when the load current Iout is constant. When the load current Iout fluctuates, the time from when the output voltage Vout is boosted to when the load current Iout is discharged and again becomes equal to or lower than the threshold voltage Vth fluctuates. That is, the values of the periods T1 and T2 where current noise occurs vary. This means that the noise spectrum of the current noise is further dispersed, and the radio noise is further reduced as compared with the case where the load current Iout is constant.
[0045]
Further, in the booster circuit shown in FIG. 1 of the present embodiment, 3-bit and 2-bit shift registers are employed as the shift registers 42 and 43. However, the number of bits of the shift register is not limited to this, and the number of bits different from these may be used. However, if the number of bits of the two shift registers is the same, the operation is the same as that of the conventional circuit, and therefore different values are required. In addition, it is preferable to prevent the number of bits of the shift register having the larger number of bits from being an integral multiple of the number of bits having the smaller number in order to avoid overlapping of harmonic components.
[Brief description of the drawings]
FIG. 1 is an electrical configuration diagram of a booster circuit showing an embodiment of the present invention.
FIG. 2 is a timing chart of main signals of the circuit shown in FIG.
FIG. 3 is a view corresponding to FIG.
FIG. 4 is a view corresponding to FIG.
[Explanation of symbols]
In the drawings, 1 is a charge pump type booster circuit, 2 is a charge pump circuit, 3 is a comparator circuit, 4 is a boost pulse generation circuit, 31 is a reference voltage generation circuit, 41 is a clock pulse generation circuit, and 42 is a first shift register. 43 is a second shift register, DF41 to DF49 are D-type flip-flops, COMP31 is a comparator, Vout is an output voltage, Vref is a reference voltage, Vf is a feedback voltage, Vin is an external power supply voltage, Iout is an output current, and CLOCK is A clock signal, φ1, indicates a boost pulse signal.

Claims (1)

A charge pump type booster circuit comprising a charge pump circuit, a comparator circuit, and a boost pulse generation circuit,
The charge pump circuit is a circuit configured to boost an external power supply voltage in response to a boost pulse from the boost pulse generation circuit,
The comparator circuit compares the output voltage boosted by the charge pump circuit with a predetermined threshold voltage. When the output voltage is lower than the threshold voltage, the comparator circuit compares the active signal with the output voltage. It is a circuit configured to output an inactive signal when it is higher than the threshold voltage,
The boost pulse generation circuit is a circuit that receives the output signal of the comparator circuit and generates the boost pulse, and the information that the first stage flip-flop latches in synchronization with the clock pulse generated by the internal clock pulse generation circuit. The first and second shift registers having different numbers of bits to be shifted and a flip-flop whose output state is inverted every time an active signal is received from the comparator circuit, and the comparator circuit is in an inactive state when the output of the flip-flop is inactive The first shift register latches the active signal, the second shift register latches the inactive signal in synchronization with the clock pulse, and conversely, the output of the flip-flop is in the active state. When the output of the comparator circuit is in an active state The first shift register is configured to latch an inactive signal, the second shift register is configured to latch an active signal in synchronization with the clock pulse, and one of the first and second shift registers. A charge pump booster circuit, wherein the booster pulse is generated in synchronization with the clock pulse when the bit output is active .

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