JP6832697B2 - Switching power supply circuit, load drive device, liquid crystal display device - Google Patents

Description

The present invention relates to a switching power supply circuit, a load drive device, and a liquid crystal display device.

Conventionally, a switching power supply circuit (for example, a step-up type switching power supply circuit that boosts an input voltage to generate an output voltage) has been widely used as a power supply means for various applications. Examples of the control method of the switching power supply circuit include a current mode control method in which feedback control is performed according to both the output voltage and the coil current.

In addition, as an example of the prior art related to the above, Patent Document 1 and Patent Document 2 can be mentioned.

JP-A-2010-220355 JP 2015-166870

However, the current mode control type switching power supply circuit has a problem that the slope compensation ratio and the PWM [pulse width modulation] gain fluctuate according to the load fluctuation.

Further, in the conventional step-up switching power supply circuit, there is room for further improvement in the line regulation characteristic and the line step characteristic (line transient characteristic).

In view of the above-mentioned problems found by the inventor of the present application, the invention disclosed in the present specification is a switching power supply circuit capable of maintaining a constant slope compensation ratio and PWM gain without depending on load fluctuation. Alternatively, it is also an object of the present invention to provide a step-up switching power supply circuit having good line regulation characteristics and line step characteristics, and further, it is an object of the present invention to provide a load drive device and a liquid crystal display device using the same.

The switching power supply circuit disclosed in the present specification includes a switching output unit that generates an output voltage from an input voltage by driving a coil current using an output transistor, and the output voltage or a feedback voltage corresponding thereto. The switching control unit includes a switching control unit that controls on / off of the output transistor so as to match a predetermined reference voltage, and the switching control unit includes a reference slope voltage generation unit that generates a reference slope voltage and the coil. A sense voltage holding unit that generates a holding sense voltage by latching a sense voltage corresponding to a current at a predetermined timing, and a voltage adding unit that generates a slope voltage by adding the reference slope voltage and the holding sense voltage. , And the on-duty of the output transistor is determined using the slope voltage (first configuration).

In the switching power supply circuit having the first configuration, the first end of the sense voltage holding unit is connected to the input end of the sense voltage, and the second end is connected to the output end of the holding sense voltage. A configuration including a switch, a capacitor whose first end is connected to the output end of the holding sense voltage and whose second end is connected to the ground end, and a control unit which controls on / off of the switch (second). The configuration of) is recommended.

Further, in the switching power supply circuit having the first configuration, the sense voltage holding unit has a first switch whose first end is connected to the input end of the sense voltage and a first end of the first switch. A second switch connected to two ends and the second end connected to the output end of the holding sense voltage, and the first end connected to the second end of the first switch and the second end connected to the ground end. Complementary to the first switch and the second switch, the first capacitor connected to the output end of the holding sense voltage and the second end connected to the ground end. A configuration (third configuration) may include a control unit that performs on / off control.

Further, in the switching power supply circuit having any of the first to third configurations, the switching control unit further includes a clock signal generation unit that generates a clock signal at a predetermined reference frequency, and the sense voltage holding unit includes a clock signal generation unit. It is preferable to have a configuration (fourth configuration) that operates in synchronization with the clock signal.

Further, in the switching power supply circuit having any of the first to fourth configurations, the switching control unit generates an error voltage according to the difference value between the output voltage or the feedback voltage and the reference voltage. And a comparator that compares the error voltage with the slope voltage to generate a comparison signal, and a configuration (fifth configuration) that determines the on-duty of the output transistor according to the comparison signal. Good.

Further, in the switching power supply circuit having the fifth configuration, the switching control unit includes a set signal generation unit that generates a set signal in a predetermined pulse cycle, and a reset signal corresponding to the set signal and the comparison signal. A configuration (sixth) further including an RS flip flop that receives the input of the pulse width modulation signal and outputs the pulse width modulation signal, and a driver that receives the input of the pulse width modulation signal and outputs the on / off control signal of the output transistor. Configuration) is recommended.

Further, in the switching power supply circuit having the sixth configuration, the switching control unit generates a maximum duty setting signal pulse when the maximum on-time elapses after the pulse is generated in the set signal. It is preferable to have a configuration (seventh configuration) further including a unit, a logic gate that logically synthesizes the comparison signal and the maximum duty setting signal to generate the reset signal.

Further, in the switching power supply circuit having any of the first to seventh configurations, the switching output unit may have a step-up type, a step-down type, or a buck-boost type (eighth configuration).

Further, the load drive device disclosed in the present specification includes a switching power supply circuit having any of the first to eighth configurations, a driver that receives power from the switching power supply circuit to drive the load, and the like. (Ninth configuration).

Further, the liquid crystal display device disclosed in the present specification has a configuration (10th) having a load drive device having the ninth configuration and a liquid crystal display panel driven as a load of the load drive device (10th). Configuration).

Further, the switching power supply circuit disclosed in the present specification controls an on / off control of the output transistor and a switching output unit that generates an output voltage by turning the output transistor on / off to boost the input voltage. The switching control unit includes an error amplifier that generates an error voltage according to the difference value between the output voltage or the feedback voltage corresponding thereto and a predetermined reference voltage, and the switching control unit that generates a slope voltage. A slope voltage generating unit is included, and a comparator that compares the error voltage with the slope voltage to determine the on-duty of the output transistor. The slope voltage generating unit comprises the input voltage and the output voltage. The configuration is such that the slope voltage gradient is changed according to the inverse of the difference (11th configuration).

In the switching power supply circuit having the eleventh configuration, the slope voltage generator is a slope current source that generates a slope current whose slope changes according to the inverse of the difference between the input voltage and the output voltage. , The configuration (12th configuration) including the resistor for converting the slope current to the slope voltage may be preferable.

Further, in the switching power supply circuit having the twelfth configuration, the slope current source is based on a charging current generating unit that generates a charging current corresponding to the inverse of the difference between the input voltage and the output voltage, and the charging current. The configuration (thirteenth configuration) may include a capacitor to be charged, a charge / discharge switch for switching the charge / discharge of the capacitor, and a voltage / current conversion unit for converting the charge voltage of the capacitor into the slope current.

Further, in the switching power supply circuit having the thirteenth configuration, the charging current generating unit has a second current source that generates a predetermined first current, and a second that is proportional to the difference between the input voltage and the output voltage. A second current source that generates a current, a logarithmic converter that linearly converts the first current and the second current to generate a first logarithmic voltage and a second logarithmic voltage, and the first logarithmic voltage and the first logarithmic voltage. It has a configuration (14th configuration) including a transconductance amplifier that receives a differential input of a binary voltage and generates the charging current.

Further, in the switching power supply circuit having the 14th configuration, the logarithmic conversion unit converts the first diode that converts the first current into the first logarithmic voltage and the second current into the second logarithmic voltage. The configuration includes a second diode (15th configuration).

Further, in the switching power supply circuit having any of the first to fifteenth configurations, the switching control unit includes a set signal generation unit that generates a pulse of a set signal at a predetermined pulse period, and the set signal and the comparator. An RS flip flop that accepts an input of a reset signal according to the comparison result and outputs a pulse width modulated signal, and a driver that accepts an input of the pulse width modulated signal and outputs an on / off control signal of the output transistor. Further, it is preferable to have a configuration including (16th configuration).

Further, in the switching power supply circuit having the 16th configuration, the switching control unit generates a maximum duty setting signal pulse when the maximum on-time elapses after the pulse is generated in the set signal. It is preferable that the configuration (17th configuration) further includes a unit, a logic gate that logically synthesizes the comparison signal of the comparator and the maximum duty setting signal to generate the reset signal.

Further, in the switching power supply circuit having any of the above 11th to 17th configurations, the switching output unit includes a coil whose first end is connected to the input end of the input voltage and grounded to the second end of the coil. An output transistor connected between the ends, a rectifying element connected between the second end of the coil and the output end of the output voltage, and a connection between the output end of the output voltage and the ground end. It is preferable to have a configuration (18th configuration) including the output capacitor.

Further, the load drive device disclosed in the present specification includes a switching power supply circuit having the configuration according to any one of the above 11th to 18th, a driver that receives power supply from the switching power supply circuit, and drives the load. It is said that the configuration has (19th configuration).

Further, the liquid crystal display device disclosed in the present specification has a load drive device having the nineteenth configuration and a liquid crystal display panel driven as a load of the load drive device (20th configuration). It is said that.

According to the invention disclosed in the present specification, a switching power supply circuit capable of maintaining a constant slope compensation ratio and PWM gain regardless of load fluctuation, or boosting with good line regulation characteristics and line step characteristics. It is possible to provide a type switching power supply circuit, and further, it is possible to provide a load drive device and a liquid crystal display device using the type switching power supply circuit.

Block diagram showing a configuration example of a liquid crystal display device A circuit diagram showing a first embodiment of a switching power supply circuit Timing chart showing an example of duty control Waveform diagram showing the first example (light load) of the slope generation operation in the first embodiment Waveform diagram showing a second example (heavy load) of the slope generation operation in the first embodiment Gain diagram showing frequency-PWM gain characteristics in the first embodiment A circuit diagram showing a second embodiment of a switching power supply circuit Circuit diagram showing a configuration example of the sense voltage holding unit Timing chart showing an example of sense voltage holding operation Circuit diagram showing a modified example of the sense voltage holding unit Waveform diagram showing the first example (light load) of the slope generation operation in the second embodiment Waveform diagram showing a second example (heavy load) of the slope generation operation in the second embodiment Gain diagram showing frequency-PWM gain characteristics in the second embodiment A circuit diagram showing a third embodiment of a switching power supply circuit Correlation diagram between on-duty and boost ratio A circuit diagram showing a fourth embodiment of a switching power supply circuit Waveform diagram showing slope voltage tilt adjustment operation Circuit diagram showing a configuration example of the reference slope voltage generator Circuit diagram showing a configuration example of a slope current source Circuit diagram showing a configuration example of the charging current generator External view of tablet terminal

<Liquid crystal display device>
FIG. 1 is a block diagram showing a configuration example of a liquid crystal display device. The liquid crystal display device 1 of this configuration example includes a liquid crystal driving device 10 and a liquid crystal display panel 20. The liquid crystal drive device 10 is a load drive device that controls the drive of the liquid crystal display panel 20 based on a video signal Sin input from a host device (microcomputer or the like) (not shown) or various commands. The liquid crystal display panel 20 is a video output means using a liquid crystal element as a pixel, and is driven as a load of the liquid crystal driving device 10.

<LCD drive device>
Subsequently, the liquid crystal driving device 10 will be described in detail with reference to FIG. The liquid crystal drive device 10 of this configuration example includes a system power supply unit 11, a timing control unit 12, a level shifter 13, a gate driver 14, a source driver 15, a gamma voltage generation unit 16, a common voltage generation unit 17, and the like. including.

The system power supply unit 11 operates by receiving an input voltage VIN (for example, + 12V), and has an analog power supply voltage A VDD (for example, + 17V) and a logic power supply voltage VDD (for example, + 3.3V, + 1.8V, + 1.2V). , Positive power supply voltage VGH (for example, + 28V) and negative power supply voltage VGL (for example, -12V) are generated and supplied to each part of the apparatus.

The timing control unit 12 operates by receiving the supply of the logic system power supply voltage VDD, and based on the commands and data input from the host device, the timing control unit 12 controls the timing of the liquid crystal drive device 10 (vertical synchronization control of the gate driver 14 and source driver). (15 horizontal synchronization control, etc.) is performed.

The level shifter 13 operates by receiving the supply of the positive power supply voltage VGH and the negative power supply voltage VGL, and transmits the timing control signal (vertical synchronization signal) input from the timing control unit 12 to the gate driver 14 after level-shifting.

The gate driver 14 operates by receiving the supply of the positive power supply voltage VGH and the negative power supply voltage VGL, and based on the vertical synchronization signal input from the level shifter 13, the gate signals G (1) to G (y) of the liquid crystal display panel 20. ) Is generated. The gate signals G (1) to G (y) are the liquid crystal elements of the liquid crystal display panel 20 (when the liquid crystal display panel 20 is an active matrix type, the gate terminals of the active elements connected to the liquid crystal elements). Is supplied to.

The source driver 15 operates by receiving the supply of the analog power supply voltage A VDD, and outputs the digital (m-bit) video signal Sin input from the host device (not shown) to the analog source signals S (1) to S (x). Is converted to and supplied to the liquid crystal element of the liquid crystal display panel 20 (when the liquid crystal display panel 20 is an active matrix type, the source terminal of the active element connected to each of the liquid crystal elements).

The gamma voltage generation unit 16 operates by receiving the supply of the analog power supply voltage A VDD, generates n ways (however, n = 2 ^m -1) of gradation voltages V (0) to V (n), and is a source driver. Supply to 15. The gradation voltages V (0) to V (n) correspond one-to-one with ^{the data values “0” to “2 m -1” of the video signal Sin, respectively.}

The common voltage generation unit 17 generates a predetermined common voltage VC to generate a liquid crystal element of the liquid crystal display panel 20 (when the liquid crystal display panel 20 is an active matrix type, the drain terminal of the active element connected to the liquid crystal element). ).

<Switching power supply circuit (first embodiment)>
FIG. 2 is a circuit diagram showing a first embodiment of a switching power supply circuit built in the system power supply unit 11. The switching power supply circuit 100 of this embodiment is a circuit unit that generates a desired output voltage Vo (for example, corresponding to analog power supply voltage A VDD) from an input voltage Vi (for example, corresponding to an input voltage VIN), and is a switching output unit. It includes 110 and a switching control unit 120.

The switching output unit 110 is a boost-type switching output stage that boosts the input voltage Vi and generates the output voltage Vo by turning on / off the output transistor N1 and driving the coil current IL, and is an output transistor N1 (this figure). In the example, an N-channel type MOS [metal oxide semiconductor] field effect transistor), a coil L1, a rectifier diode D1, an output capacitor Co1, and a sense resistor Rs are included.

The first end of the coil L1 is connected to the input end of the input voltage Vi. The second end of the coil L1 is connected to the drain of the output transistor N1 and the anode of the rectifier diode D1. The source of the output transistor N1 is connected to the first end of the sense resistor Rs. The second end of the sense resistor Rs is connected to the ground end. The sense resistor Rs is a current / voltage conversion element for taking out the switch current Is (= corresponding to the coil current IL flowing during the ON period of the output transistor N1) as the sense voltage V2 (= Is × Rs). The gate of the output transistor N1 is connected to the output end (= output end of the gate signal S4) of the switching control unit 120. The cathode of the rectifying diode D1 is connected to the output end of the output voltage Vo and the first end of the output capacitor Co1. The second end of the output capacitor Co1 is connected to the ground end.

However, as for the rectification method of the switching output unit 110, a synchronous rectification method may be adopted instead of the diode rectification method. In that case, the rectifier diode D1 may be replaced with a synchronous rectifier transistor, which may be turned on / off complementarily with the output transistor N1.

The switching control unit 120 is an output feedback circuit unit that controls on / off of the output transistor N1 so that the feedback voltage Vfb corresponding to the output voltage Vo and the predetermined reference voltage Vref match, and the digital / analog conversion unit 121 and the switching control unit 120. , Feedback voltage generation unit 122, error amplifier 123, phase compensation unit 124, clock signal generation unit 125, set signal generation unit 126, maximum duty setting unit 127, reference slope voltage generation unit 128, and voltage addition. A unit 129, a comparator 12A, an OR gate 12B, an RS flip-flop 12C, and a driver 12D are included.

The digital / analog conversion unit 121 generates an analog reference voltage Vref from the digital reference voltage setting signal REF.

The feedback voltage generator 122 includes resistors R1 and R2 connected in series between the output end and the ground end of the output voltage Vo, and divides the output voltage Vo from the connection node between the resistors R1 and R2. Vfb (= {R2 / (R1 + R2)} × Vo) is output. However, if the output voltage Vo is within the input dynamic range of the switching control unit 120 (particularly the error amplifier 123), the feedback voltage generation unit 122 may be omitted and the output voltage Vo may be directly accepted as the feedback voltage Vfb. I do not care.

The error amplifier 123 is a current output type transconductance amplifier (so-called gm amplifier). The error amplifier 123 has a capacitor C1 that forms the phase compensation unit 124 according to the difference value between the feedback voltage Vfb input to the inverting input end (−) and the reference voltage Vref input to the non-inverting input terminal (+). The error voltage Verr is generated by charging and discharging. When the feedback voltage Vfb is lower than the reference voltage Vref, a current flows from the error amplifier 123 toward the capacitor C1, so that the error voltage Verr rises. On the contrary, when the feedback voltage Vfb is higher than the reference voltage Vref, the current is drawn from the capacitor C1 toward the error amplifier 123, so that the error voltage Verr decreases.

The phase compensation unit 124 is a time constant circuit including a resistor R3 and a capacitor C1 connected in series between the output end and the ground end of the error amplifier 123, and performs phase compensation of the error voltage Verr.

The clock signal generation unit 125 generates the clock signal CLK at a predetermined reference frequency f0 (= 1 / T0).

The set signal generation unit 126 generates a pulse of the set signal S1 in synchronization with the clock signal CLK. For example, the set signal generation unit 126 generates a pulse of the set signal S1 for each m pulse of the clock signal CLK. Therefore, the pulse period T of the set signal S1 (= switching period T of the output transistor N1) is m × T0.

The maximum duty setting unit 127 generates a pulse of the maximum duty setting signal S2b in synchronization with the clock signal CLK. For example, the maximum duty setting unit 127 generates the pulse of the maximum duty setting signal S2b at the nth pulse (where n <m) of the clock signal CLK, counting from the pulse generation timing of the set signal S1. That is, the maximum duty setting unit 127 generates a pulse in the maximum duty setting signal S2b when the maximum on-time Ton (max) (= n × T0) elapses after the pulse is generated in the set signal S1.

The reference slope voltage generation unit 128 generates the reference slope voltage V1 in synchronization with the clock signal CLK. The reference slope voltage V1 starts to rise, for example, at the pulse generation timing of the set signal S1 (= the first pulse of the clock signal CLK), and at the pulse generation timing of the maximum duty setting signal S2b (= the nth pulse of the clock signal CLK). It is a serrated analog voltage that is reset to zero. However, the configuration of the reference slope voltage generation unit 128 is not limited to this, and is configured to generate the reference slope voltage V1 in synchronization with both the set signal S1 and the pulse width modulation signal S3, for example. May be good.

The voltage addition unit 129 adds the reference slope voltage V1 and the sense voltage V2 to generate the slope voltage Vslp. In this way, the reference slope voltage V1 and the sense voltage V2 are added to generate the slope voltage Vslp, and the on-duty of the output transistor N1 is determined using this to obtain both the output voltage Vo and the coil current IL. It is possible to realize the corresponding current mode control.

The comparator 12A compares the error voltage Verr input to the inverting input end (−) with the slope voltage Vslp input to the non-inverting input end (+) to generate the comparison signal S2a. The comparison signal S2a has a low level when the error voltage Verr is higher than the slope voltage Vslp, and has a high level when the error voltage Verr is lower than the slope voltage Vslp.

The OR gate 12B outputs the OR signal of the comparison signal S2a and the maximum duty setting signal S2b as the reset signal S2. Therefore, the reset signal S2 becomes high level when at least one of the comparison signal S2a and the maximum duty setting signal S2b is high level, and low level when both the comparison signal S2a and the maximum duty setting signal S2b are low level. It becomes.

The RS flip-flop 12C outputs a pulse width modulation signal S3 from the output end (Q) in response to the set signal S1 input to the set end (S) and the reset signal S2 input to the reset end (R). The pulse width modulation signal S3 is set to a high level at the rising edge of the set signal S1 and reset to a low level at the rising edge of the reset signal S2, for example.

The driver 12D receives the input of the pulse width modulation signal S3 and generates the gate signal S4 of the output transistor N1 (corresponding to the on / off control signal of the output transistor N1) by increasing its current capacity, which is used as the output transistor. Output to the gate of N1. The output transistor N1 is turned on when the gate signal S4 is at a high level and turned off when the gate signal S4 is at a low level.

<Basic operation (boost operation)>
First, the basic operation (boost operation) of the switching power supply circuit 100 will be described. When the output transistor N1 is turned on, a coil current IL (= switch current Is) directed toward the ground end flows through the coil L1 via the output transistor N1, and its electric energy is stored. At this time, the switch voltage Vsw appearing at the anode of the rectifier diode D1 drops to almost the ground voltage via the output transistor N1. Therefore, since the rectifier diode D1 is in the reverse bias state, no current flows from the output capacitor Co1 toward the output transistor N1.

On the other hand, when the output transistor N1 is turned off, the electric energy stored in the counter electromotive force generated in the coil L1 is released as a current. At this time, since the rectifier diode D1 is in a forward bias state, the coil current IL flowing through the rectifier diode D1 is applied to the load (source driver 15 and gamma voltage generator 16) from the output end of the output voltage Vo as the output current Iout. At the same time as flowing in, it also flows into the ground end via the output capacitor Co1, and the output capacitor Co1 is charged. By repeating the above operation, the load is supplied with the output voltage Vo in which the input voltage Vi is boosted.

<Duty control>
FIG. 3 is a timing chart showing an example of duty control according to the error voltage Ver. In order from the top, the clock signal CLK, the set signal S1, the error voltage Verr and the slope voltage Vslp, the comparison signal S2a, and the maximum duty setting signal S2b. , The reset signal S2, and the pulse width modulation signal S3 are depicted.

In the example of this figure, the pulse of the set signal S1 is generated every 16 pulses of the clock signal CLK. When the set signal S1 rises to a high level, the pulse width modulation signal S3 is set to a high level, so that the output transistor N1 is turned on. Further, at this time, the slope voltage Vslp starts to rise with a predetermined inclination.

After that, when the slope voltage Vslp becomes higher than the error voltage Verr, the comparison signal S2a rises to a high level, and the reset signal S2 rises to a high level. As a result, the pulse width modulation signal S3 is reset to the low level, so that the output transistor N1 is turned off.

The higher the error voltage Verr, the later the intersection timing with the slope voltage Vslp. Therefore, the high level period (= on-period Ton of the output transistor N1) of the pulse width modulation signal S3 becomes longer, and the on-duty Don of the output transistor N1 (= the ratio of the on-period Ton to the switching period T, Don) = Ton / T) becomes large.

On the contrary, the lower the error voltage Verr, the earlier the intersection timing with the slope voltage Vslp. Therefore, the high level period of the pulse width modulation signal S3 becomes short, and the on-duty Don of the output transistor N1 becomes small.

As described above, in the switching power supply circuit 100, the desired output voltage Vo is generated from the input voltage Vi by determining the on-duty Don of the output transistor N1 according to the comparison result between the error voltage Verr and the slope voltage Vslp. ..

However, as a result of the error voltage Verr becoming too high, if the pulse generation of the maximum duty setting signal S2b is performed before the comparison signal S2a rises to a high level, the reset signal S2 is at a high level at that time. The output transistor N1 is turned off. That is, a predetermined upper limit value (= maximum on-time Ton (max)) is set for the on-period Ton of the output transistor N1.

<Slope generation operation>
FIG. 4 is a waveform diagram showing a first example (light load state or no load state, for example, Iout = 0A) of the slope generation operation in the first embodiment. The horizontal axis of this figure shows the elapsed time t since the output transistor N1 was turned on, and the vertical axis of this figure is the reference slope voltage V1 (dashed line), sense voltage V2 (dashed line), and slope. The voltage values of the voltage Vslp (solid line) and the error voltage Verr (broken line) are shown.

The reference slope voltage V1 increases with a predetermined slope α [V / t] after the on-timing (t = 0) of the output transistor N1. Therefore, the voltage value of the reference slope voltage V1 at the time t1 (= the intersection timing of the slope voltage Vslp and the error voltage Verr) is V1 = α × t1.

On the other hand, the sense voltage V2 increases with a slope β [V / t] according to the switch current Is after the on-timing (t = 0) of the output transistor N1. In the no-load state, the switch current Is gradually increases from 0A, so the sense voltage V2 also increases from 0V. That is, in the no-load state, the DC component (= V2DC) of the sense voltage V2 becomes 0V. Therefore, the voltage value of the sense voltage V2 at time t1 is V2 = β × t1.

As described above, the slope voltage Vslp is generated by adding the reference slope voltage V1 and the sense voltage V2. Therefore, the voltage value of the slope voltage Vslp at time t1 is Vslp = V1 + V2 = (α + β) × t1.

FIG. 5 is a waveform diagram showing a second example (heavy load state, for example, Iout = 1A) of the slope generation operation in the first embodiment. As in FIG. 4, the horizontal axis of this figure shows the elapsed time t since the output transistor N1 was turned on, and the vertical axis of this figure is the reference slope voltage V1 (dashed line) and sense. The voltage values of the voltage V2 (two-dot chain line), the slope voltage Vslp (solid line), and the error voltage Verr (broken line) are shown.

As described above, the reference slope voltage V1 increases with a predetermined slope α [V / t] after the on-timing (t = 0) of the output transistor N1. Therefore, the voltage value of the reference slope voltage V1 at the time t2 (= the intersection timing of the slope voltage Vslp and the error voltage Verr, where t1 <t2) is V1 = α × t2.

On the other hand, the sense voltage V2 increases with a slope β [V / t] according to the switch current Is after the on-timing (t = 0) of the output transistor N1. In the heavy load state, the switch current Is rapidly increases to a current value corresponding to the output current Iout at the same time when the output transistor N1 is turned on, and then gradually increases with the passage of time. Therefore, the sense voltage V2 has a DC component (= V2DC) corresponding to the output current Iout. Therefore, the voltage value of the sense voltage V2 at time t2 is V2 = β × t2 + V2DC.

As described above, the slope voltage Vslp is generated by adding the reference slope voltage V1 and the sense voltage V2. Therefore, the voltage value of the slope voltage Vslp at time t2 is Vslp = V1 + V2 = (α + β) × t2 + V2DC.

In this way, the reference slope voltage V1 and the sense voltage V2 are added to generate the slope voltage Vslp, and the on-duty of the output transistor N1 is determined using this to obtain both the output voltage Vo and the coil current IL. It is possible to realize the corresponding current mode control.

However, the slope voltage Vslp includes not only the DC component (= V2DC) of the sense voltage V2 according to the weight of the load (= the magnitude of the output current Iout) but also the AC component of the sense voltage V2 depending on the elapsed time t. (= Β × t) is included.

Therefore, when the on-duty Don of the output transistor N1 changes according to the load fluctuation, the AC component (= β × t) of the sense voltage V2 included in the slope voltage Vslp is changed at the intersection timing of the error voltage Verr and the slope voltage Vslp. Will also change. For example, as shown in FIGS. 4 and 5, between the AC component of the sense voltage V2 at time t1 (= β × t1) and the AC component of the sense voltage V2 at time t2 (= β × t2). , An unintended voltage difference (= β × (t2-t1)) occurs due to the difference in the elapsed time t.

Further, even when the slope β itself fluctuates according to the load fluctuation, the AC component (= β × t) of the sense voltage V2 changes.

FIG. 6 is a gain diagram showing the frequency-PWM gain characteristic in the first embodiment. The broken line indicates a light load state (for example, Iout = 0A), and the solid line indicates a heavy load state (for example, Iout = 1A).

As described above, in the switching power supply circuit 100 of the first embodiment, since the slope voltage Vslp contains the AC component (= β × t) of the sense voltage V2, the slope compensation ratio and the PWM gain are accompanied by the load fluctuation. Fluctuates. As a result, the current feedback ratio also changes, so that the phase margin at the time of light load decreases (see f1 → f0). In addition, the load response characteristics also change as the load fluctuates.

In particular, in the source driver 15 and the gamma voltage generator 16, which are the loads of the switching power supply circuit 100, the liquid crystal display panel 20 alternately repeats the display period and the non-display period (so-called blanking period), and the current consumption of each is Fluctuates periodically.

That is, the output current Iout of the switching power supply circuit 100 periodically fluctuates according to the driving state of the liquid crystal display panel 20. Specifically, during the display period of the liquid crystal display panel 20, a predetermined output current Iout flows (heavy load state). On the other hand, during the non-display period of the liquid crystal display panel 20, the output current Iout hardly flows (light load state).

In this way, in the switching power supply circuit 100 in which the light load state and the heavy load state are frequently switched, in order to stabilize the output operation and obtain the desired load response characteristics, the slope compensation ratio does not depend on the load fluctuation. And it is desirable to keep the PWM gain constant. In the following, a second embodiment for realizing this is proposed.

<Switching power supply circuit (second embodiment)>
FIG. 7 is a circuit diagram showing a second embodiment of the switching power supply circuit 100. The switching power supply circuit 100 of this embodiment is based on the first embodiment (FIG. 2), and is characterized in that a sense voltage holding unit 12E is further added. Therefore, the same components as those in the first embodiment are designated by the same reference numerals as those in FIG. 2 to omit duplicated explanations, and the feature portions of the present embodiment will be mainly described below.

The sense voltage holding unit 12E generates a holding sense voltage V2hold by latching the sense voltage V2 at a predetermined timing, and outputs this to the voltage adding unit 129. The sense voltage holding unit 12E operates in synchronization with the clock signal CLK.

Further, with the addition of the sense voltage holding unit 12E, the voltage adding unit 129 is changed to a configuration in which the reference slope voltage V1 and the holding sense voltage V2hold are added to generate the slope voltage Vslp.

<Sense voltage holding unit>
FIG. 8 is a circuit diagram showing a configuration example of the sense voltage holding unit 12E. The sense voltage holding unit 12E of this configuration example includes a switch E1, a capacitor E2, and a control unit E3. The first end of the switch E1 is connected to the input end of the sense voltage V2. Both the second end of the switch E1 and the first end of the capacitor E2 are connected to the output end of the holding sense voltage V2hold. The second end of the capacitor E2 is connected to the ground end. The control end of the switch E1 is connected to the application end (= signal output end of the control unit E3) of the switch control signal SE1.

The control unit E3 controls on / off of the switch E1 by switching the logic level of the switch control signal SE1 in synchronization with the clock signal CLK. The switch E1 is turned on, for example, when the switch control signal SE1 is at a high level, and is turned off when the switch control signal SE1 is at a low level.

That is, when the switch control signal SE1 is at a high level, the input end of the sense voltage V2 and the first end of the capacitor E2 are conducted. Therefore, the capacitor E2 is charged until the voltage between both ends thereof becomes substantially the sense voltage V2.

On the other hand, when the switch control signal SE1 is at a low level, the input end of the sense voltage V2 and the first end of the capacitor E2 are cut off. Therefore, as the holding sense voltage V2hold, the voltage between both ends of the capacitor E2 (≈V2) immediately before the switch E1 is turned off is held.

In this way, the sense voltage holding unit 12E latches the sense voltage V2 at a predetermined timing by the so-called track / hold operation.

FIG. 9 is a timing chart showing an example of the sense voltage holding operation, in order from the top, clock signal CLK, pulse width modulation signal S3, coil current IL (solid line) and switch current Is (broken line), switch control signal SE1. In addition, the sense voltage V2 (solid line) and the holding sense voltage V2hold (broken line) are depicted. In this figure, the switching period T of the switching power supply circuit 100 corresponds to 16 pulses of the clock signal CLK.

When the pulse width modulation signal S3 is switched from the low level to the high level, the output transistor N1 is turned from off to on, so that the coil current IL changes from decreasing to increasing. The switch current Is corresponds to the coil current IL that flows during the ON period of the output transistor N1. Therefore, the sense voltage V2 sharply rises to a voltage value (= V2DC) corresponding to the minimum value of the coil current IL at the same time when the output transistor N1 is turned on, and then further rises with the passage of time.

The logic level of the switch control signal SE1 is switched in synchronization with the clock signal CLK. More specifically according to the example of this figure, the switch control signal SE1 rises to a high level at the 15th pulse of the clock signal CLK and falls to a low level at the 3rd pulse of the clock signal CLK. As a result, the holding sense voltage V2hold starts to follow the sense voltage V2 before the output transistor N1 is turned on, and after the output transistor N1 is turned on, the sense voltage V2 is latched at the falling timing of the switch control signal SE1. Become.

In the example of this figure, the coil current IL detection operation (= sense voltage V2 latch operation) is performed during the ON period of the output transistor N1. Regarding the latch timing of the sense voltage V2 (= falling timing of the switch control signal SE1), the minimum on-duty Ton (min) of the output transistor N1 is taken into consideration, and the timing at which the output transistor N1 is surely turned on is set. It is desirable to set.

However, the coil current IL detection operation does not necessarily have to be performed during the ON period of the output transistor N1. That is, when the coil current IL flowing during the off period of the output transistor N1 is to be detected, for example, the latch operation of the switch voltage Vsw during the off period of the output transistor N1 is performed instead of the latch operation of the sense voltage V2. Just do it. In that case, it is desirable to set the latch timing of the switch voltage Vsw to the timing at which the output transistor N1 is surely turned off in consideration of the maximum on-duty Ton (max) of the output transistor N1.

As described above, the detection timing of the coil current IL can be arbitrarily set as long as it does not change for each cycle. When the switching output unit 110 is a step-up type, a configuration is adopted in which the coil current IL is detected during the ON period of the output transistor N1, that is, a configuration in which the switch current Is flowing through the output transistor N1 is detected. Is desirable.

FIG. 10 is a circuit diagram showing a modified example of the sense voltage holding unit 12E. The sense voltage holding unit 12E of this modification is based on the configuration of FIG. 8, and is characterized in that a switch E4 and a capacitor E5 are further added.

The first end of the switch E1 is connected to the input end of the sense voltage V2. The second end of the switch E1 and the first end of the capacitor E2 are both connected to the first end of the switch E4. The second end of the capacitor E2 is connected to the ground end. Both the second end of the switch E4 and the first end of the capacitor E5 are connected to the output end of the holding sense voltage V2hold. The second end of the capacitor E5 is connected to the ground end. The control ends of the switches E1 and E4 are connected to the application ends (= signal output ends of the control unit E3) of the switch control signals SE1 and SE4, respectively. As the switch control signal SE4, for example, the logic inversion signal (= SE1B) of the switch control signal SE1 may be used.

The control unit E3 performs complementary on / off control of the switches E1 and E4 by switching the logic levels of the switch control signals SE1 and SE4 in synchronization with the clock signal CLK, respectively.

For example, when the switch control signal SE1 is at a high level and the switch control signal SE4 is at a low level, the switch E1 is turned on and the switch E4 is turned off. That is, the input end of the sense voltage V2 and the first end of the capacitor E2 are conducted, and the connection between the first end of the capacitor E2 and the output end of the holding sense voltage V2 is cut off. Therefore, the voltage across the capacitor E2 is charged until it becomes approximately the sense voltage V2. Further, as the holding sense voltage V2hold, the voltage between both ends of the capacitor E5 immediately before the switch E4 is turned off is held.

On the other hand, when the switch control signal SE1 is at a low level and the switch control signal SE4 is at a high level, the switch E1 is turned off and the switch E4 is turned on. That is, the input end of the sense voltage V2 and the first end of the capacitor E2 are cut off, and the first end of the capacitor E2 and the output end of the holding sense voltage V2hold are conducted. At this time, the electric charge is redistributed between the capacitors E2 and the capacitor E5 until the voltages across the capacitors become equal to each other. Therefore, when the capacitance values of the capacitors E2 and E5 are the same, the holding sense voltage V2hold is the voltage across the capacitor E2 (= corresponding to the sampling value in the current cycle) and the voltage across the capacitor E5 immediately before the switch E4 is turned on. It is the average value with (= corresponding to the hold value of the previous cycle).

As described above, as the sense voltage holding unit 12E, a sample / hold circuit (FIG. 10) can be used instead of the track / hold circuit (FIG. 8).

<Slope generation operation>
FIG. 11 is a waveform diagram showing a first example (light load state or no load state, for example, Iout = 0A) of the slope generation operation in the second embodiment. The horizontal axis of this figure shows the elapsed time t since the output transistor N1 was turned on, and the vertical axis of this figure is the reference slope voltage V1 (dashed line) and the sense voltage V2 (dashed line). , Holding sense voltage V2hold (dashed line), slope voltage Vslp (solid line), and error voltage Verr (dashed line) are shown.

Since the behaviors of the reference slope voltage V1 and the sense voltage V2 are the same as those in FIG. 4 above, duplicate explanations are omitted. The holding sense voltage V2hold increases with a slope β [V / t] following the sense voltage V2 after the on-timing (t = 0) of the output transistor N1, but a predetermined latch set before the time t1. At the timing (= time tx), the voltage value is latched. Therefore, after the time tx, the voltage value of the holding sense voltage V2hold is held at V2hold = β × tx regardless of the elapsed time t.

As described above, the slope voltage Vslp is generated by adding the reference slope voltage V1 and the holding sense voltage V2hold. Therefore, the voltage value of the slope voltage Vslp at time t1 is Vslp = V1 + V2hold = α × t1 + β × tx.

FIG. 12 is a waveform diagram showing a second example (heavy load state, for example, Iout = 1A) of the slope generation operation in the second embodiment. As in FIG. 11, the horizontal axis of this figure shows the elapsed time t since the output transistor N1 was turned on, and the vertical axis of this figure is the reference slope voltage V1 (dashed line) and sense. The voltage values of the voltage V2 (two-dot chain line), the holding sense voltage V2hold (three-dot chain line), the slope voltage Vslp (solid line), and the error voltage Verr (broken line) are shown.

Since the behaviors of the reference slope voltage V1 and the sense voltage V2 are the same as those in FIG. 5 above, duplicate explanations are omitted. The holding sense voltage V2hold increases with a slope β [V / t] following the sense voltage V2 after the on-timing (t = 0) of the output transistor N1, but a predetermined latch set before the time t2. At the timing (= time tx), the voltage value is latched. In the heavy load state, the switch current Is rapidly increases to a current value corresponding to the output current Iout at the same time when the output transistor N1 is turned on, and then gradually increases with the passage of time. Therefore, the holding sense voltage V2hold has a DC component (= V2DC) corresponding to the output current Iout. Therefore, after the time tx, the voltage value of the holding sense voltage V2hold is held at V2hold = β × tx + V2DC regardless of the elapsed time t.

As described above, the slope voltage Vslp is generated by adding the reference slope voltage V1 and the holding sense voltage V2hold. Therefore, the voltage value of the slope voltage Vslp at time t2 is Vslp = V1 + V2hold = α × t2 + β × tx + V2DC.

In this way, the reference slope voltage V1 and the holding sense voltage V2hold are added to generate the slope voltage Vslp, and the on-duty of the output transistor N1 is determined using this to determine both the output voltage Vo and the coil current IL. It is possible to realize the current mode control according to the above. This point is basically the same as that of the first embodiment.

Further, the holding sense voltage V2hold does not change its voltage value after a predetermined latch timing (= time tx). Therefore, the slope voltage Vslp of the second embodiment is less affected by the AC component (= β × t) of the sense voltage V2 than that of the first embodiment, so that the DC component (= V2DC) of the sense voltage V2 can be used. It will be reflected more appropriately.

That is, the voltage difference (= β) due to the difference in the elapsed time t between the AC component (= β × t1) of the sense voltage V2 at the time t1 and the AC component (= β × t2) of the sense voltage V2 at the time t2. Even if × (t2-t1)) occurs, it does not affect the duty control using the slope voltage Vslp.

Further, even when the slope β itself fluctuates according to the load fluctuation, if the time tx does not change, the duty control using the slope voltage Vslp is not affected.

FIG. 13 is a gain diagram showing the frequency-PWM gain characteristic in the second embodiment. The broken line indicates a light load state (for example, Iout = 0A), and the solid line indicates a heavy load state (for example, Iout = 1A).

As described above, since the slope voltage Vslp of the second embodiment is not easily affected by the AC component (= β × t) of the sense voltage V2, the slope compensation ratio and the PWM gain fluctuate even if the load fluctuates. It becomes difficult to do. Therefore, the current feedback ratio is less likely to change, and it is possible to maintain a phase margin at the time of a light load. It is also possible to maintain a constant load response characteristic regardless of load fluctuations.

In particular, in the switching power supply circuit 100 in which the light load state and the heavy load state are frequently switched, in order to stabilize the output operation and obtain a desired load response characteristic, the above second embodiment is adopted and the load is applied. It is desirable to keep the slope compensation ratio and PWM gain constant regardless of fluctuations.

<Switching power supply circuit (third embodiment)>
FIG. 14 is a circuit diagram showing a third embodiment of the switching power supply circuit 100. This embodiment is based on the second embodiment (FIG. 7), and is characterized in that the output format of the switching output unit 110 is changed to a step-down type. Therefore, the same components as those in the second embodiment are designated by the same reference numerals as those in FIG. 7, and duplicated explanations will be omitted. Hereinafter, the feature portions of the present embodiment will be mainly described.

The switching output unit 110 lowers the input voltage Vi (for example, corresponding to the input voltage VIN) by driving the coil current IL using the output transistor N2, and lowers the desired output voltage Vo (for example, logic system power supply voltage VDD). It is a step-down switching output stage that generates (corresponding to), and includes an output transistor N2 (N-channel type MOS electric current effect transistor in the example of this figure), a coil L2, a rectifying diode D2, and an output capacitor Co2.

The drain of the output transistor N2 is connected to the input end of the input voltage Vi. The source of the output transistor N2 is connected to the first end of the coil L2 and the cathode of the rectifier diode D2, respectively. The gate of the output transistor N2 is connected to the output end (= output end of the gate signal S4) of the switching control unit 120. The anode of the rectifying diode D2 is connected to the ground end. The second end of the coil L2 is connected to the output end of the output voltage Vo and the first end of the output capacitor Co2. The second end of the output capacitor Co2 is connected to the ground end.

When the switching output unit 110 is a step-down type, as shown in this figure, the configuration for detecting the coil current IL during the off period of the output transistor N2, that is, the switch current Is flowing through the rectifier diode D2. It is desirable to adopt the configuration to be detected. However, the configuration in which the coil current IL is detected during the ON period of the output transistor N2 is not avoided at all.

Further, as the rectification method of the switching output unit 110, a synchronous rectification method can be adopted instead of the diode rectification method. In that case, the rectifier diode D2 may be replaced with a synchronous rectifier transistor, which may be turned on / off complementarily with the output transistor N2.

As described above, the output format of the switching output unit 110 is not limited to the step-up type of the first embodiment (FIG. 2) and the second embodiment (FIG. 7), and a step-down type can also be adopted. Further, although not shown, it is also optional that the output type of the switching output unit 110 is a buck-boost type.

<On-duty and boost ratio>
FIG. 15 is a correlation diagram between the on-duty Don and the boost ratio (Vo / Vi) in the switching power supply circuit 100 of the first embodiment (FIG. 2). As is well known, in the step-up switching power supply circuit 100, the following equation (1) is established between the on-duty Don and the input voltage Vi and the output voltage Vo. Further, by modifying the equation (1), the boost ratio (Vo / Vi) can be expressed by the following equation (2).

Don = (Vo-Vi) / Vo ... (1)

(Vo / Vi) = 1 / (1-Don) ... (2)

From FIGS. 15 and (2), it can be seen that in the boost-type switching power supply circuit 100, the linearity of the boost ratio (Vo / Vi) collapses as the on-duty Don approaches 1.

In the switching power supply circuit 100 of the first embodiment, the slope of the reference slope voltage V1 (and thus the slope voltage Vslp) is fixed. Therefore, when performing duty control according to the comparison result between the error voltage Verr and the slope voltage Vslp, only the error voltage Verr fluctuates so as to satisfy the above equation (1). That is, not only the output voltage Vo but also the input voltage Vi is included as an element for determining the voltage value of the error voltage Verr.

However, since the output feedback loop for generating the error voltage Verr includes the error amplifier 123 and the phase compensation unit 124, it is difficult to give an appropriate response to the fluctuation of the input voltage Vi.

Therefore, in an application in which the input voltage Vi is liable to fluctuate (for example, a battery-powered electronic device), the line regulation characteristic and the line step characteristic (line transient characteristic) of the switching power supply circuit 100 may deteriorate. The line regulation characteristic refers to the fluctuation characteristic of the output voltage Vo with respect to the continuous fluctuation of the input voltage Vi. On the other hand, the line step characteristic (line transient characteristic) refers to the fluctuation characteristic of the output voltage Vo with respect to the discrete (transient) fluctuation of the input voltage Vi. In the following, a fourth embodiment for appropriately solving such a problem is proposed.

<Switching power supply circuit (fourth embodiment)>
FIG. 16 is a circuit diagram showing a fourth embodiment of the switching power supply circuit 100. The switching power supply circuit 100 of the present embodiment is characterized in that the reference slope voltage generation unit 128 is newly devised while being based on the first embodiment (FIG. 2). Therefore, the same components as those in the first embodiment are designated by the same reference numerals as those in FIG. 2 to omit duplicated explanations, and the feature portions of the present embodiment will be mainly described below.

In the present embodiment, the reference slope voltage generation unit 128 receives the input of the difference voltage (Vo-Vi) between the input voltage Vi and the output voltage Vo, and corresponds to the inverse number (= 1 / (Vo-Vi)). It also has a function of changing the slope of the reference slope voltage V1 (and thus the slope voltage Vslp).

The output voltage Vo is always adjusted to a desired target value by the function of the output feedback loop described above. Therefore, in order to determine the slope of the reference slope voltage Vi, it is not necessary for the reference slope voltage generator 128 to refer to the measured value of the output voltage Vo, and it is sufficient to refer to the predetermined target value of the output voltage Vo. ..

FIG. 17 is a waveform diagram showing a slope adjusting operation of the slope voltage Vslp. The horizontal axis of this figure shows the elapsed time t since the output transistor N1 was turned on, and the vertical axis of this figure is the slope voltage Vslp (solid line and broken line) and the error voltage Verr (dashed line), respectively. The voltage value of is shown.

The higher 1 / (Vo-Vi), the greater the slope of the slope voltage Vslp (see solid line). Therefore, even if the voltage value of the error voltage Verr does not change, the intersection timing (time t11) between the slope voltage Vslp and the error voltage Verr is accelerated. As a result, the on-duty Don of the output transistor N1 becomes small.

On the other hand, the lower 1 / (Vo-Vi), the smaller the slope of the slope voltage Vslp (see the broken line). Therefore, even if the voltage value of the error voltage Verr does not change, the intersection timing (time t12) between the slope voltage Vslp and the error voltage Verr is delayed. As a result, the on-duty Don of the output transistor N1 becomes large.

Due to the slope adjustment operation of the slope voltage Vslp described above, the on-duty Don of the output transistor N1 fluctuates according to 1 / (Vo-Vi). That is, in the switching power supply circuit 100 of the present embodiment, the slope of not only the error voltage Verr but also the slope voltage Vslp fluctuates so as to satisfy the above equation (1). In particular, since the numerator (= Vo-Vi) in equation (1) is canceled by the slope adjustment operation of the slope voltage Vslp, the denominator (=) in equation (1) is a factor that determines the voltage value of the error voltage Verr. Only Vo) remains.

In this way, the response to the fluctuation of the input voltage Vi is performed by the slope adjustment operation of the slope voltage Vslp. Therefore, in the output feedback loop for generating the error voltage Verr, the response to the fluctuation of the input voltage Vi is performed. You don't have to. Therefore, the switching power supply circuit 100 of the present embodiment can improve its line regulation characteristics and line step characteristics (line transient characteristics). In particular, in an application in which the input voltage Vi is liable to fluctuate (for example, a battery-powered electronic device), it is important to improve both characteristics.

<Reference slope voltage generator>
FIG. 18 is a circuit diagram showing a configuration example of the reference slope voltage generation unit 128 (and the voltage addition unit 129). The reference slope voltage generation unit 128 of this configuration example includes a slope current source 128a and a resistor 128b (resistance value: Rb). Further, the voltage addition unit 129 of this configuration example includes a P-channel type MOS field effect transistor P1.

The slope current source 128a is connected between the power supply end and the output end of the slope voltage Vslp, and synchronizes with the on / off control of the output transistor N1 (here, the clock signal CLK) to generate the slope current Ia of the slope waveform. Generate. Further, the slope current source 128a receives the input of the difference voltage (Vo-Vi) between the input voltage Vi and the output voltage Vo, and the slope current Ia corresponds to the inverse number (= 1 / (Vo-Vi)). It has a function to change the tilt.

The inclination adjusting operation of the slope current Ia can be easily understood by replacing the slope voltage Vslp in FIG. 17 with the slope current Ia. That is, the higher the 1 / (Vo-Vi), the larger the slope of the slope current Ia, and conversely, the lower the 1 / (Vo-Vi), the smaller the slope of the slope current Ia.

The first end of the resistor 128b is connected to the output end of the slope voltage Vslp. The second end of the resistor 128b is connected to the source of transistor P1. The drain of the transistor P1 is connected to the ground end. A sense voltage V2 is applied to the gate of the transistor P1. The resistor 128b functions as a current / voltage conversion element that converts the slope current Ia flowing through itself into the reference slope voltage V1 (= Ia × Rb).

In the reference slope voltage generation unit 128 of this configuration example, the slope voltage Vslp becomes the lower limit value VslpL during the off period (V1 = Ia × Rb = 0, V2 = 0) of the output transistor N1. The lower limit value VslpL corresponds to the on-threshold voltage Vth of the transistor P1.

On the other hand, the slope voltage Vslp during the ON period of the output transistor N1 is a voltage value (= Vth + V1 + V2) obtained by adding the reference slope voltage V1 (= Ia × Rb) and the sense voltage V2 to the above-mentioned lower limit value VslpL.

When the current mode control method is not adopted, the voltage addition unit 129 may be omitted and the reference slope voltage V1 may be output as the slope voltage Vslp.

<Slope current source>
FIG. 19 is a circuit diagram showing a configuration example of the slope current source 128a. The slope current source 128a of this configuration example includes a charging current generation unit a10, a capacitor a20, a charge / discharge switch a30, a charge / discharge control unit a40, and a voltage / current conversion unit a50.

The charging current generating unit a10 is connected between the power supply end and the capacitor a20, and generates a charging current Ix. The charging current generating unit a10 receives an input of a difference voltage (Vo-Vi) between the input voltage Vi and the output voltage Vo, and the charging current Ix is corresponding to the reciprocal of the voltage (= 1 / (Vo-Vi)). It has a function to change the current value of. More specifically, the higher the 1 / (Vo-Vi), the larger the current value of the charging current Ix, and conversely, the lower the 1 / (Vo-Vi), the smaller the current value of the charging current Ix.

The capacitor a20 is connected between the output end and the ground end of the charging current generating unit a10, and is charged by the charging current Ix. When the charge / discharge switch a30 is off, the capacitor a20 is charged by the charging current Ix, so that the charging voltage Vx of the capacitor a20 rises. On the other hand, when the charge / discharge switch a30 is turned on, the capacitor a20 is discharged via the charge / discharge switch a30, so that the charging voltage Vx is reset to a zero value.

The charge / discharge switch a30 is connected between both ends of the capacitor a20, and switches the charge / discharge of the capacitor according to the on / off control of the charge / discharge control unit a40.

The charge / discharge control unit a40 performs on / off control of the charge / discharge control unit a40 in synchronization with the on / off control (here, the clock signal CLK) of the output transistor N1. For example, the charge / discharge control unit a40 turns off the charge / discharge switch a30 during the on period of the output transistor N1 and turns on the charge / discharge switch a30 during the off period of the output transistor N1.

The voltage / current conversion unit a50 includes N-channel type MOS field effect transistors a51 and a52, P-channel type MOS field effect transistors a53 and a54, and a resistor a55 (resistance value: Rx), and the charging voltage Vx of the capacitor a20. Is converted into a slope current Ia.

The drain of the transistor a51 is connected to the output end of the charging current generation unit a10. The source of the transistor a51 is connected to the application end of the charging voltage Vx. Both the gate of the transistor a51 and the gate of the transistor a52 are connected to the drain of the transistor a51. The drain of the transistor a52 is connected to the first end of the resistor a55. The second end of the resistor a55 is connected to the grounded end.

Both the source of the transistor a53 and the source of the transistor a54 are connected to the power supply end. Both the gate of the transistor a53 and the gate of the transistor a54 are connected to the drain of the transistor a53. The drain of the transistor a53 is connected to the drain of the transistor a52. The drain of the transistor a54 corresponds to the output end of the slope current Ia.

In the voltage / current conversion unit a50 of this configuration example, the transistors a51 and a52 form a first current mirror, and operate so that their drain voltages coincide with each other. That is, the same voltage as the charging voltage Vx of the capacitor a20 is applied to the first end of the resistor a55. Therefore, a reference current Iy (= Vx / Rx) showing the same behavior as the charging voltage Vx flows through the resistor a55. Further, the transistors a53 and a54 form a second current mirror, and mirror the reference current Iy to generate a slope current Ia (∝Iy).

The higher 1 / (Vo-Vi), the larger the current value of the charging current Ix and the larger the slope of the charging voltage Vx. Therefore, the slope of the reference current Iy becomes large, and the slope current Ia becomes large. On the contrary, as 1 / (Vo-Vi) becomes lower, the current value of the charging current Ix becomes smaller and the slope of the charging voltage Vx becomes smaller. Therefore, the slope of the reference current Iy becomes small, and by extension, the slope of the slope current Ia becomes small.

FIG. 20 is a circuit diagram showing a configuration example of the charging current generation unit a10. The charging current generation unit a10 of this configuration example is an analog divider including current sources a11 and a12, a logarithmic conversion unit a13, and a transconductance amplifier a14.

The current source a11 generates a predetermined fixed current I11.

The current source a12 receives an input of a difference voltage (Vo-Vi) between the input voltage Vi and the output voltage Vo, and generates a variable current I12 proportional to the input.

The logarithmic conversion unit a13 includes three diodes D10 to D12, and logarithmically transforms the fixed current I11 and the variable current I12 to generate the logarithmic voltages V11 and V12, respectively. The anode of the diode D10 is connected to the end where a constant voltage is applied. The cathode of the diode D10 is connected to the anode of each of the diodes D11 and D12. A current source a11 is connected between the cathode of the diode D11 and the grounded end, and a logarithmic voltage V11 is output from the cathode of the diode D11. A current source a12 is connected between the cathode of the diode D12 and the grounded end, and a logarithmic voltage V12 is output from the cathode of the diode D12. That is, the diode D11 corresponds to the first diode that converts the fixed current I11 into the logarithmic voltage V11. On the other hand, the diode D12 corresponds to a second diode that converts the variable current I12 into a logarithmic voltage V12.

The transconductance amplifier a14 includes npn-type bipolar transistors Q1 and Q2, pnp-type bipolar transistors Q3 to Q8, resistors R11 to R13, and a current source CS0, and is charged by receiving differential inputs of logarithmic voltages V11 and V12. Generates a current Ix.

The base of the transistor Q1 is connected to the application end of the logarithmic voltage V11. The base of the transistor Q2 is connected to the application end of the logarithmic voltage V12. The emitters of the transistors Q1 and Q2 are connected to the first end of the current source CS0. The second end of the current source CS0 is connected to the ground end.

The first end of the resistor R11 is connected to the power supply end. The second end of the resistor R11 is connected to the emitter of the transistor Q3. The base and collector of transistor Q3 are connected to the emitter of transistor Q4. The base and collector of transistor Q4 are connected to the collector of transistor Q1.

The first end of each of the resistors R12 and R13 is connected to the power supply end. The second end of the resistor R12 is connected to the emitter of the transistor Q5. The second end of the resistor R13 is connected to the emitter of the transistor Q6. The base of each of the transistors Q5 and Q6 is connected to the collector of the transistor Q6. The collector of transistor Q5 is connected to the emitter of transistor Q7. The collector of transistor Q6 is connected to the emitter of transistor Q8. The base of each of the transistors Q7 and Q8 is connected to the collector of the transistor Q7. The collector of the transistor Q7 is connected to the collector of the transistor Q2. The collector of the transistor Q8 corresponds to the output end of the charging current Ix.

In the charging current generation unit a10 of this configuration example, the forward voltage drop Vf of each of the diodes D11 and D12 exhibits a logarithmic characteristic with respect to the current flowing through each. Therefore, assuming that the anode voltage common to the diodes D11 and D12 is V10, the logarithmic voltages V11 and V12 can be represented by the following equations (3) and (4), respectively. In both equations, Vt is the thermal voltage of the diodes D11 and D12, and Is is the reverse saturation current of the diodes D11 and D12.

V11 = V10-Vt · ln (I11 / Is)… (3)

V12 = V10-Vt · ln (I12 / Is)… (4)

Further, the logarithmic voltages V11 and V12 are differentially input to the transconductance amplifier a14. At this time, the difference voltage ΔV between the logarithmic voltages V11 and V12 is expressed by the following equation (5).

ΔV = V12-V11 = Vt · ln (I11 / I12)… (5)

The input stage of the transconductance amplifier a14 is formed of bipolar transistors Q1 and Q2, and the collector currents I21 and I22, respectively, exhibit exponential characteristics with respect to the base voltage. That is, in the transconductance amplifier a14, the difference voltage ΔV is inversely logarithmically converted when the charging current Ix is generated.

As a result, the charging current Ix has a current value corresponding to the value obtained by dividing the fixed current I11 by the variable current I12 (= I11 / I12). Therefore, if the current sources a11 and a12 are designed so that I12 = I11 × (Vo-Vi), the current value of the charging current Ix can be changed according to (1 / (Vo-Vi)). Can be done.

For example, when (Vo-Vi) decreases and the variable current I12 becomes smaller than the fixed current I11, the logarithmic voltage V12 becomes higher than the logarithmic voltage V11 and the collector current I22 becomes larger than the collector current I21. As a result, the charging current Ix increases. On the contrary, when (Vo-Vi) increases and the variable current I12 becomes larger than the fixed current I11, the logarithmic voltage V12 becomes lower than the logarithmic voltage V11 and the collector current I22 becomes smaller than the collector current I21. .. As a result, the charging current Ix decreases.

In this figure, a configuration using an analog divider is given as an example as a means for performing the division process of 1 / (Vo-Vi), but the circuit configuration of the analog divider is limited to the above. Other circuit configurations may be adopted instead of the above. It is also possible to use a digital divider instead of the analog divider.

Further, regarding the reference slope voltage generation unit 128, a configuration in which the input of (Vo-Vi) is received and the division processing is performed internally is given as an example, but the configuration is not limited to this, and is originally 1 It may be configured to accept the input of / (Vo-Vi).

<Application to tablet devices>
FIG. 21 is an external view of the tablet terminal. The tablet terminal X has a liquid crystal display X1 having a touch panel function. The liquid crystal display X1 is an example of the liquid crystal display device 1 described so far, and the switching power supply circuit 100 described above can be preferably used as the power supply means thereof. However, the mounting target of the liquid crystal display device 1 is not limited to the tablet terminal, and can be mounted on various electronic devices (notebook personal computers, etc.).

<Other variants>
In addition to the above-described embodiment, various technical features disclosed in the present specification can be modified in various ways without departing from the spirit of the technical creation. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is shown not by the description of the above-mentioned embodiment but by the scope of claims. It should be understood that it includes all changes that fall within the meaning and scope of the claims.

The switching power supply circuit disclosed in the present specification is suitably used as a power supply means for an application that may cause load fluctuations or as a power supply means for an application (such as a battery-powered electronic device) in which the input voltage is likely to fluctuate. It is possible.

1 Liquid crystal display device 10 Liquid crystal drive device 11 System power supply unit 12 Timing control unit 13 Level shifter 14 Gate driver 15 Source driver 16 Gamma voltage generator 17 Common voltage generator 20 Liquid crystal display panel 100 Switching power supply circuit 110 Switching output unit 120 Switching control unit 121 Digital / analog conversion unit 122 Feedback voltage generation unit 123 Error amplifier 124 Phase compensation unit 125 Clock signal generation unit 126 Set signal generation unit 127 Maximum duty setting unit 128 Reference slope voltage generation unit 128a Slope current source 128b Resistance 129 Voltage addition unit 12A Comparator 12B OR gate 12C RS flip flop 12D driver 12E sense voltage holding part N1, N2 output transistor (N channel type MOS electric field effect transistor)
P1 P-channel type MOS field effect transistor L1, L2 coil D1, D2 rectifying diode Co1, Co2 output capacitor Rs sense resistance R1 to R3 resistance C1 capacitor E1, E4 switch E2, E5 capacitor E3 control unit a10 charging current generator a11, a12 Current source a13 Log conversion unit a14 Transconductance amplifier a20 Capacitor a30 Charge / discharge switch a40 Charge / discharge control unit a50 Voltage / current converter a51, a52 N-channel type MOS field effect transistor a53, a54 P-channel type MOS field effect transistor a55 Resistance CS0 Current source Q1, Q2 npn type bipolar transistor Q3 to Q8 pn type bipolar transistor D10 to D12 Diode R11 to R13 Resistance X Tablet terminal X1 Liquid crystal display

Claims (15)

A switching output unit that generates an output voltage from an input voltage by driving a coil current using an output transistor.
A switching control unit that controls on / off of the output transistor so that the output voltage or the feedback voltage corresponding thereto and a predetermined reference voltage match.
Have,
The switching control unit
A reference slope voltage generator that generates a reference slope voltage,
A sense voltage holding unit that generates a holding sense voltage by latching the sense voltage corresponding to the coil current at a predetermined timing,
A voltage addition unit that generates a slope voltage by adding the reference slope voltage and the holding sense voltage.
The on-duty of the output transistor is determined using the slope voltage .
The sense voltage holding unit is
The first switch whose first end is connected to the input end of the sense voltage,
A second switch whose first end is connected to the second end of the first switch and whose second end is connected to the output end of the holding sense voltage.
A first capacitor whose first end is connected to the second end of the first switch and whose second end is connected to the grounded end.
A second capacitor whose first end is connected to the output end of the holding sense voltage and whose second end is connected to the ground end.
A control unit that performs complementary on / off control of the first switch and the second switch,
A switching power supply circuit characterized by including. The switching control unit
An error amplifier that generates an error voltage according to the difference value between the output voltage or the feedback voltage and the reference voltage, and
A comparator that compares the error voltage with the slope voltage to generate a comparison signal,
The switching power supply circuit according to claim 1 , further comprising the above, and determining the on-duty of the output transistor according to the comparison signal. The switching control unit
A set signal generator that generates a set signal pulse at a predetermined pulse period,
An RS flip-flop that receives input of a reset signal corresponding to the set signal and the comparison signal and outputs a pulse width modulated signal, and
A driver that accepts the input of the pulse width modulation signal and outputs the on / off control signal of the output transistor.
The switching power supply circuit according to claim 2, further comprising. The switching control unit
A maximum duty setting unit that generates a pulse of the maximum duty setting signal when the maximum on-time elapses after the pulse is generated in the set signal.
A logic gate that logically synthesizes the comparison signal and the maximum duty setting signal to generate the reset signal, and
The switching power supply circuit according to claim 3, further comprising. A switching output unit that generates an output voltage from an input voltage by driving a coil current using an output transistor.
A switching control unit that controls on / off of the output transistor so that the output voltage or the feedback voltage corresponding thereto and a predetermined reference voltage match.
Have,
The switching control unit
A reference slope voltage generator that generates a reference slope voltage,
A sense voltage holding unit that generates a holding sense voltage by latching the sense voltage corresponding to the coil current at a predetermined timing,
A voltage addition unit that generates a slope voltage by adding the reference slope voltage and the holding sense voltage.
An error amplifier that generates an error voltage according to the difference value between the output voltage or the feedback voltage and the reference voltage, and
A comparator that compares the error voltage with the slope voltage to generate a comparison signal,
A set signal generator that generates a set signal pulse at a predetermined pulse period,
An RS flip-flop that receives input of a reset signal corresponding to the set signal and the comparison signal and outputs a pulse width modulated signal, and
A driver that accepts the input of the pulse width modulation signal and outputs the on / off control signal of the output transistor.
A maximum duty setting unit that generates a pulse of the maximum duty setting signal when the maximum on-time elapses after the pulse is generated in the set signal.
A logic gate that logically synthesizes the comparison signal and the maximum duty setting signal to generate the reset signal, and
A switching power supply circuit comprising, and determining the on-duty of the output transistor according to the comparison signal. The switching control unit further includes a clock signal generation unit that generates a clock signal at a predetermined reference frequency.
The switching power supply circuit according to any one of claims 1 to 5 , wherein the sense voltage holding unit operates in synchronization with the clock signal. The switching power supply circuit according to any one of claims 1 to 6 , wherein the switching output unit is a step-up type, a step-down type, or a buck-boost type. The switching power supply circuit according to any one of claims 1 to 7.
A driver that receives power from the switching power supply circuit to drive the load,
A load drive device characterized by having. The load drive device according to claim 8 and
A liquid crystal display panel driven as a load of the load drive device and
A liquid crystal display device characterized by having. It is connected to a switching output unit that generates an output voltage from an input voltage by driving a coil current using an output transistor, and the output voltage or a feedback voltage corresponding thereto is matched with a predetermined reference voltage. A switching control circuit configured to control the on / off of the output transistor.
The switching control circuit
A reference slope voltage generator that generates a reference slope voltage,
A sense voltage holding unit that generates a holding sense voltage by latching the sense voltage corresponding to the coil current at a predetermined timing,
A voltage addition unit that generates a slope voltage by adding the reference slope voltage and the holding sense voltage.
The on-duty of the output transistor is determined using the slope voltage .
The sense voltage holding unit is
The first switch whose first end is connected to the input end of the sense voltage,
A second switch whose first end is connected to the second end of the first switch and whose second end is connected to the output end of the holding sense voltage.
A first capacitor whose first end is connected to the second end of the first switch and whose second end is connected to the grounded end.
A second capacitor whose first end is connected to the output end of the holding sense voltage and whose second end is connected to the ground end.
A control unit that performs complementary on / off control of the first switch and the second switch,
A switching control circuit characterized by including. An error amplifier that generates an error voltage according to the difference value between the output voltage or the feedback voltage and the reference voltage, and
A comparator that compares the error voltage with the slope voltage to generate a comparison signal,
The switching control circuit according to claim 10 , further comprising the above, and determining the on-duty of the output transistor according to the comparison signal. A set signal generator that generates a set signal pulse at a predetermined pulse period,
An RS flip-flop that receives input of a reset signal corresponding to the set signal and the comparison signal and outputs a pulse width modulated signal, and
A driver that accepts the input of the pulse width modulation signal and outputs the on / off control signal of the output transistor.
The switching control circuit according to claim 11, further comprising. A maximum duty setting unit that generates a pulse of the maximum duty setting signal when the maximum on-time elapses after the pulse is generated in the set signal.
A logic gate that logically synthesizes the comparison signal and the maximum duty setting signal to generate the reset signal, and
The switching control circuit according to claim 12, further comprising. It is connected to a switching output unit that generates an output voltage from an input voltage by driving a coil current using an output transistor, and the output voltage or a feedback voltage corresponding thereto is matched with a predetermined reference voltage. A switching control circuit configured to control the on / off of the output transistor.
The switching control circuit
A reference slope voltage generator that generates a reference slope voltage,
A sense voltage holding unit that generates a holding sense voltage by latching the sense voltage corresponding to the coil current at a predetermined timing,
A voltage addition unit that generates a slope voltage by adding the reference slope voltage and the holding sense voltage.
An error amplifier that generates an error voltage according to the difference value between the output voltage or the feedback voltage and the reference voltage, and
A comparator that compares the error voltage with the slope voltage to generate a comparison signal,
A set signal generator that generates a set signal pulse at a predetermined pulse period,
An RS flip-flop that receives input of a reset signal corresponding to the set signal and the comparison signal and outputs a pulse width modulated signal, and
A driver that accepts the input of the pulse width modulation signal and outputs the on / off control signal of the output transistor.
A maximum duty setting unit that generates a pulse of the maximum duty setting signal when the maximum on-time elapses after the pulse is generated in the set signal.
A logic gate that logically synthesizes the comparison signal and the maximum duty setting signal to generate the reset signal, and
A switching control circuit comprising, and determining the on-duty of the output transistor according to the comparison signal. It further includes a clock signal generator that generates a clock signal at a predetermined reference frequency.
The switching control circuit according to any one of claims 10 to 14 , wherein the sense voltage holding unit operates in synchronization with the clock signal.

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