JP4117995B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as a high-speed CPU, a high-speed DSP, a high-speed ASIC, or a high-speed memory and a semiconductor device having a high-speed interface circuit, and more particularly to a semiconductor device having a delay time adjustment function for a clock or other signal.
[0002]
[Prior art]
In recent years, high-speed processors have an operating frequency of several hundred MHz, and clock design is important for speeding up. In designing a high-speed semiconductor device, in order to reduce the phase shift of the clock of the semiconductor device (hereinafter referred to as clock skew) using circuit design technology in a design process, layout technology with a CAD tool, etc., with the goal of high-speed operation. Technology is used.
[0003]
As the circuit design technique, a technique for constructing a circuit with the same clock signal by a super buffer or the like, or a circuit to which a clock is inputted is made capacitively equivalent or a clock buffer skew is reduced while changing a clock buffer size. There is a technology to design to become. As the layout technique, there is a technique in which clocks are hierarchically configured on a tree, and a clock circuit is automatically created and automatically laid out on an automatic placement and routing tool so that delay times are equivalent.
[0004]
For example, in Japanese Patent Application Laid-Open No. 9-282444, in a semiconductor circuit having a plurality of clock systems, in order to reduce clock skew, a circuit such as a clock oscillator, a frequency divider, and a phase comparator is used. Provides a small circuit. Japanese Patent Laid-Open No. 10-124553 discloses a clock tree that can reduce the influence of clock skew caused by individual variations of clock buffers, the number of registers connected to the output of each clock buffer final stage, and the like. In order to provide a generation method, the clock tree generation for classifying the registers constituting the logic circuit and constructing a clock tree for supplying the clock pulses to the respective registers based on the classified registers and the period time of the clock pulses is provided. A method is disclosed, and the result of generating a clock tree is reflected in a logic circuit.
[0005]
[Problems to be solved by the invention]
In the conventional technology as described above, a semiconductor device having a circuit that reduces clock skew at the design stage is provided, and the designed semiconductor device is manufactured by a wafer process. Variations in each process that cannot be performed cause variations in electrical characteristics. For this reason, the clock skew value is slightly different for each LSI chip on the wafer, and due to the variation, a chip that does not reach the target operating frequency when viewed for each chip can be obtained. Due to such variations, even in the case of LSI chips manufactured under the same conditions, processors and memory products were selected by testing and sold with different added values as chips having different operation speed versions.
[0006]
Further, in order to increase the operation speed of the chip, not only a small clock skew is necessarily good, but a small skew may increase the operating frequency of the chip. For example, in the circuit shown in FIG. 4, the output signal of the flip-flop 101 is input to the combinational circuit 104 at the rising edge of the clock CK1, and the output signal of the combinational circuit 104 is input to the flip-flop 102 at the rising edge of the clock CK2. An output signal of the flip-flop 102 is input to the combinational circuit 105. Further, the output signal of the combinational circuit 105 is input to the flip-flop 103 at the rising edge of the clock CK3.
[0007]
In the conventional clock cycle based synchronous design, the clocks CK1 to CK3 are designed to have as little skew as possible, and in the combinational circuits 104 and 105, the circuit having the longer logical operation time is used as a critical path, and the clock cycle time (operation Frequency). For example, when the combinational circuit 104 is critical and the calculation time of the combinational circuit 105 has a margin, the calculation time given to the combinational circuit 104 is delayed by delaying the phase of the clock CK2 from the clocks CK1 and CK3. Since the time increases, the overall operating frequency can be increased. On the other hand, if the delay time is too long, the operation time of the combinational circuit 105 is reduced, and fine tuning is required.
[0008]
However, in simulations that assume delay times when completed in the design process, errors due to modeling during simulation, estimation errors in delay times, delays due to crosstalk between signals during actual operation, and actual current flow Since errors such as a voltage drop are included, it cannot be completely corrected at the design stage by circuit simulation such as logic simulation or SPICE. For this reason, variations in the wafer process, which is a manufacturing process, cause variations in the clock delay and delay of each signal in the semiconductor device, making it impossible to achieve the target value of the operating frequency, or the necessary signal AC. There was a problem that the yield was lowered due to the failure that the characteristics could not be achieved. For this reason, it is necessary to repeat design trial manufacture until the target operating frequency and the target yield can be achieved, resulting in a problem that the development period and cost increase.
[0009]
The present invention has been made to solve the above-described problems. In a test after a wafer process, the optimum clock delay, clock skew and signal delay are tested, and the clock delay and signal delay are determined according to the test result. A signal delay adjustment function that can improve the operating frequency by improving the operating frequency, improve the defective yield due to the operating frequency, shorten the development design period, and reduce the cost. An object is to obtain a semiconductor device having the same.
[0010]
[Means for Solving the Problems]
  The semiconductor device according to the present invention is a semiconductor device having a delay time adjustment function for adjusting and setting the delay time of an input signal.
  Consisting of a delay circuit that delays a signal with a plurality of different delay times, and a signal delay unit that delays an input signal with a selected delay time;
  A delay time selection unit that selects a delay time of the signal delay unit according to input data;
  A data generation unit that generates data for instructing a delay time to be selected with respect to the delay time selection unit;
  A data switching unit that switches data input from the outside and data generated by the data generation unit according to a predetermined signal from the outside and outputs the data to the delay time selection unit;
With,
The data generator is
At least one series circuit in which a plurality of fuses are connected in series, connected between predetermined potentials indicating binary data;
A switching circuit for controlling connection between the series circuit and a predetermined potential in response to a predetermined signal from the outside;
The delay time of the signal delay unit selected using the data input from the outside is generated by the combination of the fuses to be cut and selected by the delay time selection unit Generate dataIs.
[0011]
  Also,The semiconductor device according to the present invention is a semiconductor device having a delay time adjustment function for adjusting and setting the delay time of an input signal.
Consisting of a delay circuit that delays a signal with a plurality of different delay times, and a signal delay unit that delays an input signal with a selected delay time;
A delay time selection unit that selects a delay time of the signal delay unit according to input data;
A data generation unit that generates data for instructing a delay time to be selected with respect to the delay time selection unit;
A data switching unit that switches data input from the outside and data generated by the data generation unit according to a predetermined signal from the outside and outputs the data to the delay time selection unit;
With
  The data generator is
At least one series circuit connected in series with a plurality of trimmable resistors connected between predetermined potentials indicative of binary data;
A switching circuit for controlling connection between the series circuit and a predetermined potential in response to a predetermined signal from the outside;
And generating the data with a combination of the resistors set by trimming,Data generation is performed such that the delay time of the signal delay unit selected using data input from the outside is selected by the delay time selection unit.Is.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Next, the present invention will be described in detail based on the embodiments shown in the drawings.
FIG. 1 is a circuit diagram showing an example of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a clock generation circuit for adjusting the delay of an inputted reference clock and generating and outputting an optimum clock is shown. It is shown as an example, and a case where four types of clocks are generated and output by four delay adjustment circuits is shown as an example.
In FIG. 1, the clock generation circuit 1 is composed of four delay adjustment circuits D1 to D4. The delay adjustment circuits D1 to D4 are input with a clock signal CLK optimized by a technique such as a clock tree and a test mode signal TEST that becomes a high level when a clock skew value test is performed.
[0016]
In order to adjust the delay time of the clock CLK, the delay adjustment circuit D1 has data signals TD0 and TD1, the delay adjustment circuit D2 has data signals TD2 and TD3, and the delay adjustment circuit D3 has data signals TD4 and TD4. The data signals TD6 and TD7 are input to the delay adjustment circuit D4. The delay adjustment circuits D1 to D4 output corresponding clock signals CLK1 to CLK4 generated by delaying the clock signal CLK based on these input signals. Since the delay adjustment circuits D1 to D4 are formed with the same circuit configuration, only the internal circuit example of the delay adjustment circuit D1 is shown in FIG. 1, and the internals of the other delay adjustment circuits D2 to D4 are shown. The circuit is omitted. Therefore, hereinafter, the operation of the delay adjustment circuit D1 will be described, and the operations of the other delay adjustment circuits D2 to D4 are the same as those of the delay adjustment circuit D1, and the description thereof will be omitted.
[0017]
The delay adjustment circuit D1 includes a multiplexer 10 formed by inverters 11 and 12, NAND circuits 13 to 16, and NOR circuits 17 and 18, P-channel MOS transistors (hereinafter referred to as PMOS transistors) 21 and 22, and fuses 23 to 23. And a delay time setting unit 20 formed by H.26. Furthermore, the delay adjustment circuit D1 includes a decoder 30 formed by inverters 31 to 36 and NAND circuits 37 to 40, and a delay time adjustment unit 50 formed by buffers 51 to 54 and transmission gates 55 to 58. .
[0018]
In the multiplexer 10, the inverters 11 and 12 are connected in series in the forward direction, the test mode signal TEST is input to the input terminal of the series circuit, and the output terminal of the series circuit is one of the NAND circuits 13 and 15, respectively. Is connected to the input terminal. The data signal TD 0 is input to the other input terminal of the NAND circuit 13, and the output terminal of the NAND circuit 13 is connected to one input terminal of the NOR circuit 17. The data signal TD 1 is input to the other input terminal of the NAND circuit 15, and the output terminal of the NAND circuit 15 is connected to one input terminal of the NOR circuit 18.
[0019]
A connection portion between the inverter 11 and the inverter 12 is connected to one input terminal of each of the NAND circuits 14 and 16. The other input terminal of the NAND circuit 14 is connected to the connection part between the fuses 23 and 24 of the delay time setting part 20 and receives the data signal TDa. The output terminal of the NAND circuit 14 is connected to the other input terminal of the NOR circuit 17. The other input terminal of the NAND circuit 16 is connected to a connection part between the fuses 25 and 26 of the delay time setting part 20 and receives the data signal TDb. The output terminal of the NAND circuit 16 is connected to the other input terminal of the NOR circuit 18.
[0020]
In the delay time setting unit 20, a test mode signal TEST is input to each gate of the PMOS transistors 21 and 22, and each source of the PMOS transistors 21 and 22 is connected to a power input terminal VCC to which a DC power is supplied. ing. A series circuit of fuses 23 and 24 is connected between the drain of the PMOS transistor 21 and the ground. Similarly, a series of fuses 25 and 26 is connected between the drain of the PMOS transistor 22 and the ground. The circuit is connected.
[0021]
On the other hand, the output terminal of the NOR circuit 17 in the multiplexer 10 is connected to the input terminal of the inverter 31 in the decoder 30 and one input terminal of each of the NAND circuits 37 and 39. Similarly, the output terminal of the NOR circuit 18 in the multiplexer 10 is connected to the input terminal of the inverter 32 in the decoder 30, the other input terminal of the NAND circuit 37, and one input terminal of the inverter 38.
[0022]
In the decoder 30, the output terminal of the inverter 31 is connected to the other input terminal of the NAND circuit 38 and one input terminal of the NAND circuit 40, and the output terminal of the inverter 32 is the other input terminal of the NAND circuits 39 and 40. Connected to each end. The output terminals of the NAND circuits 37 to 40 are connected to the gates of N-channel MOS transistors (hereinafter referred to as NMOS transistors) in the corresponding transmission gates 55 to 58 in the delay time adjustment unit 50 via the corresponding inverters 33 to 36, respectively. It is connected. Further, the output terminals of the NAND circuits 37 to 40 are connected to the gates of the PMOS transistors of the corresponding transmission gates 55 to 58 in the delay time adjustment unit 50.
[0023]
In the delay time adjustment unit 50, the buffers 51 to 54 are connected in series in the forward direction, and the clock signal CLK is input to the input end of the buffer 51 that forms the input end of the series circuit. Furthermore, each output terminal of the buffers 51-52 is connected to one input / output terminal of the corresponding transmission gate 55-58, and the other input / output terminal of the transmission gate 55-58 is connected to each other to adjust delay. This constitutes the output terminal of the circuit D1, and the clock signal CLK1 is output.
[0024]
In such a configuration, the multiplexer 10 includes any two of the input data signals TD0 and TD1 or the data signals TDa and TDb input from the delay time setting unit 20 according to the signal level of the test mode signal TEST. Each signal is output. The delay time setting unit 20 generates and outputs data signals TDa and TDb corresponding to the cut states of the fuses 23 to 26 according to the signal level of the test mode signal TEST. On the other hand, the decoder 30 decodes the data signal output from the multiplexer 10 and turns on any one of the transmission gates 55 to 58 of the delay time adjustment unit 50. The delay time adjusting unit 50 outputs a clock signal CLK delayed by a time corresponding to the number of buffers connected to the input / output terminals of the transmission gate turned on by the decoder 30 as the clock signal CLK1.
[0025]
When the high-level test mode signal TEST is input, the multiplexer 10 validates the input data signals TD0 and TD1, and outputs a data signal corresponding to the signal level of the data signals TD0 and TD1 to the NOR circuit 17 and Output from each of the 18 output terminals. At this time, both the PMOS transistors 21 and 22 of the delay time setting unit 20 are off. In such a state, the delay amount of the clock signal CLK1 with respect to the clock signal CLK can be changed by changing the combination of the data signals TD0 and TD1.
[0026]
That is, when (TD0, TD1) = (0, 0), the transmission gate 55 is selected and is turned on exclusively, the clock signal CLK is delayed by the buffer 51, and the delay time is the shortest with respect to the clock signal CLK. It is output as the clock signal CLK1.
When (TD0, TD1) = (1, 0), the transmission gate 56 is selected and turned on exclusively, the clock signal CLK is delayed by the buffers 51 and 52, and is the second delay time with respect to the clock signal CLK. Is output as a short clock signal CLK1.
[0027]
When (TD0, TD1) = (0, 1), the transmission gate 57 is selected and is turned on exclusively, the clock signal CLK is delayed by the buffers 51 to 53, and is the second delay time with respect to the clock signal CLK. Is output as a long clock signal CLK1.
When (TD0, TD1) = (1, 1), the transmission gate 58 is selected and is exclusively turned on, and the clock signal CLK is delayed by the buffers 51 to 54, and has the longest delay time with respect to the clock signal CLK. It is output as the clock signal CLK1.
[0028]
In this way, the data combination of the data signals TD0 and TD1 is changed to obtain the data combination of the data signals TD0 and TD1 that is the optimum clock signal CLK1. For example, assuming that (TD0, TD1) = (1, 0) is optimal, the combination of the data signals TDa and TDb from the delay time setting unit 20 when the test mode signal TEST is at the low level. The fuses 24 and 25 are cut by a laser trimming technique or the like so that (TDa, TDb) = (1, 0).
[0029]
The laser trimming technique is a method in which a fuse composed of aluminum or polycrystalline silicon is selectively blown by laser irradiation or the like, or polycrystalline silicon which is in a high resistance state in the initial state is selectively laser-annealed. This shows a technique for lowering resistance by reducing resistance. Such a technique is a redundancy technique disclosed in Japanese Patent Laid-Open Nos. 5-36297 and 11-17010, in which a defective address is switched to a spare address for a defect in a highly integrated IC memory. In addition, it is used in a technique for trimming a resistance value disclosed in Japanese Patent Laid-Open No. 9-232119.
[0030]
On the other hand, when the test mode signal TEST is at a low level when the fuses 23 to 26 are not cut, a very small current flows between the power input terminal VCC and the ground by the fuses 23 to 26. However, when the test mode signal TEST is at a high level, the PMOS transistors 21 and 22 are turned off, so that no current flows between the power input terminal VCC and the ground. Therefore, in a semiconductor device having a standby operation mode in which power consumption is reduced in a standby state, the current consumption during standby can be accurately measured by setting the test mode signal TEST to a high level. The standby test can be done normally. Further, after the fuse of the delay time setting unit 20 is cut, the test mode signal TEST is set to a low level and the current consumption during the standby is measured to determine whether or not the fuse has been cut normally. it can.
[0031]
As a result, when the test mode signal TEST is at the low level, the delay adjustment circuit D1 turns on the transmission gate 57 regardless of the data signals TD0 and TD1, and buffers 51 to 53 for the clock signal CLK. The clock signal CLK1 delayed at is output. Similarly, the delay adjustment circuits D2 to D4 also output clock signals CLK2 to CLK4 adjusted to a desired delay time with respect to the clock signal CLK, respectively.
[0032]
In the above description, the case where the clock signals CLK1 to CLK4 adjusted to the desired delay time by the delay adjustment circuits D1 to D4 are output to one clock signal CLK is described as an example. However, as shown in FIG. 2, the signals SIG1 to SIG4 are input to the delay adjustment circuits D1 to D4 in correspondence with each other, and each delay adjustment circuit D1 to D4 adjusts the delay time with respect to the input signals SIG1 to SIG4. The signals TSIG1 to TSIG4 subjected to the above may be output.
[0033]
1 may be connected to a series circuit in which a plurality of buffers are connected in series instead of the buffer 51. Similarly, in the buffers 52 to 54, a plurality of buffers may be connected. A series circuit connected in series may be replaced. By doing so, the variation of the delay time adjustment amount can be changed.
[0034]
For example, when designing an ASIC such as a high-speed gate array or a standard cell, the delay adjustment circuit D1 of FIG. 1 may be configured as shown in FIG. In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted here, and only differences from FIG. 1 are described.
[0035]
3 is different from FIG. 1 in that the delay time can be adjusted to two types of delay time in FIG. 3, the NAND circuits 15 and 16 and the NOR circuit 18 are eliminated from the multiplexer 10 of FIG. 1, and the PMOS transistor 22 and the fuses 25 and 26 are eliminated from the delay time setting unit 20 of FIG. Further, in FIG. 3, the inverters 30 to 36 and the NAND circuits 37 to 40 are eliminated from the decoder 30 of FIG. 1, and the buffers 53 and 54 and the transmission gates 57 and 58 are eliminated from the delay time adjusting unit 50 of FIG. Instead of 52, a series circuit of buffers 61 and 62 was connected and an output driver 63 was added.
[0036]
When designing an ASIC such as a high-speed gate array or a standard cell, various variations of the delay time in the delay time adjustment unit are made by changing the buffer 52 to a series circuit of buffers 61 and 62 as shown in FIG. Each changed macro cell or each macro cell of the variation in which the driver size of the output driver 63 is changed is created in advance, and the macro cell is selected and incorporated at a position where the delay is to be adjusted, so that the fuse is blown after the chip is manufactured and the delay time is Can be tuned. For this reason, it is possible to easily improve the timing such as the operating frequency.
[0037]
Further, since the delay time of the optimum design value can be found at the prototype stage without cutting the fuses 23 to 26 in the test process, the layout can be obtained when the target specifications can be obtained within the variation range of the wafer process. By fixing the part to be trimmed by the change in the mass production, the trimming process can be omitted, the number of trial productions can be reduced, the development period can be shortened, and the cost can be reduced.
[0038]
As described above, the semiconductor device according to the present embodiment changes the data combination of the data signals TD0 and TD1 in the test mode, thereby causing the delay time adjustment unit 50 to delay the input signal according to the combination. The delay time is adjusted to the optimum delay time, and the fuses 23 to 26 of the delay time setting unit 20 are disconnected, and the input signal is always delayed by the optimum delay time regardless of the data signals TD0 and TD1 and output. I tried to do it. From this, it is possible to eliminate the clock delay in the semiconductor device due to variations in the manufacturing stage of the wafer process and the variations in delay of each signal, achieve the target value of the operating frequency, and improve the operating frequency, The defect yield due to the operating frequency can be improved, the development design period can be shortened, and the cost can be reduced.
[0039]
In the above embodiment, the fuses are cut to set the delay time. However, instead of the fuses 23 to 26, predetermined on-chip resistors are used, and the on-chip resistors are trimmed. Thus, the data combination of the data signals TDa and TDb may be changed. Needless to say, in FIG. 1, four types of delay times and two types of delay times in FIG. 3 have been described as examples, but this is an example, and the present invention is not limited to this. Instead, it may be adjusted to a plurality of types of delay times in the same manner as in FIG.
[0040]
【The invention's effect】
As is apparent from the above description, according to the semiconductor device of the present invention, in the test mode in which a predetermined signal is input from the outside, the combination of data input from the outside is changed, and the input signal is By adjusting the delay time according to the combination and outputting the result, the delay time is adjusted to an optimum value, and a desired delay time can be set using the data generation unit. From this, it is possible to eliminate the clock delay in the semiconductor device due to variations in the manufacturing stage of the wafer process and the variations in delay of each signal, achieve the target value of the operating frequency, and improve the operating frequency, The yield of high-speed operating frequency chips can be improved. Since a chip having a high operating frequency is expensive, the added value of the wafer can be increased as a result. In addition, since the signal delay time can be adjusted by a test performed after manufacturing, even for a circuit having a high-speed interface in which delicate timing between signals is specified, there is an LSI chip that originally does not satisfy the interface standard. It can be used as a good product. Furthermore, at the prototype stage, it is possible to find the optimum design value to absorb the error between the simulation at the design stage and the actual prototype device, and the development period can be shortened by reducing the number of prototypes, thereby reducing costs. Can be planned.
[0041]
Specifically, the optimum delay time obtained in the test mode is set in the data generation unit so that the input signal is always delayed with the optimum delay time regardless of the data input from the outside. did. From this, the optimum delay time obtained in the test mode can be easily set after chip manufacture.
[0042]
In addition, by setting the optimum signal delay time obtained by the test mode in which a predetermined signal is input from the outside by the combination of fuses to be cut, the optimum signal delay time can be set with a simple and inexpensive configuration. Can do.
[0043]
Further, the optimum signal delay time obtained by the test mode in which a predetermined signal is input from the outside may be set by a combination of resistors set by trimming. An optimum signal delay time can be set with a simple and inexpensive configuration.
[0044]
Furthermore, a switching circuit for connecting and disconnecting the series circuit between predetermined potentials in accordance with a predetermined signal from the outside may be provided. In this way, in the case of having a standby operation mode in which the power consumption is reduced in a standby state, the connection between the predetermined potentials with respect to the series circuit is cut off when measuring the current consumption during standby. In addition, the current consumption during standby can be accurately measured, and the standby test can be performed normally.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating an example of a semiconductor device in an embodiment of the present invention.
FIG. 2 is a circuit diagram showing another example of a semiconductor device in an embodiment of the present invention.
FIG. 3 is a circuit diagram showing another example of the semiconductor device in the embodiment of the present invention.
FIG. 4 is a schematic block diagram showing an example of a conventional semiconductor device.
[Explanation of symbols]
1 Semiconductor device
10 Multiplexer
20 Delay time setting section
23-26 fuse
30 decoder
50 Delay time adjuster
D1 to D4 delay time adjustment circuit

Claims (2)

In a semiconductor device having a delay time adjustment function for adjusting and setting the delay time of an input signal,
Consisting of a delay circuit that delays a signal with a plurality of different delay times, and a signal delay unit that delays an input signal with a selected delay time;
A delay time selection unit that selects a delay time of the signal delay unit according to input data;
A data generation unit that generates data for instructing a delay time to be selected with respect to the delay time selection unit;
A data switching unit that switches data input from the outside and data generated by the data generation unit according to a predetermined signal from the outside and outputs the data to the delay time selection unit;
Equipped with a,
The data generator is
At least one series circuit in which a plurality of fuses are connected in series, connected between predetermined potentials indicating binary data;
A switching circuit for controlling connection between the series circuit and a predetermined potential in response to a predetermined signal from the outside;
The delay time of the signal delay unit selected using the data input from the outside is generated by the combination of the fuses to be cut and selected by the delay time selection unit wherein a perform data generation. In a semiconductor device having a delay time adjustment function for adjusting and setting the delay time of an input signal,
Consisting of a delay circuit that delays a signal with a plurality of different delay times, and a signal delay unit that delays an input signal with a selected delay time;
A delay time selection unit that selects a delay time of the signal delay unit according to input data;
A data generation unit that generates data for instructing a delay time to be selected with respect to the delay time selection unit;
A data switching unit that switches data input from the outside and data generated by the data generation unit according to a predetermined signal from the outside and outputs the data to the delay time selection unit;
With
The data generator is
At least one series circuit connected in series with a plurality of trimmable resistors connected between predetermined potentials indicative of binary data;
A switching circuit for controlling connection between the series circuit and a predetermined potential in response to a predetermined signal from the outside;
The delay time of the signal delay unit selected using data input from the outside is generated by the combination of the resistors set by trimming and selected by the delay time selection unit. semi conductor arrangement and performing data generated so that.

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