TW201608354A - Clock generation circuit that tracks critical path across process, voltage and temperature variation - Google Patents

Abstract

Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.

Description

Clock generation circuit for tracking critical paths across program, voltage and temperature variations

Particular embodiments of the present invention relate to the field of semiconductor design, fabrication, testing, and operation, and more particularly to embodiments of the present invention are systems and methods for tracking a critical path of a program, voltage, and temperature variation with respect to a clock generation circuit.

Semiconductor processes are generally considered to be highly self-consistent, that is, the process is very sophisticated in producing "accurate" replicas of integrated circuit design. Particularly suitable for semiconductor products operating in the digital domain, such as microprocessors and / or graphics processing units (GPUs). Functionally, the semiconductor industry has successfully produced very versatile similar replicas.

Unfortunately, many of the analogy characteristics of integrated circuits are very variable, resulting in circuit-to-circuit and/or wafer-to-wafer analog function/performance variations, for example, even with the same process, the same design of the wafer-to-wafer The threshold voltage, capacity, gate delay, current consumption, minimum operating voltage, and maximum operating frequency may also vary by 30% or more. In addition, once manufactured, this characteristic will vary drastically depending on the operating voltage and temperature. For example, compared to operating at lower voltages and higher temperatures, integrated circuits are generally available at higher voltages and lower temperatures. Have a higher operating frequency.

The clock signal is an oscillating electronic signal, and many composite integrated circuits, such as micro-location The processor and/or graphics processing unit utilizes a synchronization signal that is generally known or referred to as a clock or clock signal. Such clock signals can be used to control and/or synchronize many aspects of integrated circuit operation, such as, in particular, synchronous digital circuits. The frequency of this signal is related to the performance of the integrated circuit, and is usually used in advertising, and as a means of comparison between competing products, such as "the operating frequency of this chip is 2.4 GHz".

In the conventional field, manufacturers often specify the highest clock frequency after the qualification test of the integrated circuit due to the manufacturing error of the integrated circuit operation and the variability of the operation. The highest clock frequency is determined to determine that the operation of the integrated circuit can reliably pass through a particular operating environment, such as a range of operating voltages and operating temperatures, some of which are known or referred to as an operating window or operating envelope. Once this highest clock frequency has been determined, for example, a high or stable clock signal, typically derived from the highest or lower frequency of a crystal source, is provided to the integrated circuit for operation.

Unfortunately, because it has been decided that the highest operating frequency satisfies all processing variations and operating conditions (including, for example, the worst case combination of these processes and operational changes), the highest operating frequency available under conventional techniques is generally less than in actual operating conditions. The frequency at which any known integrated circuit can be implemented. This suboptimal operation results in an undesirable reduction in the performance of the integrated circuit and reduces the competitive position of the integrated circuit.

Accordingly, the present invention is directed to a system and method for a clock generation circuit to track a critical path across program, voltage, and temperature variations. Systems and methods are also provided for the clock generation circuit to improve system performance. Further proposed systems and methods for clock generation that reduce or eliminate the need for crystal frequency references, their associated costs, and space requirements. Further, systems and methods are provided that are compatible and complementary to systems and methods for designing, manufacturing, testing, and operating of existing electronic circuits. Specific embodiments of the present invention provide these advantages.

According to a first embodiment of the present invention, an integrated circuit device is included An oscillator electronics on the integrated circuit device to generate an oscillating signal and a receiving electronic circuit to use the oscillating signal as a clock. The oscillating signal tracks a frequency voltage characteristic of the receiving electronic circuit across program, voltage and temperature variations.

In accordance with another embodiment of the present invention, an electronic circuit includes a first delay chain having a first type of delay element and a second delay chain having a second type of delay element. The second type of delay element performs a different digital function than the first type of delay element. The electronic circuit also includes combining logic to combine the output of the first delay chain with the output of the second delay chain to produce an oscillating signal output of the electronic circuit.

In accordance with a method embodiment of the present invention, a method includes first generating a first delayed signal based on a first type of delay element and generating a second delayed signal based on a second type of delay element different from the first type of delay element. The method also includes combining the first and second delay signals to form a clock signal oscillating at a frequency corresponding to the longer of the first and second delay signals.

100‧‧‧Demonstration frequency versus voltage characteristics

110-150‧‧‧ Curve

200‧‧‧ demonstration clock generation circuit

210‧‧‧Line delay model delay chain

220‧‧‧Simple gate delay model delay chain

230‧‧‧Composite gate delay model delay chain

240‧‧‧Composite structure delay model delay chain

250‧‧‧ Consistent detector components

260‧‧‧ Consistent detector components

270‧‧‧ Consistent detector components

280‧‧‧ clock signal

300‧‧‧Demonstration line delay model delay chain

310‧‧‧ coarse adjustment delay phase

311-317‧‧‧ lines

320‧‧‧ reverser

321‧‧‧ reverser

322‧‧‧ reverser

350‧‧‧ fine-tuning delay phase

360‧‧‧Delayed phase

361‧‧‧ stage

370‧‧‧ reverser

380‧‧‧Three-state inverter

391‧‧‧Three-state inverter

392‧‧‧Three-state inverter

393‧‧‧Three-state inverter

400‧‧‧Demonstration of a simple gate delay model delay chain

410‧‧‧ coarse delay adjustment phase

450‧‧‧fine delay adjustment phase

500‧‧‧ Demonstration composite brake delay model delay chain

510‧‧‧ coarse delay adjustment phase

550‧‧‧fine delay adjustment phase

600‧‧‧ Demonstration composite structure delay model delay chain

610‧‧‧ reverser

630‧‧‧Static Random Access Memory Unit

680‧‧‧Precharge circuit

690‧‧‧Rough delay chain

The drawings are incorporated in and constitute a part of the specification, The drawings are not drawn to scale unless otherwise noted.

1 illustrates exemplary frequency versus voltage characteristics of an exemplary integrated circuit in accordance with an embodiment of the present invention.

2 illustrates an exemplary clock generation circuit that tracks a critical path across program, voltage, and temperature variations in accordance with an embodiment of the present invention.

3A and 3B illustrate an exemplary line delay model delay chain in accordance with one embodiment of the present invention.

4 illustrates an exemplary simple gate delay model delay chain in accordance with one embodiment of the present invention.

Figure 5 illustrates a composite gate delay model delay chain in accordance with one embodiment of the present invention.

Figure 6 illustrates a composite structure delay model delay chain in accordance with one embodiment of the present invention.

Reference will now be made in detail to the preferred embodiments of the claims While the invention will be described in conjunction with the specific embodiments, it should be understood that Rather, the invention is to cover the modifications, modifications, and equivalent arrangements of the inventions. Still, in the following detailed description of the invention, numerous specific details are set forth However, those skilled in the art will appreciate that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail so as not to obscure the scope of the specific embodiments.

<Representation and terminology>

The term "ring oscillator" is often used to represent or describe an oscillator that includes a plurality of digital gates. The most well-known configuration is an odd number of inverters. The output of the last gate is fed back into the input of the first gate, but still There may be many configurations. The output frequency of a ring oscillator is a function of the number of stages and the delay of each stage, such as the gate delay. It should be understood that not every oscillator circuit having a "ring" topology is a ring oscillator. For example, U.

<System and method for tracking clock generation circuits across critical paths of program, voltage and temperature variations>

In addition to the general effects of process variations and operating conditions, depending on the design, the highest clock frequency of a particular integrated circuit is limited by the time of its most critical (eg, slowest) path. This circuit is generally known or referred to as a "critical path."

In accordance with a particular embodiment of the present invention, it is desirable to employ a clock generation circuit that tracks the critical path of a program circuit across voltage, temperature, and temperature variations. Compared with the conventional technology, this clock generation circuit has higher efficiency when the situation permits. Moreover, embodiments in accordance with the present invention may reduce or eliminate the need for such a device for crystal oscillation sources, reducing cost and volume or space requirements.

It should be appreciated that this innovative approach can produce a variable clock signal, such as a clock signal that changes frequency based on manufacturing variations and/or operating conditions. This variable clock signal can be compared to conventional techniques (i.e., with very stable, for example, crystal controlled clock signals that do not change with manufacturing variations and/or operating conditions).

In general, the term "critical path" circuit is used to represent or describe an electronic circuit that limits the maximum clock frequency of an integrated circuit device, such as a "wafer." By way of example, a critical path circuit is generally the circuit that takes the longest time to complete an operation in all circuits. Critical path circuits are typically composite circuits that contain a variety of gates and other sources of delay, such as long wires. In general, the frequency versus voltage characteristics of the critical path circuit are non-linear.

1 illustrates an exemplary frequency versus voltage characteristic 100 of an exemplary integrated circuit in accordance with an embodiment of the present invention. For example, the curve on characteristic 100 represents the highest operating frequency for a known operating voltage of a circuit on the IC. Curve 110 illustrates exemplary frequency-voltage characteristics of an integrated circuit, such as a combined frequency-voltage characteristic of all components of an integrated circuit. For example, at high frequencies, the voltage increase will produce little or no increase in the maximum operating frequency, and similarly at low voltages, the curve will be close to the lowest voltage at which the lower circuit will not operate.

According to a particular embodiment of the invention, the critical path delay variation is modeled by more than one delay chains. Each delay chain establishes a model of the component behavior of the critical path circuit. In an exemplary embodiment of the invention, the change in critical path delay is modeled by four delay chains. Embodiments in accordance with the present invention are also applicable to delay chains (or oscillators) according to different models and different number of models.

A first delay chain model will change the delay of a critical path due to line delay. late. Line-type delays typically include line impedance and capacitance from the interconnect. Line delay is almost agnostic for program and voltage changes; however, it is sensitive to parasitic effects, process corners, and temperature. Paths dominated by line delays typically limit the frequency at higher operating voltages, higher temperatures, and fast program angles. Curve 120 illustrates an exemplary frequency versus voltage characteristic of a line delay model delay chain, and curve 120 should be understood to be relatively horizontal. In general, the frequency-voltage characteristics of most circuits are not linear. However, the frequency-voltage characteristics of the line delay model delay chain are more linear than the frequency-voltage characteristics of the critical path circuit. Thus, curve 120 is illustrated as being substantially linear for purposes of clarity of illustration.

The second delay chain model can change the delay of the critical path due to a simple logic gate, such as a gate with a small stack height, such as a buffer and an inverter. The delay of a simple logic gate is sensitive to program and operating condition changes, but less sensitive than composite logic gates. A path dominated by a simple gate delay typically limits the frequency in the case of a medium to high operating voltage range. Curve 130 illustrates an exemplary frequency versus voltage characteristic of a simple gate delay model delay chain. In general, the frequency-voltage characteristics of most circuits are non-linear. However, the frequency-voltage characteristics of the simple logic gate model delay chain are more linear than the frequency-voltage characteristics of the critical path circuit. Thus, curve 130 is illustrated as being substantially linear for purposes of clarity of illustration.

The third delay chain model can change the delay of the critical path due to the composite logic gate, such as a gate with three or more transistor stacks, such as NAND/NOR/XOR gates, transfer gates, pass gates, and the like. The delay of the composite logic gate is very sensitive to changes in program and operating conditions. The path dominated by the composite gate delay typically limits the frequency in the low to medium operating voltage range. Curve 140 illustrates an exemplary frequency versus voltage characteristic of a composite gate delay model delay chain. In general, the frequency-voltage characteristics of most circuits are non-linear. However, the frequency-voltage characteristics of the composite logic gate delay chain are more linear than the frequency-voltage characteristics of the critical path circuit. Thus, curve 140 is illustrated as being substantially linear for purposes of clarity of illustration.

The fourth delay chain model may change the delay of the critical path due to the composite structure, such as a memory structure, a feedback type structure, a time varying structure, a non-combined structure, and the like. Composite structure The delay is extremely sensitive to changes in program and operating conditions. The path dominated by the composite structure delay typically limits the frequency in the case of low operating voltage ranges. Curve 150 illustrates an exemplary frequency versus voltage characteristic of a composite structure delay model delay chain. In general, the frequency-voltage characteristics of most circuits are non-linear. However, the frequency-voltage characteristics of the composite structure model delay chain are more linear than the frequency-voltage characteristics of the critical path circuit. Thus, for purposes of clarity of illustration, curve 150 is illustrated as being substantially linear.

2 illustrates an exemplary clock generation circuit 200 that tracks one of critical paths across program, voltage, and temperature variations in accordance with an embodiment of the present invention. The clock generation circuit 200 includes a plurality of (e.g., four) delay chain circuits that establish a model of a plurality of delay characteristics of the critical path circuit. For example, the line delay model delay chain 210 establishes a model of delay and related characteristics due to lines such as resistors and capacitors. The frequency-voltage characteristics of the line delay model delay chain 210 generally correspond to the curve 120 of FIG. The simple gate delay model delay chain 220 establishes a model of delay due to simple gate characteristics. The frequency-voltage characteristics of the simple gate delay model delay chain 220 generally correspond to the curve 130 of FIG. The frequency-voltage characteristics of the composite gate delay model delay chain 230 generally correspond to the curve 140 of FIG. The compound gate delay model delay chain 230 establishes a model due to the delay of the composite gate characteristics. The composite structure delay model delay chain 240 establishes a model of the delay due to the characteristics of the composite structure. The frequency-voltage characteristics of the composite structure delay model delay chain 240 generally correspond to the curve 150 of FIG. For the purposes of clarity, the control inputs, if any, are not instantiated to the delay chains.

The outputs from delay chains 210, 220, 230, and 240 are combined by a coincidence detector element 250, 260, and 270, as illustrated. In the embodiment of FIG. 2, coincident detector elements 250, 260, and 270 include a "Mueller-C" component. It will be appreciated that embodiments of the invention are also applicable to other types of coincident detectors. The Mueller-C component is a well-known special-type NAND gate characterized by propagating a state change only when its two inputs are identical, for example, when only one of the inputs of a true NAND (or AND) gate is converted from true to false. , its ability to convert from true to false. In contrast, the coincident detector elements 250, 260, and 270 do not convert (eg, both inputs change from true to false) until all inputs are consistent.

It should be appreciated that the coincident detector elements 250, 260, and 270 select the slowest of the delay chains 210, 220, 230, and 240, such as the lowest frequency output. In this innovative approach, clock signal 280 is an oscillating signal that reflects the slowest modeled frequency-voltage characteristic of a critical path circuit and can represent the frequency that the critical path opportunity satisfies. Thus, in accordance with an embodiment of the present invention, a clock generation circuit that tracks a critical path across program, voltage, and temperature variations is provided.

According to a particular embodiment of the invention, the individual delay chains 210, 220, 230 and 240 do not contain internal feedback. The output of the relatively consistent detector 270 (i.e., clock signal 280) is fed back to the inputs of each of the delay chains 210, 220, 230, and 240. This configuration has the advantage of avoiding excessive power consumption if individual delay chains are set up as ring oscillators and allowing the ring oscillators to operate at their natural frequency. It should be appreciated that a particular embodiment in accordance with the present invention is suitable for use in a ringless oscillator operating without load, for example, including internal feedback, and does not require feedback in conjunction with the clock signal 280.

3A and 3B illustrate an exemplary line delay model delay chain 300 in accordance with one embodiment of the present invention. FIG. 3A illustrates a coarse adjustment or adjustment delay phase 310 of the line delay model delay chain 300. The coarse adjustment delay phase 310 includes a plurality of long lines, such as lines 311, 312, 313, 314, 315, 316, and 317. Lines 311, 312, 313, 314, 315, 316, and 317 are generally not of the same length, as shown. Exemplary lengths are 100 nm, 80 nm, 100 nm, 130 nm, 20 nm, 40 nm, and 330 nm, respectively. In this manner, a plurality of line lengths can be combined to establish a coarse line delay.

To reduce the delay through the line, many small parallel tristate (optional) drivers are connected at many points in the line segment. These parallel small drives, when enabled, help signal transmission through the line, thus reducing latency at startup. For example, turning on one of these tristatable drivers shortens the delay through one phase, but is less than the delay that is shortened by removing the line. Depending on where the tri-state drivers help the conversion and how many are enabled, different amounts can be used to adjust the delay through the line. Under the point of careful selection of parallel drive connections, Achieve a wide range of adjustments.

For example, inverters 320, 321, and 322 represent three parallel (optional) three parallel instances of the inverter/driver, each driving the output of line segments 311, 312, and 313, respectively. By driving this output, the delay contribution of each individual line length is shortened or eliminated. For example, when the tri-state (optional) inverter 320 is enabled, it tends to bypass the line 311. Similarly, inverters 330 and 321 represent two parallel instances of a tristate inverter/driver, each driving the output of line segments 315 and 316, respectively.

FIG. 3B illustrates a trimming delay phase 350 of the line delay model delay chain 300 in accordance with an embodiment of the present invention. The trim delay phase 350 includes a plurality of delay phases, such as a delay phase 360. Each delay phase includes a master driver, such as inverter 370, coupled in parallel with a tristate driver, such as tristate inverter 380. Each delay phase can reduce its delay by a different amount. For example, the delay phase 360 can have two delay values: a first delay value when the inverter is alone, and when the tristate driver is enabled, for example, A second delay value for selecting ("sel") line. Enabling this tri-state driver provides additional drive strength to each trim stage. It will be appreciated that increasing the drive strength, such as the drive strength of the inverter 370 plus the drive strength of the tristate inverter 380, shortens the delay of the delay phase. The reduced delay ratio due to enabling the tri-state driver depends on the relative drive strength of the master drive to the tri-state driver. For a known tri-state driver size, as the size of the primary drive increases, the percentage of delay changes decreases.

In general, the delays for each delay phase of the fine-tuning delay phase 350 are not equal, but this does not have to be equal. In one embodiment, one weight is a binary weighted relationship between delay contributions, for example: one delay phase can produce 50% of the highest delay of the trim delay phase 350, and a second phase can produce the highest delay of the trim delay phase 350 25%, a third stage can produce 12.5% of the highest delay of the fine-tuning delay stage 350, and so on. This configuration enables high-grained delay adjustments with reduced phase and number of devices. Embodiments of the present invention also consider linearity, exponential, and combined correlation between delay phase weightings. In addition, the three-state drive from each stage The adjustment ratio delays of the devices may not be equal.

In general, the maximum delay of the trim delay phase 350 can be approximately equal to the minimum delay increment of the coarse delay phase 310 of the line delay model delay chain 300, but does not necessarily need to be equal. This configuration will increase the achievable delay granularity (or frequency) available to the line delay model delay chain 300.

The outputs of all even phases of the trim delay phase 350 are coupled to a multiplexer that includes tristate inverters/drivers, such as tristate inverters 391, 392, and 393. This multiplexing can be selected between different legs of the multiplexer to extend or shorten the delay of each step in the delay steps of the two inverters, for example: enabling the tristate inverter 392 tends to use a tristate The delay of inverter 392 replaces the two delay phases, such as the delays of phases 361 and 360, thereby reducing the overall delay.

In accordance with a particular embodiment of the present invention, the line delay model delay chain 300 is independent of (e.g., does not include) a multiplexer. One way to change the delay of the delay chain in this model is to use a multiplexer to select different line paths of different lengths. Unfortunately, such multiplexers tend to dominate the delay compared to the delay caused by the length of the line. In addition, the frequency-voltage characteristics of a multiplexer circuit are generally different from the frequency-voltage characteristics of the line. Therefore, using a multiplexer to select different line paths of different lengths is not suitable for establishing a line delay model.

4 illustrates an exemplary simple gate delay model delay chain 400 in accordance with one embodiment of the present invention. The simple gate delay model delay chain 400 includes a coarse delay adjustment phase 410 and a fine delay adjustment phase 450. The coarse delay adjustment phase 410 includes a long chain of inverters. All even-phase outputs are coupled to a combiner circuit that includes a tri-state inverter/driver. This tri-state combination can be selected between different feet of the circuit to extend or shorten the delay of each step in the large (rough) step of the two inverter delays.

The fine delay adjustment phase 450 includes a plurality of delay stages, which may be comparable to those described for the fine delay adjustment stage 350 of FIG. 3B, and a fine adjustment of the overall delay of the similar simple gate delay model delay chain 400 can be performed.

FIG. 5 illustrates a composite gate delay model delay chain 500 in accordance with an embodiment of the present invention. The simple gate delay model delay chain 500 includes a coarse delay adjustment phase 510 and a fine delay adjustment phase 550. The coarse delay adjustment phase 510 includes a long chain of XNOR (negative mutually exclusive OR) gates in series with the inverter chain.

Each XNOR gate and inverter of the coarse delay adjustment phase 510 is further coupled to a multiplexer including a tri-state inverter/driver that can be selected between different legs of the multiplexer. Extend or shorten the delay in the large (coarse) step.

In accordance with a particular embodiment of the present invention, since the frequency-voltage characteristic of the XNOR gate has been characterized as being most sensitive to voltages from available standard gates within a particular semiconductor technology design library, the gate is selected for compound gate delay Model delay chain 500. For example, a typical complementary metal oxide semiconductor (CMOS) XNOR gate comprises a stack of two four FETs. As previously presented, this stacked FET gate is very sensitive to changes in program and operating conditions due to the bulk effect acting on the "internal" FET. It should be appreciated that other design libraries for other program nodes may have different gates that meet this standard. Embodiments in accordance with the present invention are applicable to the use of other composite brakes.

In contrast, inverters are typically the simplest gate design that can be achieved and are typically the type of gate that is least sensitive to changes in program and operating conditions. In accordance with a particular embodiment of the invention, the series combination of the XNOR gate and the inverter gate adjusts the frequency-voltage characteristic to achieve the desired overall delay voltage sensitivity. For example, the voltage sensitivity of the overall delay required is determined by the delay ratio of the selected XNOR gate to the delay of the selected inverter. According to a particular embodiment of the invention, the overall delay is adjustable while fixing the delay ratio to be substantially constant.

The fine delay adjustment phase 550 includes a plurality of delay phases that can be compared to the delay phases described for the fine delay adjustment phase 350 of FIG. 3B to perform fine tuning of the overall delay of the similar composite gate delay model delay chain 500.

FIG. 6 illustrates a composite structure delay model delay chain 600 in accordance with one embodiment of the present invention. Composite structure delay model delay chain 600 is based on a static access memory (SRAM, static random access memory) unit 630. In general, SRAM cell transistors are different from typical transistors used in most digital logic, and thus can undergo manufacturing variations that are different from other transistors on the same die. In addition, SRAM cell transistors operate at higher threshold voltages than many typical transistors used in most digital logic, for example to reduce static leakage current. Therefore, such SRAM cell transistors are typically slower than many of the common transistors of the integrated circuit. Further, in the general integrated circuit design procedure, a "fast" transistor is used in the critical path circuit to replace the "slow" transistor in order to improve the timing of the critical path circuit. However, this option is usually not available for SRAM cells.

The delay of the composite structure is extremely sensitive to changes in program and operating conditions. A path dominated by a composite structure delay typically limits the operating frequency over a low operating voltage range. The SRAM cell 630 is selected from a cell library and is most sensitive to changes in program and operating environment conditions between circuit blocks. The composite structure delay model delay chain 600 includes a coarse delay chain 690, similar to the coarse delay adjustment phase 410 of the simple gate delay model delay chain 400 illustrated in FIG. However, the composite structure delay model delay chain 600 differs from other delay chains in that the rising and falling transitions follow different paths. One transition triggers a read operation on SRAM array 630 and the other transition triggers a pre-charge operation within pre-charge circuit 680. Tracking different paths through the delay chain results in different delays for different conversions. To achieve the equilibrium phase of the clock, the conversion through the read phase is bypassed by the inverter 610 using a parallel path. This bypass path allows other delay chains, such as delay chains 300, 400, and 500, to determine the width of a clock phase. Additionally, the read operation self-triggers the pre-charge operation of SRAM 630. Self-triggering determines that the total clock period is determined by the total read latency plus the pre-charge delay of SRAM 630.

It should be understood that the delay model described in the embodiments contains a large amount of adjustability. After characterization of the frequency-voltage characteristics of a circuit critical path, such as curve 110 of Figure 1, the frequency of each delay model delay chain can be adjusted to be approximately a portion of the frequency-voltage characteristics of such a circuit critical path.

In general, the type of gate that contains the delay chain for each individual delay model determines its frequency. Rate "slope" of the voltage characteristic. It should be understood that this characteristic is generally non-linear. However, for the sake of illustration, considering this characteristic as linear is a convenient and simplified way. Many adjustment settings, such as the value of the "sel" signal selected, typically determine where the characteristic along the voltage axis (abscissa) is steep. It should be understood that for the composite gate model delay chain illustrated in FIG. 5, the delay ratio caused by the composite gates can be adjusted to the delay ratio caused by the inverters, and this ratio also affects the "slope" of the characteristic.

Many adjustment settings, such as the selection "sel" signal for each delay model delay chain, can be permanently set, such as through a fuse, or in some embodiments, during operation.

It will be appreciated that an embodiment of the present invention produces an oscillating signal suitable for use as a clock signal within a composite digital logic circuit. The clock signal is generated on the same integrated circuit device as the digital logic circuit, such as a "wafer", and can be generated by the same voltage rail as the receiving circuit. Therefore, the clock signal is highly correlated with the manufacturing variations of the integrated circuit device. For example, if the process produces a "slow" wafer, the oscillator will run relatively "slowly". In addition, because the oscillating signal is generated by two or more oscillators, or by modeling delay circuits of different delay sources within the critical path circuit, the oscillating signal can track changes in operating frequency across operating voltage and temperature changes. In this innovative approach, a clock generation circuit that tracks critical paths across program, voltage, and temperature variations is provided in accordance with an embodiment of the present invention.

Embodiments of the present invention provide systems and methods for clock generation circuits to track critical paths across program, voltage, and temperature variations. Moreover, systems and methods for clock generation circuitry that can improve system performance are provided in accordance with embodiments of the present invention. Further, systems and methods for clock generation that reduce or eliminate the need for crystal frequency references, their associated costs, and space requirements are provided in accordance with embodiments of the present invention. Still further, systems and methods are provided in accordance with embodiments of the present invention that are compatible and complementary to systems and methods for designing, manufacturing, testing, and operating of existing electronic circuits.

Various specific embodiments of the invention have been described herein. Although specific specific EXAMPLES The present invention should be understood that the invention should not be construed as being limited to

200‧‧‧ demonstration clock generation circuit

210‧‧‧Line delay model delay chain

220‧‧‧Simple gate delay model delay chain

230‧‧‧Composite gate delay model delay chain

240‧‧‧Composite structure delay model delay chain

250‧‧‧ Consistent detector components

260‧‧‧ Consistent detector components

270‧‧‧ Consistent detector components

280‧‧‧ clock signal

Claims (20)

An integrated circuit device comprising: an oscillator electronic circuit located on the integrated circuit device to generate an oscillating signal; a receiving electronic circuit for using the oscillating signal as a clock, and wherein the oscillating signal is tracked The receiving electronic circuit has a frequency voltage characteristic across program, voltage and temperature variations. The integrated circuit device of claim 1, wherein the oscillator electronic circuit comprises at least two delay chains, the at least two delay chains generating an output signal to combine to generate the oscillating signal. The integrated circuit device of claim 2, wherein the output signals are combined by an electronic circuit including a coincident detector. The integrated circuit device of claim 3, wherein the coincident detector comprises a Mueller-C gate. The integrated circuit device of claim 2, wherein each of the at least two delay chains models a different delay source of the receiving electronic circuit. The integrated circuit device of claim 5, wherein the at least two delay chains are modeled on at least the delay characteristic to line delay, simple gate delay, composite gate delay, and composite structure delay setting. Delay. The integrated circuit device of claim 5, wherein each of the at least two delay chains One contains delay elements that are not found elsewhere. The integrated circuit device of claim 1, wherein the oscillator electronic circuit generates the oscillating signal regardless of any off-chip oscillating reference signal. An electronic circuit comprising: a first delay chain comprising a first type of delay element; a second delay chain comprising a second delay element, wherein the second delay element is executed with the first delay element Different digital functions; and combinational logic to combine the output of the first delay chain with the output of the second delay chain to produce an oscillating signal output of the electronic circuit. The electronic circuit of claim 9, wherein the oscillating signal output is fed back to an input of the first and second delay chains. An electronic circuit as claimed in claim 9 further comprising a third delay chain comprising a third delay element, wherein the third delay element performs a function different from the first or second delay element And additionally incorporated into the output of the second oscillating signal. An electronic circuit as in claim 9 wherein the combination logic comprises a Mueller-C element. The electronic circuit of claim 9, wherein the first delay chain comprises a line delay model delay chain, the line delay model delay chain comprises: a line type delay element; and a selectable driver comprising an output link to the Line delay model delay chain And an output coupled to the output of the line type delay element, and wherein the selectable driver is enabled to shorten the one of the output from the line delay model delay chain to the output of the line type delay element. The electronic circuit of claim 9, wherein the first delay chain comprises a trimming section, the trimming section comprising: a plurality of delay stages, each of the delay stages comprising: a first driving component a selectable drive element parallel to the first drive element, and wherein when enabled, the selectable drive element shortens a delay of the delay phase, the shortening of the delay being less than corresponding to removing the first drive element Shortened delay. A method comprising: first generating a first delayed signal according to a first type of delay element; generating a second delayed signal according to a second delay element different from the first type of delay element; and The two delayed signals combine to form a clock signal oscillated at a frequency corresponding to the longer of the first and second delayed signals. The method of claim 15, wherein the first and second delayed signals comprise different frequency-voltage characteristics. The method of claim 15, further comprising the step of: feeding the clock signal as an input to the step of generating the first delayed signal and the step of generating the second delayed signal. The method of claim 15, further comprising: adjusting a delay of the first delay signal by using a smaller one of the plurality of drive elements to enable selection of the drive element, wherein the delay is shorter than the corresponding This larger drive element removes the shortened delay. The method of claim 15, wherein the step of generating the second delayed signal comprises combining a delay caused by a gate comprising more than three transistors in a stack with a delay caused by a gate comprising less than three transistors. The method of claim 15, wherein the step of generating the first delayed signal and the step of generating the second delayed signal are independent of a frequency reference that is substantially stable with respect to voltage stability.