JP2001250920A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device having a signal delay adjustment function that can improve an operating frequency and poor yields caused by the operating frequency, at the same time, can shorten a development design period, and can reduce costs. SOLUTION: The combination of the data of data signals TD0 and TD1 is changed in a test mode, and an input signal is delayed by the amount of time corresponding to the combination by a delay time adjustment part 50 for outputting, thus adjusting appropriate delay time, at the same time, cutting fuses 23 to 26 of a delay time setting part 20, and outputting a signal CLK1 where an input signal CLK is delayed constantly by appropriate delay time regardless of the data signals TD0 and TD1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a high-speed CPU, a high-speed DSP, a high-speed ASIC or a high-speed memory, and a semiconductor device having a high-speed interface circuit, and more particularly to a semiconductor device having a clock or other signal delay time adjusting function. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art In recent years, several hundred MHz have been used in high-speed processors.
Clock frequency is important for high speed operation. In designing high-speed semiconductor devices,
With the aim of high-speed operation, a technique for reducing a clock phase shift (hereinafter, referred to as clock skew) of a semiconductor device using a circuit design technique in a design process, a layout technique with a CAD tool, or the like is used. .

[0003] As the above circuit design technique, a technique of configuring a circuit with the same clock signal using a superbuffer or the like, or a technique of making a circuit to which a clock is input equivalent in capacity or changing the clock buffer size while changing the clock buffer size is used. There is a technique for designing such that skew is reduced. As the layout technique, there is a technique in which clocks are hierarchically arranged on a tree, and a clock circuit is automatically created and automatically laid out on an automatic placement and routing tool so that delay times are equivalent.

[0004] For example, in Japanese Patent Application Laid-Open No. 9-282444, in a semiconductor circuit having a plurality of clock systems,
In order to reduce clock skew, a circuit with small skew is provided by using circuits such as a clock oscillator, a frequency divider, and a phase comparator. In addition, Japanese Patent Application Laid-Open
Japanese Patent No. 124553 discloses a clock tree generation method capable of reducing the influence of clock skew generated due to individual variations of clock buffers, the number of registers connected to the output of the final stage of each clock buffer, and the like. Discloses a clock tree generation method for classifying registers constituting a logic circuit and forming a clock tree for supplying a clock pulse to each of the registers based on the classified registers and the period of the clock pulse. The result of generating the clock tree is reflected on the logic circuit.

[0005]

In the prior art as described above, there is provided a semiconductor device having a circuit in which the clock skew is reduced at the design stage, and the semiconductor device after the design is manufactured by a wafer process. However, variations in each step, which cannot be avoided in the wafer process, cause variations in electrical characteristics. As a result, the clock skew value is slightly different for each LSI chip on the wafer, and a chip that does not reach the target operating frequency can be obtained by looking at each chip due to the variation. Due to such variations, the LS manufactured under the same conditions
Even I-chips were sorted by testing and sold with different added values as chips with different operation speed versions.

In order to achieve high-speed operation of a chip, it is not always necessary that the clock skew be small. In other words, a small skew may increase the operating frequency of the chip. For example, in the circuit shown in FIG. 4, at the rising edge of the clock CK1, the flip-flop 1
01 is input to the combinational circuit 104, the output signal of the combinational circuit 104 is input to the flip-flop 102 at the rising edge of the clock CK2, and the output signal of the flip-flop 102 is input to the combinational circuit 105. Further, the output signal of the combination circuit 105 is input to the flip-flop 103 at the rising edge of the clock CK3.

In the conventional clock cycle-based synchronous design, the clocks CK1 to CK3 are designed to have as little skew as possible. Determine the time (operating frequency). For example, when the combinational circuit 104 is critical and the operation time of the combinational circuit 105 has a margin,
By delaying the phase of the clock CK2 relative to the phases of the clocks CK1 and CK3, the operation time given to the combinational circuit 104 increases by the delay time, so that the overall operating frequency can be increased. On the other hand, if the delay time is too long, the operation time of the combinational circuit 105 will be reduced, and fine tuning will be required.

However, in a simulation assuming a delay time at the time of completion in the design process, errors due to modeling at the time of simulation, errors in estimating the delay time, delay due to crosstalk between signals when actually operated, and actual Since errors such as a voltage drop when a current flows are included, it was not possible to completely correct the errors at the design stage by logic simulation or circuit simulation such as SPICE. For this reason, due to variations in the wafer process, which is a manufacturing process, variations in the clock delay and the delay of each signal in the semiconductor device occur, and the target value of the operating frequency cannot be achieved, or the required signal AC is not obtained. There is a problem that the yield is lowered due to a defect that the characteristics cannot be achieved. For this reason, it is necessary to repeat design prototypes until a target operating frequency and a target yield can be achieved, and there has been a problem that the development period and cost increase.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems. In a test after a wafer process, an optimum clock delay, a clock skew, and a signal delay are tested, and a clock is determined according to a test result. A signal delay capable of adjusting delays and signal delays, thereby increasing operating frequency, improving defective yield due to operating frequency, shortening development design period, and reducing cost. It is an object to obtain a semiconductor device having an adjusting function.

[0010]

SUMMARY OF THE INVENTION A semiconductor device according to the present invention is a semiconductor device having a delay time adjusting function for adjusting and setting a delay time of an input signal. A delay circuit for delaying an input signal by a selected delay time, a delay time selection unit for selecting a delay time of the signal delay unit according to input data, and a delay time selection unit. A data generating unit for generating data for instructing a delay time to be selected for the unit, and switching between data input from the outside and data generated by the data generating unit in accordance with a predetermined signal from the outside And a data switching unit that outputs the data to the delay time selection unit.

Further, the data generation section performs data generation such that the delay time of the signal delay section selected using data input from the outside is selected by the delay time selection section.

More specifically, the data generating section is formed by disconnecting at least one series circuit in which a plurality of fuses are connected in series between predetermined potentials representing binary data, and is cut off. The above data is generated by a combination of fuses.

[0013] In the data generation section, at least one series circuit in which a plurality of trimmable resistors are connected in series is connected between predetermined potentials indicating binary data, and is formed by trimming. The data may be generated by a set combination of resistors.

Further, the data generating section may include a switching circuit for controlling connection between predetermined potentials with respect to the series circuit in accordance with the predetermined signal from the outside.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a clock generation circuit that adjusts the delay of an input reference clock, generates an optimum clock, and outputs the clock is described. In this example, four types of clocks are generated and output by four delay adjustment circuits. In FIG. 1, the clock generation circuit 1 includes four delay adjustment circuits D1 to D4. Delay adjustment circuit D
A clock signal CLK optimized by a technique such as a clock tree and a test mode signal TEST which becomes a high level when a clock skew value test is performed are input to 1 to D4, respectively.

In order to adjust the delay time of the clock CLK, the delay adjustment circuit D1 receives the data signals TD0 and TD1, the delay adjustment circuit D2 receives the data signals TD2 and TD3, and the delay adjustment circuit D3 receives the data signals TD2 and TD3. The signals TD4 and TD5 are input to the delay adjustment circuit D4, and the data signals TD6 and TD7 are input to the delay adjustment circuit D4. Delay adjustment circuit D1
To D4 are clock signals C based on these input signals.
A corresponding clock signal CLK generated by delaying LK
1 to CLK4. Note that the delay adjustment circuits D1 to D
4 has the same circuit configuration, FIG. 1 shows only an example of the internal circuit of the delay adjustment circuit D1, and the internal circuits of the other delay adjustment circuits D2 to D4 are omitted. Therefore, the operation of the delay adjustment circuit D1 will be described below, and the operations of the other delay adjustment circuits D2 to D4 are the same as those of the delay adjustment circuit D1, and the description thereof will be omitted.

The delay adjustment circuit D1 includes inverters 11, 1
2. NAND circuits 13 to 16 and NOR circuits 17 and 18
And a P-channel type MO
S transistor (hereinafter referred to as PMOS transistor)
21 and 22 and a delay time setting section 20 formed by fuses 23 to 26. Further, the delay adjustment circuit D1
Are inverters 31 to 36 and NAND circuits 37 to 40
And a delay time adjusting unit 50 formed by buffers 51 to 54 and transmission gates 55 to 58.

In the multiplexer 10, the inverters 11 and 12 are connected in series in the forward direction. The input terminal of the serial circuit receives the test mode signal TEST, and the output terminal of the serial circuit connects the NAND circuits 13 and 15 Are connected to one input terminal. NAND circuit 13
TD0 is input to the other input terminal of
The output terminal of the ND circuit 13 is connected to one input terminal of the NOR circuit 17. The data signal TD1 is input to the other input terminal of the NAND circuit 15, and the output terminal of the NAND circuit 15 is connected to one input terminal of the NOR circuit 18.

The connection between the inverter 11 and the inverter 12 is connected to one input terminal of each of the NAND circuits 14 and 16. The other input terminal of the NAND circuit 14 is connected to the connection between the fuses 23 and 24 of the delay time setting unit 20, and receives the data signal TDa. NAN
The output terminal of the D circuit 14 is connected to the other input terminal of the NOR circuit 17. The other input terminal of the NAND circuit 16 is connected to the connection between the fuses 25 and 26 of the delay time setting unit 20, and receives the data signal TDb. N
The output terminal of the AND circuit 16 is connected to the other input terminal of the NOR circuit 18.

In the delay time setting section 20, a test mode signal TEST is input to each gate of the PMOS transistors 21 and 22, and each source of the PMOS transistors 21 and 22 is connected to a power input terminal VCC to which DC power is supplied. Each is connected. Also, PM
A series circuit of fuses 23 and 24 is connected between the drain of the OS transistor 21 and the ground. Similarly, a series circuit of fuses 25 and 26 is connected between the drain of the PMOS transistor 22 and the ground. It is connected.

On the other hand, the NOR in the multiplexer 10
The output terminal of the circuit 17 is connected to the input terminal of the inverter 31 in the decoder 30 and to one input terminal of each of the NAND circuits 37 and 39. Similarly, the output terminal of the NOR circuit 18 in the multiplexer 10 is connected to the decoder 3
0 and the input terminal of the inverter 32 and the NAND circuit 3
7 and one input terminal of the inverter 38.

In the decoder 30, the output terminal of the inverter 31 is connected to the other input terminal of the NAND circuit 38 and the NAND terminal.
The output terminal of the inverter 32 is connected to one input terminal of the circuit 40, and the output terminal of the inverter 32 is connected to the other input terminal of each of the NAND circuits 39 and 40. Each output terminal of the NAND circuits 37 to 40 is connected to a corresponding one of the inverters 33 to 3.
6, N-channel type M in transmission gates 55 to 58 in delay time adjusting section 50
It is connected to the gate of an OS transistor (hereinafter referred to as an NMOS transistor). Further, the NAND circuit 3
7 to 40 are connected to the PMOSs of the corresponding transmission gates 55 to 58 in the delay time adjusting unit 50.
It is connected to the gate of the transistor.

In the delay time adjusting unit 50, the buffer 5
1 to 54 are connected in series in the forward direction, and a clock signal CLK is applied to an input terminal of a buffer 51 forming an input terminal of the series circuit.
Is entered. Further, each output terminal of the buffers 51 to 52 is connected to one input / output terminal of the corresponding transmission gate 55 to 58, and the other input / output terminal of the transmission gates 55 to 58 is connected to each other to adjust the delay. The output terminal of the circuit D1 forms a clock signal CLK1.

In such a configuration, multiplexer 10 receives data signals TD0 and TD1 or data signals TDa and TDb input from delay time setting section 20 according to the signal level of test mode signal TEST.
Output any two signals. The delay time setting unit 20 generates and outputs data signals TDa and TDb according to the cut state of the fuses 23 to 26 according to the signal level of the test mode signal TEST. On the other hand, the decoder 30 decodes the data signal output from the multiplexer 10 and turns on one of the transmission gates 55 to 58 of the delay time adjusting unit 50. The delay time adjusting unit 50 controls the clock signal CL delayed by a time corresponding to the number of buffers connected to the input / output terminal of the transmission gate turned on by the decoder 30.
K is output as a clock signal CLK1.

When the high-level test mode signal TEST is input, the multiplexer 10 makes the input data signals TD0 and TD1 valid, and outputs a data signal corresponding to the signal levels of the data signals TD0 and TD1 to the NOR. The signals are output from the output terminals of the circuits 17 and 18.
At this time, both the PMOS transistors 21 and 22 of the delay time setting unit 20 are off. In such a state, the amount of delay of the clock signal CLK1 with respect to the clock signal CLK can be changed by changing the combination of the data signals TD0 and TD1.

That is, (TD0, TD1) = (0,
0), the transmission gate 55 is selected and turned on exclusively, and the clock signal CLK is supplied to the buffer 51.
And output as the clock signal CLK1 having the shortest delay time with respect to the clock signal CLK.
When (TD0, TD1) = (1, 0), the transmission gate 56 is selected and turned on exclusively, the clock signal CLK is delayed by the buffers 51 and 52, and the clock signal CLK is delayed for the second time. Is output as a short clock signal CLK1.

When (TD0, TD1) = (0, 1),
The transmission gate 57 is selected and turned on exclusively, the clock signal CLK is delayed by the buffers 51 to 53, and is output as the clock signal CLK1 having the second longest delay time with respect to the clock signal CLK.
When (TD0, TD1) = (1, 1), the transmission gate 58 is selected and turned on exclusively, and the clock signal CLK is delayed by the buffers 51 to 54,
It is output as clock signal CLK1 having the longest delay time with respect to clock signal CLK.

Thus, the data signals TD0 and TD1
By changing the combination of the data, the optimal clock signal C
A combination of data of the data signals TD0 and TD1 to be LK1 is obtained. For example, (TD0, TD
If the test mode signal TEST is at the low level, the combination of the data signals TDa and TDb from the delay time setting unit 20 is (TDa, TDb) when the test mode signal TEST is at the low level. The fuses 24 and 25 are cut by a laser trimming technique or the like so that) = (1, 0).

The laser trimming technique means that a fuse made of aluminum or polycrystalline silicon is selectively blown by laser irradiation or the like, or a polycrystalline silicon initially in a high resistance state is selectively laser-annealed. This shows a technique for lowering the resistance by lowering the resistance. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 5-36.
No. 297 and Japanese Unexamined Patent Application Publication No. Hei 11-17010, a redundancy technology for switching a defective address to a spare address for a defect of a highly integrated IC memory to make it a good product, and Japanese Patent Application Laid-Open No. 9-232119. It is used in the disclosed technique of trimming the resistance value.

On the other hand, when the test mode signal TEST is at the low level when the fuses 23 to 26 are not cut, a small current flows between the power supply input terminal VCC and the ground by the fuses 23 to 26. However, the test mode signal TE
When ST is at the High level, the PMOS transistors 21 and 22 are turned off, so that the power supply input terminal VCC
No current flows between the ground and the ground. For this reason, in the semiconductor device having the standby operation mode in which the power consumption is reduced in the standby state, the test mode signal TES
By setting T to a high level, the current consumption during standby can be accurately measured, and the standby test can be performed normally. After the fuse of the delay time setting unit 20 is cut, the test mode signal TEST is set to the Low level, and the current consumption during the standby is measured to determine whether the fuse is cut normally. it can.

Thus, when the test mode signal TEST is at the low level, the delay adjustment circuit D1 turns on the transmission gate 57 and turns on the clock signal CL regardless of the data signals TD0 and TD1.
The clock signal CLK1 delayed by the buffers 51 to 53 for K is output. Similarly, the delay adjustment circuits D2
Also in D4, clock signals CLK2 to CL each adjusted to a desired delay time with respect to clock signal CLK.
K4 is output.

In the above description, one clock signal CLK
However, the case where clock signals CLK1 to CLK4 adjusted to desired delay times by delay adjustment circuits D1 to D4 are output has been described as an example. However, as shown in FIG. 2, the signals SIG1 to SIG4 are supplied to the delay adjustment circuits D1 to D4.
And the delay adjustment circuits D1 to D4 may output the signals TSIG1 to TSIG4 obtained by adjusting the delay times of the input signals SIG1 to SIG4, respectively.

In the delay time adjusting section 50 of FIG. 1, a series circuit in which a plurality of buffers are connected in series may be connected instead of the buffer 51. Similarly, in the buffers 52 to 54, a plurality of buffers may be connected. May be replaced with a series circuit connected in series.
By doing so, the variation of the delay time adjustment amount can be changed.

For example, when designing an ASIC such as a high-speed gate array or a standard cell, the delay adjusting circuit D1 in FIG. 1 may be configured as shown in FIG.
In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof will be omitted and only the differences from FIG. 1 will be described.

The difference between FIG. 3 and FIG. 1 is that two delay times can be adjusted while four delay times can be adjusted in FIG. That is, in FIG. 3, in the multiplexer 10 of FIG.
The circuits 15 and 16 and the NOR circuit 18 are eliminated, and the delay time setting unit 20 shown in FIG.
And the fuses 25 and 26 have been eliminated. Further, in FIG.
In the decoder 30 in FIG. 1, the inverters 32 to 36 and the NAND circuits 37 to 40 are eliminated, and in the delay time adjusting unit 50 in FIG. 1, the buffers 53 and 54 and the transmission gates 57 and 58 are eliminated and the buffer 52 is eliminated.
, A series circuit of buffers 61 and 62 is connected and an output driver 63 is added.

When designing an ASIC such as a high-speed gate array or a standard cell, as shown in FIG. 3, the buffer 52 is changed to a serial circuit of the buffers 61 and 62 to reduce the delay time in the delay time adjusting unit. A fuse is cut after the chip is manufactured by preparing in advance each macro cell having variously changed variations and each macro cell of a variation having changed the driver size of the output driver 63 and selecting and incorporating the macro cell at a position where the delay is to be adjusted. Tuning of the delay time. Therefore, it is possible to easily improve the timing such as the operating frequency.

In the test process, fuses 23 to 26
Since the delay time of the optimum design value can be found at the prototype stage without cutting the wafer, if the target specification can be obtained within the variation range of the wafer process, the part to be trimmed by changing the layout is fixed. By performing mass production, the trimming process can be omitted, the number of trial productions can be reduced, and the development period and cost can be reduced.

As described above, the semiconductor device according to the present embodiment changes the combination of the data signals TD0 and TD1 in the test mode,
The delay time adjusting unit 50 delays the input signal by a time corresponding to the combination and outputs the delayed signal to adjust the optimum delay time.
26 are cut off, and the input signal is always output with an optimum delay time regardless of the data signals TD0 and TD1. From this, it is possible to eliminate the delay of the clock and the delay of each signal in the semiconductor device due to the variation in the manufacturing stage of the wafer process, achieve the target value of the operating frequency, and improve the operating frequency, The defective yield due to the operating frequency can be improved, the development design period can be shortened, and the cost can be reduced.

In the above-described embodiment, the fuse is cut to set the delay time. However, instead of the fuses 23 to 26, a predetermined on-chip resistor is used, and each of the on-chip resistors is used. May be trimmed to change the data combination of the data signals TDa and TDb. Needless to say, FIG. 1 shows an example in which four types of delay time can be adjusted, and FIG. 3 shows an example in which two types of delay time can be adjusted. However, this is an example,
The present invention is not limited to this,
In the same manner as described above, it may be possible to adjust the delay time to a plurality of types.

[0040]

As is apparent from the above description, according to the semiconductor device of the present invention, in the test mode in which a predetermined signal is input from the outside, the combination of the data input from the outside is changed to change the input. The signal is delayed by a time corresponding to the combination and output, so that the signal is adjusted to an optimum delay time, and a desired delay time can be set by using a data generator. From this, it is possible to eliminate the delay of the clock and the delay of each signal in the semiconductor device due to the variation in the manufacturing stage of the wafer process, and achieve the target value of the operating frequency.
The operating frequency can be improved, and the yield of high-speed operating frequency chips can be improved. Since a chip with a high operating frequency is expensive, the added value of the wafer can be increased as a result. In addition, since the signal delay time can be adjusted by a test performed after manufacturing, even for a circuit having a high-speed interface in which delicate timing between signals is defined, there are LSI chips that originally do not satisfy the interface standard. It can be used as a good product. Furthermore, in the prototype stage,
It is possible to find a design optimum value for absorbing an error between the simulation at the design stage and the actual prototype device, shorten the development period by reducing the number of trial production, and reduce the cost.

More specifically, by setting the optimum delay time obtained in the test mode in the data generator, the input signal is always delayed with the optimum delay time and output regardless of the data input from the outside. I did it. From this, the optimum delay time obtained in the test mode can be easily set after the chip is manufactured.

Further, by setting an optimum signal delay time obtained in a test mode in which a predetermined signal is input from the outside by a combination of fuses to be blown, an optimum signal delay time can be obtained with a simple and inexpensive configuration. Can be set.

The optimum signal delay time obtained in a test mode in which a predetermined signal is input from the outside may be set by a combination of trimmed and set resistors. Also, the optimum signal delay time can be set with a simple and inexpensive configuration.

Further, a switching circuit for connecting and disconnecting the series circuit between predetermined potentials in response to the predetermined signal from the outside may be provided. In this way, when the standby mode is set to reduce the power consumption in the standby state, the connection between the series circuit and the predetermined potential is cut off when measuring the current consumption in the standby mode. The current consumption during standby can be accurately measured, and the standby test can be performed normally.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating an example of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another example of the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a circuit diagram showing another example of the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a schematic block diagram showing an example of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Multiplexer 20 Delay time setting part 23-26 Fuse 30 Decoder 50 Delay time adjusting part D1-D4 Delay time adjusting circuit

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H03K 5/13 H01L 27/04 MF term (Reference) 5B015 JJ16 KB32 KB84 NN03 QQ10 QQ15 QQ18 RR01 5F038 AV15 CD06 CD08 CD09 DF04 DF05 DF07 DT02 EZ20 5F064 AA02 BB05 BB06 BB07 BB09 BB12 BB26 BB33 DD39 EE47 EE54 FF05 FF09 FF27 5J001 AA11 BB10 BB11 BB12 CC03 DD04 5L106 DD21 GG03 GG05 GG07

Claims (5)

[Claims] 1. A semiconductor device having a delay time adjusting function for adjusting and setting a delay time of an input signal, comprising a delay circuit for delaying a signal with a plurality of different delay times, A signal delay unit for delaying an input signal; a delay time selection unit for selecting a delay time of the signal delay unit according to input data; and a command for instructing the delay time selection unit to select a delay time. And a data switching unit that switches between data input from the outside and data generated by the data generation unit according to a predetermined signal from the outside and outputs the data to the delay time selection unit. And a semiconductor device comprising: 2. The data generation unit generates data such that a delay time of the signal delay unit selected by using data input from the outside is selected by the delay time selection unit. 2. The semiconductor device according to claim 1, wherein: 3. The combination of fuses, wherein at least one series circuit in which a plurality of fuses are connected in series is connected between predetermined potentials representing binary data and the fuse is cut. The semiconductor device according to claim 1, wherein the data is generated by: 4. The data generating section is formed by connecting at least one series circuit in which a plurality of resistors capable of being trimmed are connected in series between predetermined potentials indicating binary data, and performing trimming. 3. The semiconductor device according to claim 1, wherein said data is generated by a set combination of resistors. 5. The data generator according to claim 3, further comprising a switching circuit for controlling connection between predetermined potentials with respect to the series circuit in accordance with the predetermined signal from the outside. 5. The semiconductor device according to any one of 4.