JPH0951261A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an accurate time delay of the integrated circuit in a programmable way after the manufacture. SOLUTION: The circuit includes a program element, preferably a variable delay element 8 programmed by combinations of control signals whose levels are decided by a fuse program matrix 14. In the test mode, a multiplexer array 12 disconnects the program matrix 14 and gives a test mode control signal served by the user to the variable delay element 8. A proper delay is selected by observing the effect of all available delays by the control signal onto possible functions of the IC. After a proper delay is once decided, the program matrix 14 is revised by a program and a pattern of a proper control signal is permanently stored and given to the variable delay element 8, which generates such a delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for providing a precision programmable time delay to a post-manufacturing integrated circuit, and more specifically to a digitally maintained program on-chip. The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the semiconductor integrated circuit device, which confirms and provides the generated precise timing to an integrated circuit.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, an integrated circuit (IC) chip often includes a circuit which must respond within a desired time interval when receiving a clock signal. For example, there is a memory IC chip that includes a plurality of memory cells arranged in rows and columns and has sense amplifiers respectively coupled between complementary pairs of column bit lines. Upon receiving the sense enable signal, the sense amplifier must be enabled to generate and provide the true state of the memory cell read as the latched output signal. The sense enable signal may be a delayed version of the input clock signal. If the time delay is too short and the sense amplifier is enabled too early, under all circumstances it will not be possible to reliably read the true stored value. If the sense amplifier is enabled too late, access and system cycle time is slowed, time is wasted and the economic value of the IC with the sense amplifier is reduced.

The use of simulation techniques determines the initial expected timing delay for a given IC design prototyped. In practice, determining the exact amount of delay required for an IC chip is not always easy to determine. More specifically, semiconductor process variations, defects, and system offsets can introduce uncertainty into the expected delay. After making the prototype wafer,
Extensive testing, given extreme timing and environmental conditions, allows thorough characterization of it and a general approximation of the actual standard desired delay.

Based on the results of the characterization studies, subsequent fabrication masks can be modified, thereby permanently providing an amount of delay expected to be close enough to the actual standard desired delay during mass production. it can. The prior art attempts to provide adequate delay by modifying the metallization only. However, other layers often need to be modified to produce a time delay closer to the desired value determined by characterization.

[0005]

However, even though all sense amplifiers on all wafers are subject to a delay fixed by the same metallization,
The actual delay required will depend on the sense amplifier being manufactured. All of the memory cells fabricated on different wafers have the same speed in that they sense reliably in response to the inputs to the sense amplifier and generate enough signals to provide the optimal delayed latch signal. It would be ideal. However, there are manufacturing process variations, semiconductor defects and system offsets. For example, there are some defects in which the chip cannot be repaired, such as a short circuit from Vcc to ground. However, for a statistically significant number of defects, for example, to generate the appropriate signal,
It simply slows down the time required to generate sufficient signal from the memory cell to the bit line coupled to it.

As a result of these variables, individual I
For some of the C chips, it is possible that there are one or more sense amplifiers in the sense amplifier that function correctly but are slower than the sense amplifiers elsewhere in the chip. Fast-reacting ICs are more valuable in value than slow-reacting ICs and can generally be sold at higher prices. Slowly responding ICs can also be used in applications where the delay between the latch signal input and the sense amplifier output may be long, but such ICs would only sell at low selling prices.

Prior art metallization pattern techniques for fixing delay are relatively inflexible and
The delay cannot be customized after C has been manufactured. If the delay fixed by the metallization is too short, an IC chip with a defectively slow but functional sense amplifier will be enabled too early. In such cases, those sense amplifiers will not produce the proper output signal,
The IC cannot work. In the prior art, such IC chips generally cannot be salvaged. However, if the delay can be increased after manufacture, a significant number of these chips could work at slower speeds.

In addition, the prior art can achieve a suitable standard delay for some sense amplifiers on one IC chip, but for other sense amplifiers on the same chip, the delay will be unnecessarily long. . As such, these other sense amplifiers are forced to operate with unnecessarily long standard delays while still being able to fully function with short time delays. These chips, which are underutilized, can be
You have to sell it at a low price. That is, prior art delay technology must sacrifice production value, speed, or both.

What is needed is a test mode method for verifying the actual optimum delay on a chip-by-chip basis for manufactured ICs. Such delays should be individually programmable on an individual IC chip basis after fabrication is complete with acceptable delay resolution. In this way, it is possible to customize the time delay after manufacturing, realize a short delay, realize an IC chip with fast access time, and meet the demand for a faster and defect-free chip. Become. Moreover, such a method can extend the delay in order to maintain the functionality of a slow IC chip with small defects that slow the detection or generation of the read signal.

The present invention provides a semiconductor integrated circuit device and a method of manufacturing the same which can meet those needs.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The present invention is provided by program means 1
An on-chip variable delay element is provided that generates a time delay in response to a set of control signals. The programming means is preferably a matrix of programmable elements,
It includes a multiplexer array and an optional (ie, optional) combinational logic unit.
The variable delay element outputs a delayed version of the input signal.

In summary, the test mode procedure performed on a chip-by-chip basis after fabrication allows determination of the optimal time delay. This delay is then programmed and incorporated into the programming means so that the IC chip thereafter operates with its optimal time delay.

More specifically, in normal mode operation, the multiplexer array causes the control signal to be determined by the output signal of the matrix of programmable elements. The matrix contains m programmable elements, which are preferably fuses. In normal mode operation, this matrix connects up to 2 ^m combinations of fixed "0" or "1" matrix output signals to variable delay elements via multiplexer arrays and optional combinational logic units. .

The default values of these matrix output signals are preferably determined by the metallization pattern of the integrated circuit chip containing the invention. Furthermore, I
After manufacturing C, change these matrix output signals,
The delay provided by the variable delay element can be changed. For example, if the programmable element is a fuse, the selected fuse may be blown and the matrix reprogrammed, thus providing the desired change in time delay.

In test mode, on a chip-by-chip basis, a multiplexer array decouples the matrix from the variable delay elements, instead, up to 2 ^m types resulting from the m test mode program input signals provided by the user. Different "0" and "1"
Output signal combinations of the. In the test mode, any combination of test mode program input signals (corresponding to the same combination of matrix output signals)
Are provided to the variable delay element, which causes its delay to change.

In test mode, the IC's response is checked to determine the circuit's functionality for each of the various delays. Based on these results, an appropriately small time delay that can achieve acceptable and reliable IC performance can be determined. Then, the matrix is modified, preferably by blowing a pattern of fuses, to permanently generate a matrix output signal of a copy of the test mode output signal that has been found to provide the desired time delay. You can

In either mode, the resulting time delay is determined by the combination of "0" or "1" signals provided by the multiplexer array (via the optional combinatorial logic unit) to the variable delay element. To be done. The programmed delay is quantized into 2 ^m values ranging from a minimum delay to a maximum delay, preferably at substantially the same time increment.

In the normal mode operation of the present invention,
The input signal is received by a variable delay element, and the variable delay element also receives an appropriately matrixed control signal from a matrix array. The variable delay element then provides the appropriately delayed signal as an output, which delay signal is then fed to another circuit of the same chip,
For example, the delayed signal can be connected to a sense amplifier that requires the clock signal (or enable signal) for proper reading.

[0021]

1 shows an integrated circuit (IC) chip 2 including a variable delay element 8 for receiving an input signal as a semiconductor integrated circuit device according to an embodiment of the present invention, the input signal of which has an appropriate delay. Afterwards, it may be connected to some on-chip clocked circuits 4, 6 and also off-chip. In the embodiment shown, the input signal is preferably a master clock signal which is provided on-chip, for example generated by element 9 or directly provided off-chip. According to the invention, the IC chip 2 further comprises, in addition to the variable delay element 8, a combinatorial logic unit (whether or not to provide this is optional, i.e., a multiplexer array 12 and m units). Programmable elements (total 1
8, a programming matrix 14 including a programming matrix 14 (see FIG. 2) is included.

The variable delay element 8 receives the master clock input and is supplied by the multiplexer array 12, preferably via the optional combinatorial logic unit 10, as indicated by the control signals B ₁ -B _n , "0" and "0". The delayed clock output is generated according to the pattern of "1". In NORMAL mode of operation, the multiplexer array 12 couples the program matrix 14 to the variable delay element 8 (again, preferably via the optional combinatorial logic unit 10). Thus, the time delay of the variable delay element 8 is determined by this matrix. Test (TEST)
In mode, the program matrix 14 is detached,
The multiplexer array 12 instead couples the user-provided test mode control signals to the variable delay element 8 (again, preferably via the optional combinatorial logic unit 10).

In FIG. 1, combinatorial logic unit 10 receives as input the control signals A ₁ -A _m from the output of multiplexer array 12. Signal in test mode
When TEST = 1, the signals A ₁ -A _m are copies of the test mode signals (designated TM-A ₁ to TM-A _m ). Normal mode, for example, non-test mode, in, M-A from the output signal (M-A ₁ of the output signal A ₁ -A _m are programmed matrix 14 of the multiplexer array
₍ indicated by _m ).

The output control signal B ₁ − provided from the optional combinational logic unit 10 to the variable delay element 8
The number of B _n is independent of the number of input control signals A ₁ -A _m . For example, when m = 3, combinatorial logic unit 1
0 can provide up to 2 ³ different available combinations of output control signals B ₁ -B _n . In the embodiment shown, m = 3 and the combinational logic unit 10 is
A combinational logic element that produces n = 6 different outputs B ₁ -B ₆ with eight different combinations of "1" and "0". The number of control signals (n) required to fully program the variable delay element 8 depends on how the element 8 is implemented.

In the case of the embodiment of the variable delay element 8 shown in FIG. 3 (which will be explained later),
To provide 8 (2 ³ ) quantized smooth gradient time delays, m = 3 and n = 6 control signals B ₁ -B ₆
Was enough. However, the number n of control signals may be anywhere from 3 to 8 or more.

The design of such combinatorial logic is well known to those skilled in the art of logic design. However, how the combinatorial logic unit 10 can be implemented will be described later in connection with Table 2.

Although the test mode signal is shown as being generated off-chip in FIG. 1, it is actually an IC.
It may be generated on the chip 2. Further, in some applications it may not be necessary to provide the delayed clock output signal off-chip as shown in FIG. As will be appreciated, the IC chip 2 may include other circuits,
It may also receive or provide other input and output signals including, for example, power supply voltage, address input, data input / output and control signals.

In one embodiment, the IC chip 2 includes a plurality of memory cells (not shown) coupled to the clock operating circuits 4, 6 which clock operating circuits 4, 6 are sense amplifiers. Is preferred. But,
As will be appreciated, the clocked circuits 4, 6 may be any circuit that needs to deliver a delayed version of some other signal, typically an on-chip or off-chip input signal. As shown in FIG. 1, a buffer circuit 4 ′ for driving a large capacitive load 7,
6'is generally provided. The load 7 may be on-chip or off-chip. Further, although only a few clock operating circuits 4 and 6 are shown in FIG. 1, the IC chip 2 may actually have any number of such circuits.

From the precise timing provided by the present invention,
Including high-speed circuits such as memory circuits and high-performance processors,
It can be advantageous in many applications of integrated circuits.
However, the described embodiments focus on implementing memory circuits using the present invention.

As is commonly known to those skilled in the art of memory design, memory ICs include a plurality of memory cells that are addressably arranged in rows and columns. The sense amplifier is coupled between the complementary column lines to read the "0" or "1" value stored in the addressed memory cell. In read mode, the appropriate memory cells and sense amplifiers are enabled. Then, after a delay of typically a few ns,
The memory cell produces a signal large enough to allow the sense amplifier to correctly latch the small signal produced by the addressed memory cell to properly read the stored "0" or "1" value.

In the context of FIG. 1, the arrival of the master clock input signal may coincide with the beginning of signal generation by the memory cell in read mode. When the sense amplifier 4 or 6 receives the clock signal with an appropriate delay, the latched signal is correctly read from the memory cell. Those skilled in the relevant art will understand that delays that are too small do not guarantee complete generation of the signal from the memory cells to the bit lines. Further, the required time delay may vary from wafer to wafer, from IC chip manufactured from the same wafer, or even from bit line pairs of the same IC chip. If the memory cells, bit lines, and sense amplifiers are fully manufactured and infinitely fast, the amount of delay needed is very small, perhaps one or two fast inverter delays (current CMOS (complementary metal-oxidizer).
With e-semiconductor) technology, it will be <1 ns).

However, due to manufacturing variables including defects in the semiconductor formed of the circuit on the IC chip 2, a delay is unavoidable before the sense amplifier can be reliably read out. Such a delay corresponds to several inverter delays (eg 3-5 ns in current CMOS technology). For defective chips, 10-1 for accurate detection
5ns will be required.

It is possible to realize a sufficiently large fixed delay, perhaps 15 ns, because the slowest sense amplifier can generate a sufficient latch signal before a read occurs, but doing so would allow the IC chip 2 to Performance and selling price will be reduced.

The present invention allows the IC chip 2 to operate in the post-fabrication test mode with a time delay determined to be optimal for a particular IC. In the test mode, the output signal of the program matrix 14 is bypassed by the multiplexer array 12 and the optimum delay is determined by changing the test mode signal (TM-A ₁ etc.) provided by the user. The program element 18 in the program matrix 14 is then programmed to this optimum delay value for controlling the variable delay element 8 (also preferably via the optional combinatorial logic unit 10). This produces the minimum required time delay required for later normal mode operation.

Although FIG. 1 shows an IC chip 2 to which the present invention is applied only once, the present invention can, of course, be repeated in the same form or with modifications on the same chip. In doing so, different precision time delays can be generated and provided for different types of circuits on the IC chip 2.

FIG. 2 shows programming means 16 having a program matrix 14 (which contains program elements 18), a multiplexer array 12 and an optional combinatorial logic unit 10. The program matrix 14 is optional
It includes the metallization connection options indicated by T1-T3.

In FIG. 2, the program matrix 14
Comprises three (eg, m = 3) programmable elements F1-F3 (generally designated by reference numeral 18) and optional metallization options T1-T3. F1-F3 are preferably laser-fusible fuses. As such, the program matrix 14 provides a binary output signal _{M-A 1, M-A} 2, M-A 3 of m = 3, and, of course, whereby 2 ^three available control The signal combination B ₁ -B _n can be generated. As mentioned above, the combinational logic unit 10 only converts the three binary output signals into 2 ³ different usable combinations of "0" and "1" signals B ₁ -B ₆ in the normal mode. Then that signal will program the variable delay element 8.

The use of combinatorial logic unit 10 is optional. It is also possible to match the number of program elements to the number of control signals required to control the variable delay element 8. However, it is advantageous for the combinatorial logic unit 10 to allow the use of fewer program elements 18 in the program matrix 14. For example, in the organization of FIG. 2 using combinatorial logic unit 10, m = 3
Program elements can program up to six of the eight combinations of the control signals B ₁ -B _6. (As noted above, n can be any number in the range 3 to 8 or more).

Of course, depending on the granularity of the delay resolution variable provided by the variable delay element 8, more or less binary output combinations Am can be provided. The two binary signals A ₁ , A ₂ can produce delay resolutions up to 2 ² or 4 levels, the 4 binary signals can produce delay resolutions up to 16 levels, and so on. . In the embodiment of FIG. 2, m =
3 program elements produce 8 levels of programmed delay granularity.

According to the first metal pattern, M-A ₁ ,
Select one of any from among the possible eight combinations of _{M-A 2, M-A} 3, it is possible to generate any of the eight time delay. In fact, none of the program elements F1-F3 are programmed (eg by blowing a fuse) prior to the IC test.
Before such programming, the first M-A ₁ , M-
-A _2, "0" of the M-A ₃ or "1" value to the corresponding T-1 not each is determined by the metalization option T-3. For example in FIG. 2, but T-1 is prepared to be "1" M-A ₁ =, T-
2 is manufactured so that M−A ₂ = “0”. This couples the M-A ₁ line to the output of inverter I1B,
The M-A ₂ line, on the other hand, is achieved by coupling to the output of inverter I2A.

The delay due to the metallization pattern is first determined by simulation. However, the metallization pattern can be modified based on the results of the characterization study of the engineering prototype. Furthermore, at some later stage of mass production, the metallization pattern can be changed again later, depending on the history of the pattern for blowing the fuse. For example, in a significant number of IC to be actually mass produced, in order to generate the appropriate time delays, "1-0-1" is required as a pattern of A ₁ -A ₂ -A ₃ in which the matrix program However, if the original pattern is another different one, for example, "1-1-0", the metallization is changed so that the default value is "1-0-1" as shown in FIG. Can be provided. If this value is defaulted, then preferably a relatively small number of program elements F actually need to be programmed.
1-F3, which reduces the inspection cost and ultimately the cost of the finished chip. As will be appreciated, once the production process is stable and the optimal default values are determined, only a relatively small number of elements F1-F3 actually require programming time and expense.

In the test mode (TEST = 1), the circuit of the multiplexer MUX1A is opened and the circuit of the multiplexer MUX1B is closed. Thus disabled matrix programmed condition, the multiplexer array output signal A1 is any TEST mode signal "0" provided in MUX1B by the user as TM-A ₁ signal
Alternatively, it is set to "1". Similarly, during test mode, applied respectively to MUX2B and MUX3B as TM-A ₂ and TM-A ₃ signal "0" or "1" becomes the output signal A ₂ and A ₃ of the multiplexer array by the user .

The test mode signal provided by the user can be provided to multiplexer 12 in a variety of ways. For example, on-chip circuitry may logically generate these signals in response to other logic input signals. If desired, unconnected pads (“PADS” in FIG. 1) can be provided for access by the wafer probe card during wafer test mode. In this example, the test mode signal can be provided by the tester directly to these PADSs when probing the IC, but these pads have no other useful function. Alternatively, the input pads that perform some other function during normal mode operation can be rearranged and used to provide a user-provided test mode input signal to multiplexer array 12 during test mode.

A ₁ through the multiplexer array 12
As A ₂ , A _{3, and} as a result, control signals B ₁ -B ₆
Eight TM-A ₁ coupled as, TM-A _2, T
According to the combination of M-A ₃ , the variable delay element 8 is
Change the time delay between the master clock input and the delayed clock output. The delay can be generated in eight quantized steps, ranging from a minimum value to a maximum value, preferably with approximately equal time increments.

Since each of the control combinations can be provided in test mode, the entire IC chip 2 can be tested for function and speed (simple function is measured in response to incremental changes in time delay). , The so-called "schmoo test" procedure). T
Based on the results of the function of the IC chip 2 when given different combinations of TM-A ₃ from M-A _1, the tester selects the appropriate time delay to achieve the desired reliability margin of the IC. This delay time is the fuse element 18 first.
If the combination is different from the programmed combination, the appropriate fuse is blown and the output of the program matrix 14 is modified to match the newly determined optimum delay value.

The minimum delay required is determined by the IC manufacturer to accommodate quality and reliability specifications. For example, the test mode is typically performed in a low noise, low temperature environment, but the IC should function reliably in a wide range of conditions, for example, a wide temperature range, a noisy power supply environment, etc. There is expected. In practice, the manufacturer can select and program a delay time greater than the minimum delay as long as the IC functions properly in test mode.

Another consideration that affects whether or not the programming matrix 14 should be programmed is whether a slightly reduced delay (by programming the matrix) will result in a more valuable IC. For example, memory chips are typically graded by quantized speed increments. One of such memory chips
One, static random access memory (SRAM)
Are typically sold as speed grades of 15ns, 25ns, 35ns. So the specific IC
Increasing the speed of the program from 33 ns to 28 ns by the program matrix 14 cannot be sold at a high price, and the time and cost spent on the matrix program to achieve the 5 ns improvement is not justified.

However, if it is found that the IC functions in 27 ns in the default matrix program in the test mode and 22 ns can be reliably realized by the program matrix 14, the resulting "25 ns class" is obtained. ICs can be sold at higher prices and programming is justified.

On the other hand, for one or more sense amplifiers,
If the IC does not work, the default delay may be too short for proper sensing, and it may be remedied by programming the matrix to generate a reasonably long delay. The resulting IC will function at a slower speed, but if the speed is still within the same grade range, the selling price of the IC will be fully functional with the default conditions of matrix and metallization. It is the same price as the IC.

Even an initially non-functioning IC could be converted to a slower grade IC by slow delay,
The effect is obtained. ICs that work at slower speeds can be sold even at low prices. In either case, ICs that were discarded in the prior art can be salvaged by using the present invention, and can probably be sold at the same price as good quality ICs. Thus, by using the present invention, the actual production value per wafer and the income are increased.

In summary, to ensure that the circuits 4, 6 (or other off-chip circuits) operate, the appropriate signals TM-A ₁ , TM-A ₂ , T which produce the desired time delay.
When the M-A ₃ is determined, the test mode is terminated. Taking into account the above considerations, then the appropriate TM-A ₁ , T
Program matrix 14 is programmed to permanently provide a desired pattern of A ₁ -A ₂ -A ₃ of _{M-A 2, TM-A} 3 corresponding to the pattern 000 from 111.

[0052] For example, the M-A ₃ from the default pattern M-A ₁ metallization T1-T3 "1-0
-1 ", but" 1-1-1 "depending on the test mode
Is determined to achieve a more optimal time delay. Given the various considerations, and if programming is justified, then the fuse of program element F2 is blown (ie, "programmed"). As is apparent from FIG. 2, when the fuse of F2 is blown (that is, an open circuit), the transistor M ₂
There provides a logic value "0" to the inverter I2A, whereby M-A ₂ becomes "1". In this way, as desired, to M-A ₁ not of the desired M-A ₃ pattern "1-1
-1 "is realized.

After this point in the lifetime of a particular IC, one must try to retest, reshuffle, and reprogram the program elements F1-F for three times (that is, the IC chip 2 was tested by a dedicated IC tester). Unless it continues to be driven, it will hardly occur in a noticeable manner.) It is always in the normal mode with TEST = 0. In fact, the test mode is only realized under special circumstances driven by a dedicated IC tester. TE
It is important to design the circuit that generates the ST signal so that it does not enter the TEST = 1 mode improperly.

In the normal mode, MUX1B, MUX
The circuit of UX2B and MUX3B is open, and MUX1
The circuits of A, MUX2A, and MUX3A are closed. A
Whether ₁ , A ₂ and A ₃ are “0” or “1” depends on the metal mask pattern (see T1, T2 and T3 in FIG. 2).
Program elements F1-F3 are dependent on programmed or unprogrammed (eg, open or closed) conditions. After programming, it is practically preferable to thoroughly retest the IC chip 2 in the full range of production test electrical and environmental conditions.

In the preferred embodiment, the program elements F1, F2, F3 are positive power and metal-oxide-.
Semiconductor (MOS) type N-channel transistors M1 and M
It is a laser-cuttable fuse connected in series with 2 or M3. For example, in FIG. 2, M1, M
2 and M3 are MO with relatively high impedance and low current
S device. When the associated fuse is unprogrammed (ie, untouched), the low impedance of the fuse, relative to the high impedance of the MOS device, results in inverters I1A, I2A, I3A.
A logical value "1" is given to the input of. However, when the fuse is blown (ie, opened), the MOS devices M1, M2, M3 are strong enough to ensure the input of a logic "0" to the associated inverter.

In FIG. 2, the metallization pattern is as shown, and as the default A ₁ , A ₂ , and A ₃ patterns in the normal mode, “1-0-
1 ”is realized. In test mode,
When the pattern "1-1-1" optimizes the time delay and the fuse program is determined to be valid, the fuse F2 can be blown. When the fuse F2, M-A ₂ becomes "1", the multiplexer array 12 outputs to the optional combinational logic 10 of the pattern of "1-1-1", the delay time of the variable delay element 8 accordingly Will be fixed.

Although a fuse is shown in FIG. 2, it will be appreciated that the program element 18 can be any component configuration that can be permanently modified to produce the desired output pattern. Such components may include, but are not limited to, flash memory elements, anti-fuse elements, electrically programmable ROMs (EPROMs).

In some applications, the DC current may be required to be zero under some conditions (eg, "power down" with chip enable signal CE = 0). In such applications, M1-M3 are weak pull-down MOS devices whose gate signals are controlled by properly generated logic signals. These gating logic signals are such that the program matrix 14 is sampled as needed, but when not in the zero DC current mode. For example, programmed element status (fuse blown / not blown)
Can be sampled by a gated logic pulse signal and the sampled value can be stored, for example in a "CMOS latch. In this way, no additional DC current is required while the chip is powered and such sampling can be done, for example, in a special start cycle.

As to how the optimum time delay can be determined in test mode, and how to program the program matrix 14 to generate the pattern of control signals that permanently generate such delay. Now that it has been described, the operation of the variable delay element 8 will be described below with reference to FIG. 3 and Tables 1 and 2.

FIG. 3 includes a CMOS transistor, which is combined to form a multiplexer transmission gate, a programmable current source, and first and second.
Forming the inverter pair IP1 and IP2. The numbers placed on the source side of the MOS transistors, eg "5", "15", are according to the preferred embodiment.
It represents a relative width / length (W / L) magnification. Other W
/ L magnification can also be used, but as will be appreciated,
MOS devices with higher W / L ratio produce more drain-source current and can react faster than MOS devices with lower W / L ratio. As shown in FIG. 3, the parasitic load capacitor C can be intentionally coupled to the output of the inverter pair (IP2) to contribute an additional time delay. Of course, a transmission gate (not shown) may be used to controllably couple the capacitor C to or from the output of the inverter, thereby providing flexibility and range to the additional time delay. You can

As shown, the variable delay element 8 receives a master clock input signal, a number of program control signals B ₁ , B ₂ ... B ₆ and provides a delayed clock output signal. The delay of the delayed clock output signals from the master clock input is determined by their control signals, preferably received from combinatorial logic unit 10. Depending on the pattern of "1" and "0" of the control signal, the variable delay element 8 is in the range of the minimum delay (delay D0) to the maximum delay (delay D7), and the intermediate value of the delay is delay D2- A delay is generated at D6. Here, for the sake of simplicity, the notation “delay D0-D7” is used to represent various quantized amounts of delay.

According to the invention, the variable delay element 8
Implements a variable delay clock output by programmablely routing an input clock signal through one of several possible paths to a delay clock output port. For example, the minimum time delay (D0 case) is achieved by routing the master clock input signal directly through the transmission gate TG1 gated by B ₁ , / B ₁ . In doing so, perhaps a minimum delay of <0.5 ns is provided. For other delay cases, the master clock input signal is the inverter pair IP1 or IP.
Routed through either one of the two or through the series combination of both inverter pairs IP1 and IP2. It is preferable to have each one inverter pair operate with different time delays, and in FIG. 3, two such delays are shown for each inverter pair. For example, perhaps the maximum delay of> 5 ns (D7 case) is generated by the B ₅ , / B ₅ , B ₆ , / B ₆ signals operating each inverter pair with the slowest time delay. Unlike that, other route assignment routes and / or
Or source current setting can generate an intermediate delay D1-D6, the it is determined by appropriate pattern B ₁ -B ₆ of the control signal. As noted, the different delay states D0, D1, ... D7 quantize the time difference between the maximum delay and the zero delay, preferably into substantially equal time increments.

It can be noted in FIG. 3 that each of the inverter pairs IP1 and IP2 are respectively coupled in parallel to IP1 and IP2 when / B ₅ = 0 and / B ₆ = 0, respectively, and PMOS load transistors IP1-P. , IP2-
That is, P is included. Thus, when / B ₆ = 0, the circuit of FIG. 3 provides three times the source current to the inverter pair IP1, so IP1 exhibits a shorter time delay than / B ₆ = 1 and / B ₅ = 0. Then, the same applies to IP2. Similarly, IP1 and IP2 have B ₅ =
1 and B ₆ = 1 when IP1, IP2 to NMOS source transistor coupled in parallel IP1-N,
It contains IP2-N.

Table 1 shows operatively coupled IP1-P, IP1- for generating various delays D0-D7.
Inverter pair I including N, IP2-P, IP2-N
Figure 6 shows various combinations of P1 and IP2.

[0065]

[Table 1]

Table 2 shows various A ₁ -A ₃ matrix-generated 8 combinations of ₆ signals B ₁ -B _6.
, Which is preferably generated by the combinational logic unit 10 from the combination of, and its programmed state will cause the variable delay element 8 to generate delays D0-D7.

[0067]

[Table 2]

First of all, various A ₁ , A ₂ , A ₃
Consider how a signal produces different time delays. In state D0 where minimum delay is required, the master clock input signal bypasses both IP1 and IP2 and is coupled to the delayed clock output port by transmission gate TG1. In this minimum delay case, transmission gate TG2 coupled to B ₂ , / B ₂ and transmission gate TG3 coupled to B ₄ , / B ₄ are both open circuit, The delayed clock output port is isolated from the rest. In the same way, logic signal B ₁ −
By tracking the effect of different combinations of B _{6 on} the multiplexer transmission gate and MOS devices in FIG. 3, it will be seen that the results summarized in Table 1 are correct. IP1, IP1-P, I
By setting the W / L ratio of the MOS devices forming P1-N, IP2, IP2-P, and IP2-N to an appropriate value, the delay range and granularity can be controlled in a variable manner.

The design of combinatorial logic is known in the art. For example, in Table 2, the signal B ₁ is A ₁ , A
It can be generated by taking the logical NOR of ₂ and A ₃ . The signal B ₂ can be generated by _first performing a logical AND of A ₂ and A ₃ and inputting the intermediate signal and A ₁ to an OR gate. The output of the OR gate is signal B ₂ . If desired, the source transistors can be independently controlled in any combination for additional design flexibility. For example, in one direction, it may be desired to achieve a longer delay, for example, when the master clock input signal falls from a "1" to a "0", and a shorter delay in the opposite direction. unknown. To do so in the two inverter pair embodiment of FIG. 3 would require an additional number and / or combination of control signals.

4A, 4B and 4C show different time delays T _d provided by the present invention for different signals A ₁ , A ₂ and A ₃ . Of course, as will be appreciated, if eight or more steps of resolution between zero delay (D0) and maximum delay (D7) are desired, then program matrix 14 provides output lines greater than m = 3, Variable delay element 8 will provide additional delay options.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
Although the present invention has been described with respect to delaying signals used in the sense amplifier circuit of a memory, other circuits that require precise time delays can benefit from the present invention. More specifically, the present invention precisely controls the timing of a secondary sense amplifier of a memory circuit or the latch of an input sampler of a synchronous (clocked) IC of any type (memory or non-memory). It can also be used for technology.

[0072]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, according to the semiconductor integrated circuit device and the method of manufacturing the same of the present invention, regarding the manufactured IC,
It is possible to confirm the actual optimum delay on the basis of individual chip, and customize the time delay after manufacturing, which realizes IC chip with short delay and fast access time, which is faster and defect-free. It can meet the demand for chips.

In addition, such a method is a slow IC with small defects that slow the detection or generation of read signals.
The delay can be extended to maintain the functionality of the chip.

[Brief description of drawings]

FIG. 1 is an IC including a variable delay element, a program means including a matrix of program elements, a multiplexer array, and an optional combination logic unit according to a semiconductor integrated circuit device according to an embodiment of the present invention.
It is a figure showing a chip.

FIG. 2 shows the programming means of FIG. 1 according to the present embodiment, m =
It is the figure which showed in detail about the program element of 3.

FIG. 3 is a diagram showing one embodiment of a variable delay element that inserts one of eight (2 ³ ) delay values into a delayed clock output signal according to the present embodiment.

FIG. 4A is a programmed delay D0 according to an embodiment.
FIG. 7 is a diagram showing a comparison between a master clock input and a delayed master clock output regarding the.

FIG. 4B is a programmed delay D3 according to the present embodiment.
FIG. 7 is a diagram showing a comparison between a master clock input and a delayed master clock output regarding the.

FIG. 4C is a programmed delay D7 according to an embodiment.
FIG. 7 is a diagram showing a comparison between a master clock input and a delayed master clock output regarding the.

[Explanation of symbols]

 2 IC chip 4, 6 clock operation circuit (sense amplifier) 4 ', 6'buffer circuit 7 load 8 variable delay element 9 element 10 combinational logic unit 12 multiplexer array 14 program matrix 16 program means 17 fuse element

Claims (20)

[Claims] 1. A semiconductor integrated circuit device with on-chip circuitry for determining and maintaining a delay between an input signal and an output signal, the semiconductor integrated circuit device being coupled to receive the input signal and at least one program input signal. Variable delay means for providing a delayed version of the input signal as the output signal after a time delay, the delay being determined by the at least one program input signal,
Variable delay means and programming means coupled to the variable delay means for determining and maintaining one selected from a plurality of combinations of the at least one program input signal, the selected one combination And a program means for generating the delay, the semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein said programming means includes m programmable elements, each one of which is a logical value “1”.
Alternatively, a semiconductor integrated circuit device characterized by being capable of maintaining a state of "0". 3. The semiconductor integrated circuit device according to claim 2, further comprising means for logically coupling the programmable elements to generate 2 ^m combinations of the program input signals. A semiconductor integrated circuit device comprising: 4. The semiconductor integrated circuit device according to claim 2, wherein the element is a fuse that can be cut by a user, and the selected one of a plurality of combinations.
A semiconductor integrated circuit device, wherein a selected one of the fuses is blown to generate one. 5. The semiconductor integrated circuit device according to claim 2, wherein when a test mode signal is received, the matrix of m elements is separated from the variable delay means, and a plurality of program input signals provided by a user are provided. The programming means is further coupled to the matrix of m elements and includes a multiplexing means coupled to the variable delay means for coupling a combination to the variable delay means, The semiconductor integrated circuit device, wherein the delay is determined by the combination of program input signals provided by a user. 6. The semiconductor integrated circuit device according to claim 1, wherein the variable delay means selectively bypasses at least a first delay generation inverter transistor pair and the delay generation inverter transistor pair. A transmission gate, wherein the input signal appears as the output signal through the first delay generating inverter transistor pair in the first time delay state, and the input signal in the second time delay state. Bypasses the first delay generation inverter transistor pair. 7. The semiconductor integrated circuit device according to claim 6, further comprising a delay changing transistor coupled in parallel to the transistors of the first delay generating inverter transistor pair in a switchable manner, and the delay changing transistor. A semiconductor integrated circuit device, wherein a transistor changes a time delay generated by the first delay generation inverter transistor pair in response to the program input signal. 8. The semiconductor integrated circuit device according to claim 1, wherein the on-chip circuit is manufactured on an integrated circuit chip including at least one circuit coupled to receive the output signal. A characteristic semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 8, wherein the at least one circuit includes a memory sense amplifier. 10. A method of manufacturing a semiconductor integrated circuit device for determining and maintaining a delay between an input signal on an integrated circuit chip and an output signal on the integrated circuit chip, the input signal and at least one program. Variable delay means coupled to receive an input signal and for providing a delayed version of the input signal as the output signal after a time delay, the delay being determined by the at least one program input signal. Providing variable delay means on the integrated circuit chip for determining and maintaining one selected from a plurality of combinations of the at least one program input signal coupled to the variable delay means. Programming means, wherein the selected one combination is for generating the delay. A step of providing on-up consists method for manufacturing a semiconductor integrated circuit device characterized by delayed determining maintained between the input signal and the output signal on the integrated circuit chip on an integrated circuit chip. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the step of providing a programming means includes providing a matrix of m programmable elements, each one of the elements being provided. A method of manufacturing a semiconductor integrated circuit device, which is capable of maintaining a state of a logical value "1" or "0". 12. The method of manufacturing a semiconductor integrated circuit device according to claim 11, further comprising logically combining the programmable elements to generate 2 ^m combinations of the program input signals. A method of manufacturing a semiconductor integrated circuit device, further comprising: 13. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the programmable element is a fuse that can be cut by a user.
A method of manufacturing a semiconductor integrated circuit device, wherein a selected one of the fuses is blown to generate the one combination selected from a plurality of combinations. 14. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein said integrated circuit chip requests at least two different time delays, and said step of providing variable delay means comprises at least two variable delays. A method of manufacturing a semiconductor integrated circuit device, comprising providing means, and the step of providing the program means includes providing at least one of the program means. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein the step of providing programming means further comprises: receiving a test mode signal from the variable delay means to form a matrix of m elements. Coupled to the matrix of m elements for decoupling and for coupling a combination of program input signals provided by a user to the variable delay means,
Also, comprising semiconductor multiplexing means coupled to the variable delay means, wherein the delay is determined by the combination of program input signals provided by a user during the test mode signal. Manufacturing method of integrated circuit device. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the variable delay means selectively bypasses at least the first delay generation inverter transistor pair and the delay generation inverter transistor pair. At least one transmission gate for transmitting the input signal through the first delay generating inverter transistor pair to appear as the output signal in the first time delay state and in the second time delay state. A method of manufacturing a semiconductor integrated circuit device, wherein the input signal bypasses the first delay generation inverter transistor pair. 17. A method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the variable delay means is coupled to the transistors of the first delay generation inverter transistor pair in a switchable manner in parallel. A method of manufacturing a semiconductor integrated circuit device, comprising a transistor, wherein the delay changing transistor changes a time delay generated by the first delay generating inverter transistor pair in response to the program input signal. 18. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the integrated circuit chip is coupled to the variable delay means, and the time delay is programmed by a metallization pattern on the integrated circuit chip. A method of manufacturing a semiconductor integrated circuit device, further comprising the step of providing a metallization default program means for 19. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the metallization default program means is required in the step of providing the following list of criteria, (a) programming means. Minimize programming; and (b) provide a default time delay that, according to the actual historical data, matches the actual required delay by a significant number of the mass-produced integrated circuit chips. A method for manufacturing a semiconductor integrated circuit device, characterized in that the method is programmed according to a standard. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the integrated circuit chip includes at least one sense amplifier coupled to receive the output signal. Manufacturing method of integrated circuit device.