JP4115243B2 - GaN-based III-V nitride semiconductor two-terminal device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a GaN-based III-V nitride semiconductor two-terminal device having non-linear voltage-current characteristics. More specifically, it is a GaN-based III-V group nitride semiconductor two-terminal device having voltage-current characteristics shown by a varistor.
[0002]
[Prior art]
A varistor is known as one of semiconductor two-terminal elements exhibiting non-linear voltage-current characteristics. FIG. 6 shows the voltage-current characteristics exhibited by the varistor. As shown in FIG. 6, even if a positive or negative voltage is applied between the terminals, no current flows until a predetermined positive or negative voltage. However, when V _{b +} and V _b− are reached, current suddenly flows, and once the current rises, the resistance between the terminals becomes extremely low.
[0003]
As described above, since the varistor exhibits high resistance while the voltage applied between the terminals is low, even if it is connected in parallel to the circuit, the operation of the circuit is hardly affected. However, when an abnormally high voltage is applied between the terminals, the resistance is low, and an abnormal current flows to the varistor side, so that the connected circuit can be protected. Utilizing such properties of varistors, varistors are used for lightning arresters for power transmission lines and communication circuits, shock voltage absorbers for electronic devices, overvoltage protection for rectifiers and thyristors, protection for relay contacts, and the like.
[0004]
When the varistor element is composed of a semiconductor, as shown in FIG. 7, p-type impurities are diffused from both sides of the n-type Si substrate 15 to form p-type semiconductor layers 16 and 17 and pnp junctions (from pn junctions 18 and 19). And electrodes 20 and 21 are formed on the surfaces of the p-type semiconductor layers 16 and 17.
This element can be regarded as an element in which two diodes are equivalently connected in the opposite direction as shown in the inset of FIG. 6, and exhibits a voltage-current characteristic as shown in FIG. In addition to Si semiconductors, there are varistors using Ge or GaAs.
[0005]
In addition to varistors based on semiconductors, there are varistors made of a sintered body based on SiC as shown in FIG. The SiC varistor is obtained by adding a ceramic binder such as clay and carbon or metal oxide to a fine powder of carborundum (SiC) and sintering at a high temperature of about 1300 ° C. Each of the produced SiC fine powders of the varistor is equivalent to a diode connected in the reverse direction, and the sintered body as a whole exhibits voltage-current characteristics as shown in FIG.
[0006]
[Non-Patent Document 1]
Tetsuro Ishida, “Semiconductor Device”, Corona, 1978, p232
[0007]
[Problems to be solved by the invention]
In FIG. 6, the current suddenly flows when V _{b +} and V _b− are exceeded, mainly because one of the two diodes described in the equivalent circuit of FIG. 6 breaks down. Since semiconductors based on Si, GaAs, and Ge have a small band gap of 0.5 to 1.5 eV, it is difficult to produce a varistor with a low breakdown voltage and high V _{b +} and V _b− values. Met.
[0008]
Further, even when a varistor is manufactured using a sintered body such as SiC, the V _{b +} and V _b− values can be made higher than those of a varistor using Si, GaAs, and Ge based semiconductors. About 200V is the limit.
[0009]
The present invention has been made in view of the above-mentioned drawbacks of the prior art, and an object thereof is to realize a varistor having high V _{b +} and V _b− values.
[0016]
As in the First claim 1 of the present invention, a laminated structure in which a p-type semiconductor layer and the n-type semiconductor layer made of AlGaN or AlInGaN constituting pnp structure or npn structure are laminated, the outermost of the stacked structure Provided with electrodes respectively formed on the upper layer and the lowermost layer
It is characterized by that.
[0017]
In the first aspect of the present invention constitutes a semiconductor two-terminal elements by two pn junctions, the pn junction is formed by p-type semiconductor elements and n-type semiconductor element made of AlGaN or AlInGaN. Therefore, V _{b +} and V _b− can be increased.
[0018]
The second aspect of the present invention as claimed in claim 4, wherein, ini structure and i-type semiconductor layer and the n-type semiconductor layer made of AlGaN or AlInGaN is laminated or i-type semiconductor layer and the p-type semiconductor layer, are stacked It is characterized by comprising a laminated structure constituting an ipi structure and electrodes formed respectively on the uppermost layer and the lowermost layer of the laminated structure.
[0019]
In the second aspect of the present invention constitutes an AlGaN or ini structures i-type semiconductor layer and the n-type semiconductor layer and are stacked consisting AlInGaN or i-type semiconductor layer and the p-type ipi structure semiconductor layer are stacked, In addition, since the p- type semiconductor layer or the n-type semiconductor layer is sandwiched between undoped semiconductor layers having high insulating properties , V _{b +} and V _b− can be further increased.
[0020]
According to a fifth aspect of the present invention, there is provided an undoped structure between the p-type GaN-based III-V group nitride semiconductor layer and the n-type GaN-based group III-V nitride semiconductor layer constituting the pn junction. A GaN-based group III-V nitride semiconductor layer is sandwiched.
[0021]
In the fifth aspect of the present invention, an undoped GaN-based III-V nitride semiconductor layer is sandwiched between a p-type semiconductor layer and an n-type semiconductor layer. Therefore, the impurity of the p-type semiconductor layer and the impurity of the n-type semiconductor layer do not diffuse each other. Therefore, the influence of diffusion on V _{b +} and V _b− is small.
[0022]
According to a sixth aspect of the present invention, as described in claim 7, the semiconductor two-terminal element is configured by a stacked structure of GaN-based III-V nitride semiconductor layers constituting two in junctions or ip junctions. Features.
[0023]
In the sixth aspect of the present invention, the semiconductor two-terminal element is configured by a pn junction because the semiconductor two-terminal element is configured by the laminated structure of the GaN-based III-V group nitride semiconductor layers forming two in-junction or ip-junction. V _{b +} and V _b− can be increased as compared with FIG.
[0024]
According to a seventh aspect of the present invention, as described in claim 8, the GaN-based III-V group nitride semiconductor layers constituting the in-junction, ip-junction, and pn-junction are different from each other.
[0025]
According to the seventh aspect of the present invention, since the band gaps of the semiconductor layers constituting the in-junction, ip-junction, and pn-junction are different from each other, V _{b +} and V _b− can be set to different values.
[0026]
According to an eighth aspect of the present invention, as described in claim 9, a GaN system having a smaller band gap than the GaN-based III-V nitride semiconductor layer between the GaN-based III-V nitride semiconductor layers connected to the electrode. A III-V nitride semiconductor layer is sandwiched.
[0027]
According to the eighth aspect of the present invention, a GaN-based III-V group nitride having a smaller band gap than the GaN-based group III-V nitride semiconductor layer between the GaN-based group III-V nitride semiconductor layers connected to the electrodes. Since the physical semiconductor layer is sandwiched, the contact resistance of the electrode can be reduced. Therefore, the resistance after the current rise can be reduced.
[0028]
According to a ninth aspect of the present invention, the electrode is made of a metal silicide alloy.
[0029]
In the ninth aspect of the present invention, since the metal silicide alloy is used as the electrode, the contact resistance can be reduced.
[0030]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a GaN-based III-V nitride semiconductor two-terminal element according to the present invention will be described below with reference to the drawings. In the description of the drawings, the same or similar parts are given the same or similar reference numerals and names. Also, it should be noted that the drawings are schematic and are different from actual ones. Of course, the drawings include portions having different dimensional relationships and ratios.
[0031]
First, the laminated structure of the GaN-based III-V group nitride semiconductor two-terminal element according to the embodiment will be described with reference to FIG.
On a sapphire substrate 7 as shown in FIG. 2, p-type semiconductor layer 2 composed of the buffer layer 1 made of _{GaN, p-Al x Ga 1} -x N (0 ≦ x ≦ 1), n-Al y Ga 1- _{y n (0 ≦ y ≦ 1} ) (0 ≦ y ≦ 1) n -type semiconductor layer 4 made _{of, p-Al z Ga 1-} z n p -type semiconductor layer 6 made of (0 ≦ z ≦ 1) is formed ing. With this structure, two pn junctions 3 and 5 are formed. An electrode 8 connected to the p-type semiconductor layer 2 and an electrode 9 connected to the p-type semiconductor layer 6 are formed.
[0032]
The manufacturing method of the above-described GaN-based III-V nitride semiconductor two-terminal device is as follows, and uses a gas source molecular beam epitaxial growth method (GSMBE method).
That is, as shown in FIG. 1, dimethylhydrazine (5 × 10 ⁻⁵ Torr) is used as the N source and metal Ga (5 × 10 ⁻⁷ Torr) is used as the Ga source on the sapphire substrate 7, and the growth temperature is 640 ° C. A GaN buffer layer 1 having a thickness of 50 nm was formed. Furthermore, ammonia (5 × 10 ⁻⁶ Torr) as the N source, metal Ga (5 × 10 ⁻⁷ Torr) as the Ga source, Al (1 × 10 ⁻⁷ Torr) as the Al source, and a metal that is a p-type dopant Mg (5 × 10 ⁻⁹ Torr) is added to form a p-type semiconductor layer 2 (doping concentration 5 × 10 ¹⁸ cm ⁻³ ) made of p-Al _x Ga _1-x N with a growth temperature of 850 ° C. and a thickness of 2 μm. did.
[0033]
Then, Al (1 × 10 ⁻⁷ Torr) and n-type dopant metal Si (5 × 10 ⁻⁹ Torr) are used for the above N source and Ga source, and the growth temperature is 850 ° C. and the thickness is 2 μm. _An n-type semiconductor layer 4 (doping concentration 5 × 10 ¹⁸ cm ⁻³ ) made of _y Ga _1-y N was formed.
[0034]
Next, Al (1 × 10 ⁻⁷ Torr) and metal Mg (5 × 10 ⁻⁹ Torr) as a p-type dopant are added to the N source and Ga source described above, and GSMBE is grown at a growth temperature of 850 ° C. A p-type semiconductor layer 6 (doping concentration 5 × 10 ¹⁸ cm ⁻³ ) made of p-Al _z Ga _1-z N with a thickness of μm is formed. As a result, two pn junctions 3 and 5 are formed, and the stacked structure in FIG. 1 is completed.
[0035]
The layer structure of FIG. 1 completes a GaN-based III-V nitride semiconductor two-terminal device through a process of forming electrodes 8 and 9 as shown in FIG. That is, after a SiO ₂ film is formed on the surface of p-Al _z Ga _{1 -z} N (p-type semiconductor layer 6) by plasma CVD, patterning is performed with a photoresist, and wet etching is performed using this SiO ₂ film as a mask. Then, a part of the laminated structure is removed by etching until the surface of the p-Al _x Ga _1-x N layer (p-type semiconductor layer 2) is exposed, and the p-Al _x Ga _1-x N layer (p-type semiconductor) A partial surface of layer 2) was exposed.
[0036]
Then after removing the SiO ₂ film was formed again SiO ₂ film on the entire surface, there is formed an electrode opening, on the _{p-Al z Ga 1-z} N layer (p-type semiconductor layer 6) Ti / Pt is vapor-deposited to form an electrode 9, and Ti / Pt is vapor-deposited on p-Al _x Ga ₁ -xN (p-type semiconductor layer 2) to form an electrode 8 as shown in FIG. The GaN-based III-V nitride semiconductor two-terminal device shown is completed.
[0037]
When the GaN-based group III-V nitride semiconductor two-terminal device of FIG. 1 was used as a varistor, the following characteristics were obtained. At this time, x = 0.2, y = 0.5, and z = 0.2.
That is, when the area of the pn junctions 3 and 5 is 500 × 500 μm ⁻² , V _{b +} and V _b− indicate 300V and −300V, respectively. This is 30 times as large as V _{b +} and V _{b− of} Si, GaAs, and Ge varistors having the same junction area, which are 10V and −10V, respectively.
[0038]
Furthermore, it has been found that the upper limit of the temperature at which a Si, GaAs, Ge-based varistor can operate normally is 150 ° C., whereas the varistor described above operates normally even at a high temperature of 600 ° C.
[0039]
The values of x, y, and z of the varistor described above were 0.2, 0.5, and 0.2, respectively, but are not limited thereto. In particular, when the values of x, y, and z are changed, the values of V _{b +} and V _b− can be changed freely. Therefore, it is possible to produce a varistor tailored to the application. In this embodiment, a varistor having a pnp structure is used, but a varistor having an npn structure is also possible.
[0040]
Further, p-AlGaN layer (p-type semiconductor layers 2 and 6), the doping concentration of the _{n-Al y Ga 1-y} N layer (n-type semiconductor layer 4) was the 5 × 10 ¹⁸ cm ^-3, which is not limited to, it can be varied in the range of ^{1 × 10 17 cm -3 ~1 ×} 10 19 cm -3. A varistor made of a Si-based semiconductor has a problem that the values of V _{b +} and V _b− are remarkably reduced when high concentration doping is performed in order to reduce the resistance at the time of current rising. However, the varistor made of a GaN-based III-V group nitride semiconductor according to the present invention can reduce the resistance at the time of current rise without lowering V _{b +} and V _b− even at high concentration doping.
[0041]
In this embodiment, Ti / Pt is used as the material of the electrodes 8 and 9, but if a metal silicide alloy is used instead of these, the electrode resistance can be greatly reduced. Examples of the metal material of the metal silicide alloy include Ta, Al, Ti, Cu, Pt, Pd, Ag, Ni, W, Mo, Cr, In, Sn, and Mn. Therefore, the resistance at the time of current rising can be reduced.
[0042]
In this embodiment, the electrodes 8 and 9 are formed directly on the surface of the p-type semiconductor layers 2 and 6, but a p-type contact is provided between the electrodes 8 and 9 and the p-type semiconductor layers 2 and 6 as shown in FIG. Layers 10 and 11 may be formed.
[0043]
In particular, the contact resistance of the electrode / contact layer can be reduced by making the band gap of the contact layers 10 and 11 smaller than the band gap of the p-type semiconductor layers 2 and 6. In particular, the effect can be further enhanced by combining with the electrode of the metal silicide alloy described above. In FIG. 3, InGaN is used for the contact layers 10 and 11. Here, the thickness of the contact layer is 50 to 500 nm, and the doping concentration is suitably 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ .
[0044]
Further, as shown in FIG. 3, an undoped layer 12 can be inserted between the n-type semiconductor layer 4, the p-type semiconductor layer 2, and the p-type semiconductor layer 6. When the n-type semiconductor layer 4 and the p-type semiconductor layers 2 and 6 are directly joined, the impurities in the two layers diffuse to each other, so that V _{b +} and V _b− may slightly decrease, but the undoped layer 12 By interpolating, it is possible to prevent mutual diffusion.
[0045]
Furthermore, although the above example consists of two pn junctions 3 and 5, three or more pn junctions may exist. As a result, V _{b +} and V _b− can be further increased.
[0046]
In this embodiment, the varistor has a pnp structure and an npn structure. However, as shown in FIG. 4, an ipi varistor having two ip junctions or an ini structure varistor having two in junctions can be produced. is there. According to this, since the p-type semiconductor layer 6 or the n-type semiconductor layer exhibiting conductivity is sandwiched between the undoped semiconductor layers 12 having high insulation, the V _{b +} and V _b− values can be further increased.
[0047]
In the above example, V _{b +} and V _b− of the manufactured varistor cannot be controlled. However, as shown in FIG. 5, from the n-type semiconductor layer 4 between the p-type semiconductor layers 2 and 6 to which the electrodes 8 and 9 are connected. By pulling out the electrode 14, V _{b +} and V _b− can be controlled.
[0048]
In this embodiment, the laminated structure is formed on the substrate, but the substrate may be removed. The substrate is removed by irradiating a laser from the back surface of the substrate after forming the front surface electrode. Since the heat dissipation is improved by removing the substrate, the performance is improved when used as a large-capacity varistor.
[0049]
In this embodiment, a sapphire substrate is used as the substrate 7, but Si, SiC, GaAs, or GaP may be used instead of the sapphire substrate. Since these substrates are cheaper than sapphire substrates, they are advantageous in terms of cost.
[0050]
In this embodiment, AlGaN is used as the semiconductor material of the p-type semiconductor layer, the n-type semiconductor layer, and the undoped semiconductor layer. However, the present invention is not limited to these, and all GaN-based III-V nitride semiconductors are used. Can be used. The same applies to the contact layers 10 and 11 as long as the condition that the band gap is smaller than that of the p-type semiconductor layer 6 and the n-type semiconductor layer 4 is satisfied. For example, AlInGaN, AlGaNP, AlGaNAs, AlGaNP, AlGaNAs, AlInGaNAsP and the like can be mentioned.
[0051]
【The invention's effect】
As described above, according to the present invention, a varistor having excellent high temperature characteristics and high V _{b +} and V _b− values can be produced.
[Brief description of the drawings]
FIG. 1 shows a stacked structure of a semiconductor used for manufacturing an embodiment of the present invention. FIG. 2 shows a stacked structure of an embodiment of the present invention.
FIG. 3 shows another embodiment of the present invention.
FIG. 4 shows still another embodiment of the present invention.
FIG. 5 shows still another embodiment of the present invention.
FIG. 6 shows voltage-current characteristics of a varistor.
FIG. 7 shows the structure of a conventional varistor.
FIG. 8 shows another structure of a conventional varistor.
[Explanation of symbols]
1 buffer layer 2 p-type semiconductor layer 3 pn junction 4 n-type semiconductor layer 5 pn junction 6 p-type semiconductor layer 7 substrate 8 electrode 9 electrode 10 contact layer 11 contact layer 12 undoped semiconductor layer 13 electrode 14 electrode 15 Si substrate 16 p-type Semiconductor layer 17 p-type semiconductor layer 18 pn junction 19 pn junction 20 electrode 21 electrode

Claims (9)

A pnp structure in which a p-type semiconductor layer made of AlGaN or AlInGaN and an n-type semiconductor layer are laminated, or a laminated structure constituting an npn structure;
A GaN-based group III-V nitride semiconductor two-terminal device comprising electrodes formed on the uppermost layer and the lowermost layer of the laminated structure, respectively.   2. The GaN-based III-V group according to claim 1, further comprising an undoped (i-type) GaN-based III-V nitride semiconductor layer between the p-type semiconductor layer and the n-type semiconductor layer. Nitride semiconductor two-terminal device.   A GaN-based III-V nitride semiconductor having a smaller band gap than the uppermost layer or the lowermost layer and having the same conductivity type as the uppermost layer or the lowermost layer, between the uppermost layer or the lowermost layer and the electrode, respectively. 3. The GaN-based group III-V nitride semiconductor two-terminal element according to claim 1, further comprising a contact layer made of: An ini structure in which an i-type semiconductor layer and an n-type semiconductor layer made of AlGaN or AlInGaN are laminated, or a laminated structure constituting an ipi structure in which an i-type semiconductor layer and a p-type semiconductor layer are laminated,
A GaN-based group III-V nitride semiconductor two-terminal device comprising electrodes formed on the uppermost layer and the lowermost layer of the laminated structure, respectively.   4. The GaN-based III-V group nitride semiconductor according to claim 1, further comprising a control electrode on the n-type semiconductor layer having the pnp structure or the p-type semiconductor layer having the npn structure. Two-terminal element.   5. The GaN-based III-V nitride semiconductor two-terminal element according to claim 4, further comprising a control electrode in the n-type semiconductor layer having the ini structure or the p-type semiconductor layer having the ipi structure.   7. The GaN-based group III-V nitride semiconductor two-terminal element according to claim 1, wherein the electrode is made of a metal silicide alloy.   8. The metal of the metal silicide alloy according to claim 7, wherein the metal is any one of Ta, Al, Ti, Cu, Pt, Pb, Ag, Ni, W, Mo, Cr, In, Sn, or Mn. GaN-based III-V nitride semiconductor two-terminal device.   9. A GaN-based group III-V nitride semiconductor, wherein the GaN-based group III-V nitride semiconductor two-terminal device according to claim 1 is connected in parallel to a predetermined circuit and used as a varistor. Two-terminal element.

Images