CN110993688A - Three-terminal semiconductor device and manufacturing method thereof - Google Patents
Three-terminal semiconductor device and manufacturing method thereof Download PDFInfo
- Publication number
- CN110993688A CN110993688A CN201911218758.1A CN201911218758A CN110993688A CN 110993688 A CN110993688 A CN 110993688A CN 201911218758 A CN201911218758 A CN 201911218758A CN 110993688 A CN110993688 A CN 110993688A
- Authority
- CN
- China
- Prior art keywords
- electrode
- heterojunction
- layer
- semiconductor device
- doped layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 230000010287 polarization Effects 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 4
- 239000012670 alkaline solution Substances 0.000 claims description 4
- 230000002269 spontaneous effect Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 114
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 11
- 229910002601 GaN Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- -1 silicon ions Chemical class 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
- H01L29/454—Ohmic electrodes on AIII-BV compounds on thin film AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention provides a three-terminal semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The three-terminal semiconductor device comprises a supporting layer, a heterojunction arranged on the supporting layer, a first electrode, a second electrode and a grid electrode, wherein the first electrode, the second electrode and the grid electrode are arranged on the heterojunction; wherein at least one of the first electrode and the second electrode comprises: a doped layer disposed on the heterojunction and an electrode contact layer disposed on the doped layer. The three-terminal semiconductor device can reduce contact resistance, reduce switching loss of the device and cannot cause the device to be broken down in advance.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a three-terminal semiconductor device and a manufacturing method thereof.
Background
Currently, because gallium nitride (GaN) materials have a large forbidden bandwidth, power semiconductor devices based on GaN materials can have a higher breakdown voltage and a higher power density than conventional silicon (Si) -based power devices; and by utilizing the inherent polarization characteristic of the GaN material, a two-dimensional electron gas channel with high concentration and high electron mobility can be formed, so that the switching frequency of the silicon-based power device can be higher than that of the traditional silicon-based power device. Based on the high voltage resistance and high frequency characteristics of GaN, the AlGaN/GaN high mobility transistor (HEMT) with a planar structure has wide application requirements in the high voltage and high frequency fields.
In the field of radio frequency/millimeter wave applications, electrode quality is of considerable importance. High quality ohmic contacts can reduce conduction losses and improve gain and circuit efficiency. Due to the wide band gap material properties, optimizing ohmic contacts is particularly important for gallium nitride based devices.
The electrode with low contact resistance is usually made of a multi-layer metal combination of Ti/Al/Ni/Au, but in the annealing process of making ohmic contact, metal becomes rough, metal diffusion in a semiconductor causes metal spikes to exist under the ohmic electrode, the tips of the spikes can even penetrate into a buffer layer, and a local high electric field appears at the tips of the metal spikes, so that the electric field distribution is changed, and the device is broken down in advance.
Therefore, it is an urgent technical problem to design a semiconductor device that can achieve low contact resistance and reduce device switching loss.
Disclosure of Invention
The invention aims to provide a three-terminal semiconductor device and a manufacturing method thereof, which can reduce contact resistance and switching loss of the device.
The invention provides a technical scheme that:
a three-terminal semiconductor device includes:
a support layer;
a heterojunction disposed on the support layer;
a first electrode, a second electrode, and a gate electrode disposed on the heterojunction;
wherein at least one of the first electrode and the second electrode comprises: a doped layer disposed on the heterojunction and an electrode contact layer disposed on the doped layer.
In a preferred embodiment of the present invention, the first electrode and the second electrode each include: a doped layer disposed on the heterojunction and an electrode contact layer disposed on the doped layer.
In a preferred embodiment of the present invention, the gate electrode is used for controlling on and off between the first electrode and the second electrode, and has a structure of any one of a P-type gate structure, a metal insulator semiconductor structure, a multi-layer metal structure, or a semiconductor structure of a recessed gate.
In a preferred embodiment of the present invention, the support layer comprises one or more layers of a group iii nitride semiconductor film.
In a preferred embodiment of the present invention, the heterojunction comprises two layers of group iii nitride semiconductor films.
In a preferred embodiment of the present invention, the heterojunction includes a stacked film of AlGaN and GaN or a stacked film of AlInN and GaN.
The invention also provides a technical scheme that:
the manufacturing method of the three-terminal semiconductor device comprises the following steps:
providing a support layer;
manufacturing a heterojunction on the supporting layer;
fabricating a first electrode and a second electrode on the heterojunction, wherein at least one of the first electrode and the second electrode comprises: a doped layer disposed on the heterojunction and an electrode contact layer disposed on the doped layer;
and manufacturing a grid electrode on the heterojunction.
In a preferred embodiment of the present invention, the step of forming the first electrode and the second electrode on the heterojunction includes:
manufacturing two doping layers on the heterojunction;
and respectively manufacturing the electrode contact layers on the two doped layers.
In a preferred embodiment of the invention, the doped layer and the heterojunction have the same or opposite spontaneous polarization direction.
In a preferred embodiment of the present invention, the doped layer is doped n-type;
the polarization direction of the doped layer and the polarization direction of the heterojunction are both metal polarities, and the doped layer is prepared by adopting dry etching of plasma; or the polarization direction of the doped layer is nitrogen polarity, the polarization direction of the heterojunction is metal polarity, and the doped layer is prepared by wet etching of alkaline solution.
The three-terminal semiconductor device and the manufacturing method thereof have the beneficial effects that:
1. an electrode contact layer of at least one of the first electrode and the second electrode is arranged on the doped layer, and the contact resistance is smaller than that of the electrode contact layer which is directly manufactured on an undoped semiconductor layer; meanwhile, the influence of metal peaks is reduced, and the voltage resistance of the device is improved;
2. the doped layer is arranged on the heterojunction, the electrode contact layer can be easily obtained by a wet etching method without high-precision dry etching equipment, and the process is simple.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a three-terminal semiconductor device according to a first embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a three-terminal semiconductor device according to a second embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a three-terminal semiconductor device according to a third embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a three-terminal semiconductor device according to a fourth embodiment of the present invention.
Fig. 5 is a flowchart of a method for manufacturing a three-terminal semiconductor device according to a fourth embodiment of the invention.
Fig. 6 to 10 are schematic structural diagrams illustrating a manufacturing process of a three-terminal semiconductor device according to a fourth embodiment of the present invention.
Icon: a 100-three terminal semiconductor device; 110-a support layer; 120-heterojunction; 130-a first electrode; 140-a second electrode; 150-a gate; 160-doped layer; 170-electrode contact layer; a 180-P type doped layer; 190-a gate electrode contact layer; 200-an insulating layer; 210-a groove; 220-a layer of doped material.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like, indicate orientations or positional relationships that are based on the orientations or positional relationships shown in the drawings, or the orientations or positional relationships that the products of the present invention conventionally put into use, or the orientations or positional relationships that the persons skilled in the art conventionally understand, are only used for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the equipment or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should also be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In order to reduce the influence of the metal spike on the device, one of the prior arts is to implant silicon ions into a selective region by an ion implantation method before an ohmic electrode is manufactured, then perform thermal diffusion, and finally manufacture the metal electrode on a semiconductor with a silicon diffusion region, wherein the metal spike is wrapped by a silicon-doped region, so that the influence of the metal spike can be effectively reduced. The obvious disadvantages of this method are: additional ion implantation and thermal diffusion processes are introduced, thereby increasing the complexity of the process and the manufacturing cost. Moreover, it is not easy to implant silicon ions into GaN crystal lattice, and thermal activation and implantation damage repair of the implanted silicon ions require annealing at 1500 ℃ high temperature, nitrogen environment, and 15kbar pressure, which is very demanding on process and equipment.
First embodiment
Referring to fig. 1, the present embodiment provides a three-terminal semiconductor device 100, and the three-terminal semiconductor device 100 includes a support layer 110, a heterojunction 120, a first electrode 130, a second electrode 140, and a gate 150.
Wherein the support layer 110 includes one or more layers of group iii nitride semiconductor films.
The heterojunction 120 is disposed on the support layer 110. The heterojunction 120 comprises two layers of group iii nitride semiconductor films. The interface of the two films has high depth and high mobility of electrons or holes. Specifically, the heterojunction 120 includes a stacked film of AlGaN and GaN or a stacked film of AlInN and GaN.
The first electrode 130 and the second electrode 140 each include: a doped layer 160 disposed on the heterojunction 120, and an electrode contact layer 170 disposed on the doped layer 160. Doped layer 160 is n-type doped and doped layer 160 has a low resistivity. An electrode contact layer 170 is formed on the doped layer 160, and the electrode contact layer 170 and the doped layer 160 form a low-resistance ohmic contact.
The doped layer 160 may have the same or opposite spontaneous polarization direction as the heterojunction 120. Specifically, the polarization direction of the doped layer 160 and the polarization direction of the heterojunction 120 are both metal polarities, and the doped layer 160 is prepared by dry etching of plasma; alternatively, the polarization direction of the doped layer 160 is nitrogen polarity, the polarization direction of the heterojunction 120 is metal polarity, and the doped layer 160 is prepared by wet etching with an alkaline solution.
In other embodiments, only either one of the first and second electrodes 130 and 140 may be provided in the form of forming the electrode contact layer 170 on the doped layer 160 instead of providing both the first and second electrodes 130 and 140 in the form of forming the electrode contact layer 170 on the doped layer 160.
The gate 150 is a multi-layer metal structure, and specifically, the gate 150 is a single-layer contact layer.
The three-terminal semiconductor device 100 provided by the embodiment has the beneficial effects that:
1. the electrode contact layer 170 of the first and second electrodes 130 and 140 is disposed on the doped layer 160, and the contact resistance is smaller than that when the electrode contact layer 170 is directly formed on an undoped semiconductor layer; meanwhile, the influence of metal peaks is reduced, and the voltage resistance of the device is improved;
2. the doping layer 160 is disposed on the heterojunction 120, and the electrode contact layer 170 can be easily obtained by wet etching without using high-precision dry etching equipment, and the process is simple.
Second embodiment
Referring to fig. 2, the present embodiment provides a three-terminal semiconductor device 100, which has the same structure as the three-terminal semiconductor device 100 of the first embodiment, except that the gate 150 in the present embodiment is a P-type gate structure.
The gate 150 includes a P-type doped layer 180 disposed on the heterojunction 120 and a gate electrode contact layer 190 disposed on the P-type doped layer 180.
Third embodiment
Referring to fig. 3, the present embodiment provides a three-terminal semiconductor device 100, which has the same structure as the three-terminal semiconductor device 100 of the first embodiment, except that the gate 150 in the present embodiment is a metal insulator semiconductor structure.
The gate 150 includes an insulating layer 200 disposed on the heterojunction 120 and a gate electrode contact layer 190 disposed on the insulating layer 200.
Fourth embodiment
Referring to fig. 4, the present embodiment provides a three-terminal semiconductor device 100, which has the same structure as the three-terminal semiconductor device 100 of the first embodiment, except that the gate 150 in the present embodiment is a semiconductor structure of a recessed groove 210 gate.
The heterojunction 120 is formed with a recess 210. The gate 150 includes an insulating layer 200 disposed in the recess 210 and a gate electrode contact layer 190 disposed on the insulating layer 200 and in the recess 210.
Fifth embodiment
Referring to fig. 5, the present embodiment provides a method for manufacturing a three-terminal semiconductor device 100, wherein the gate 150 of the three-terminal semiconductor device 100 mainly refers to a P-type gate structure or a metal insulator semiconductor structure. The method for manufacturing the three-terminal semiconductor device 100 comprises the following steps:
s1: referring to fig. 6, a supporting layer 110 is provided.
S2: a heterojunction 120 is fabricated on the support layer 110.
In S1 and S2, the support layer 110 and the heterojunction 120 may be grown on a silicon substrate or a SiC substrate or a sapphire substrate using a MOCVD or MBE method.
S3: a doped layer 160 is fabricated on the heterojunction 120.
First, referring to fig. 7, a doped material layer 220 is formed on the heterojunction 120, the doped material layer 220 is doped n-type, and then, referring to fig. 8, the doped material layer 220 is selectively etched to form two doped layers 160 disposed at intervals.
The polarization direction of the doped layer 160 and the polarization direction of the heterojunction 120 are both metal polarities, and the doped layer 160 is prepared by adopting dry etching of plasma; alternatively, the polarization direction of the doped layer 160 is nitrogen polarity, the polarization direction of the heterojunction 120 is metal polarity, and the doped layer 160 is prepared by wet etching with an alkaline solution.
The pattern of the doped layer 160 may be grown on the surface of the heterojunction 120 by a selective area growth method. And can also be made by selective ion implantation and thermal diffusion.
S4: referring to fig. 9, an insulating layer 200 is formed on the heterojunction 120.
S3 and S4 may not be limited to the order, and in other embodiments, S3 may be omitted for a specific structure of the gate 150.
S5: referring to fig. 10, an electrode contact layer 170 is formed on the doped layer 160, a gate electrode contact layer 190 is formed on the insulating layer 200, and a first electrode 130, a second electrode 140 and a gate 150 are formed.
Wherein, when the insulating layer 200 is formed on the heterojunction 120, the gate 150 has a metal insulator semiconductor structure. In S4 and S5, the insulating layer 200 may be replaced by a P-type doped layer 180, and the gate 150 may be formed as a P-type gate structure when the P-type doped layer 180 is formed on the heterojunction 120.
In the manufacturing method of the present embodiment, both the first electrode 130 and the second electrode 140 are formed as the electrode contact layer 170 on the doped layer 160, but in other embodiments, only one of the first electrode 130 and the second electrode 140 may be formed as the electrode contact layer 170 on the doped layer 160.
The manufacturing method provided by the embodiment has the beneficial effects that:
1. the electrode contact layer 170 is manufactured on the n-type doped layer 160, and compared with the electrode contact layer 170 which is directly manufactured on an undoped semiconductor layer, the contact resistance is smaller, the influence of metal peaks is reduced, and the voltage resistance of the device is improved;
the n-type doped layer 160 is realized in the film growth process, rather than adopting a post-treatment method after the film growth is finished, such as ion implantation and thermal diffusion, so that the complexity of the manufacturing process is reduced;
3. the n-type doped layer 160 with nitrogen polarity is manufactured on the semiconductor film structure with gallium polarity, the pattern of the electrode contact layer 170 can be easily obtained by a wet etching method without high-precision dry etching equipment, and the process is simple.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A three-terminal semiconductor device, comprising:
a support layer (110);
a heterojunction (120) disposed on the support layer (110);
a first electrode (130), a second electrode (140), and a gate (150) disposed on the heterojunction (120);
wherein at least one of the first electrode (130) and the second electrode (140) comprises: a doped layer (160) disposed on the heterojunction (120) and an electrode contact layer (170) disposed on the doped layer (160).
2. The three-terminal semiconductor device according to claim 1, wherein the first electrode (130) and the second electrode (140) each comprise: a doped layer (160) disposed on the heterojunction (120) and an electrode contact layer (170) disposed on the doped layer (160).
3. The three-terminal semiconductor device according to claim 1, wherein the gate (150) is used for controlling the conduction and the disconnection between the first electrode (130) and the second electrode (140), and has a structure of any one of a P-type gate structure, a metal insulator semiconductor structure, a multilayer metal structure or a semiconductor structure of a groove (210) gate.
4. Three-terminal semiconductor device according to claim 1, characterized in that the support layer (110) comprises one or more layers of group iii nitride semiconductor films.
5. The three-terminal semiconductor device according to claim 1, wherein said heterojunction (120) comprises two layers of group-ill nitride semiconductor films.
6. The three-terminal semiconductor device according to claim 5, wherein the heterojunction (120) comprises a stacked film of AlGaN and GaN or a stacked film of AlInN and GaN.
7. A method for manufacturing a three-terminal semiconductor device is characterized by comprising the following steps:
providing a support layer (110);
-fabricating a heterojunction (120) on the support layer (110);
fabricating a first electrode (130) and a second electrode (140) on the heterojunction (120), wherein at least one of the first electrode (130) and the second electrode (140) comprises: a doped layer (160) disposed on the heterojunction (120) and an electrode contact layer (170) disposed on the doped layer (160);
a gate (150) is fabricated on the heterojunction (120).
8. The method of fabricating a three-terminal semiconductor device according to claim 7, wherein the step of fabricating a first electrode (130) and a second electrode (140) on the heterojunction (120) comprises:
-fabricating two of said doped layers (160) on said heterojunction (120);
and respectively manufacturing the electrode contact layers (170) on the two doped layers (160).
9. The method of fabricating a three-terminal semiconductor device according to claim 7, wherein said doped layer (160) and said heterojunction (120) have the same or opposite spontaneous polarization direction.
10. The method of claim 9, wherein said doped layer (160) is doped n-type;
the polarization direction of the doped layer (160) and the polarization direction of the heterojunction (120) are both metal polarities, and the doped layer (160) is prepared by adopting dry etching of plasma; or the polarization direction of the doped layer (160) is nitrogen polarity, the polarization direction of the heterojunction (120) is metal polarity, and the doped layer (160) is prepared by wet etching of alkaline solution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911218758.1A CN110993688A (en) | 2019-12-03 | 2019-12-03 | Three-terminal semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911218758.1A CN110993688A (en) | 2019-12-03 | 2019-12-03 | Three-terminal semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110993688A true CN110993688A (en) | 2020-04-10 |
Family
ID=70089579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911218758.1A Pending CN110993688A (en) | 2019-12-03 | 2019-12-03 | Three-terminal semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110993688A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112599412A (en) * | 2020-11-24 | 2021-04-02 | 上海工程技术大学 | Preparation method of breakdown-preventing gallium nitride-based power device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050082568A1 (en) * | 2003-06-10 | 2005-04-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2007317794A (en) * | 2006-05-24 | 2007-12-06 | Mitsubishi Electric Corp | Semiconductor device, and its manufacturing method |
| CN104704615A (en) * | 2012-09-28 | 2015-06-10 | 夏普株式会社 | Switching element |
| CN107230709A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | AlGaN/GaN MIS-HEMT preparation method |
| CN110429132A (en) * | 2019-08-16 | 2019-11-08 | 广东省半导体产业技术研究院 | Gate structure, the manufacturing method of gate structure and enhanced semiconductor device |
-
2019
- 2019-12-03 CN CN201911218758.1A patent/CN110993688A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050082568A1 (en) * | 2003-06-10 | 2005-04-21 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2007317794A (en) * | 2006-05-24 | 2007-12-06 | Mitsubishi Electric Corp | Semiconductor device, and its manufacturing method |
| CN104704615A (en) * | 2012-09-28 | 2015-06-10 | 夏普株式会社 | Switching element |
| CN107230709A (en) * | 2016-03-25 | 2017-10-03 | 北京大学 | AlGaN/GaN MIS-HEMT preparation method |
| CN110429132A (en) * | 2019-08-16 | 2019-11-08 | 广东省半导体产业技术研究院 | Gate structure, the manufacturing method of gate structure and enhanced semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112599412A (en) * | 2020-11-24 | 2021-04-02 | 上海工程技术大学 | Preparation method of breakdown-preventing gallium nitride-based power device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9029916B2 (en) | Gallium nitride based semiconductor devices and methods of manufacturing the same | |
| US8697581B2 (en) | III-nitride semiconductor device with trench structure | |
| EP3284107B1 (en) | Iii-nitride transistor with trench gate | |
| KR102055839B1 (en) | Nitride based semiconductor device | |
| CN113380623A (en) | Method for realizing enhanced HEMT (high Electron mobility transistor) through p-type passivation | |
| CN113725296B (en) | Nitride semiconductor epitaxial lamination structure and power element thereof | |
| JP2013504889A (en) | Semiconductor structure | |
| CN109545850A (en) | Semiconductor device and method for manufacturing the same | |
| US20150123139A1 (en) | High electron mobility transistor and method of manufacturing the same | |
| CN108258035B (en) | GaN-based enhanced field effect device and manufacturing method thereof | |
| CN111192928B (en) | Vertical GaN Schottky device structure with high breakdown voltage and low reverse leakage | |
| CN220065702U (en) | Enhancement mode HEMT device | |
| TW201709512A (en) | Semiconductor cell | |
| JP2019506740A (en) | Schottky barrier rectifier | |
| TWI569439B (en) | Semiconductor cell | |
| JP2021533556A (en) | External electric field termination structure to improve the reliability of high voltage and high power active devices | |
| CN110993688A (en) | Three-terminal semiconductor device and manufacturing method thereof | |
| KR20130082307A (en) | Substrate structure, semiconductor device fabricated from the same and fabricating method thereof | |
| CN111933709A (en) | Nitride device with high reliability and preparation method thereof | |
| CN110970499B (en) | GaN-based transverse super-junction device and manufacturing method thereof | |
| CN212182338U (en) | Semiconductor structure | |
| CN108352408A (en) | The manufacturing method of semiconductor device, electronic unit, electronic equipment and semiconductor device | |
| CN107706238A (en) | HEMT device and its manufacture method | |
| CN110444597B (en) | Semiconductor device and method for manufacturing the same | |
| US20240154030A1 (en) | Semiconductor structures and manufacturing methods therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200410 |