JP4102955B2 - Semiconductor memory device and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device including an electrically rewritable and erasable nonvolatile memory having a data protection function, and a test method thereof.
[0002]
[Background Art and Problems to be Solved by the Invention]
In a computer system including a semiconductor memory device having an electrically rewritable and erasable nonvolatile memory such as a flash EEPROM, programs and data stored in the flash EEPROM are protected as a system. For example, it is protected from unauthorized access by a third party by an access restriction function by the operating system.
[0003]
However, when the semiconductor memory device is taken out from the computer system, there is a problem that unauthorized access by a third party is easily allowed because the protection as the system does not work.
[0004]
Since it is desirable to protect the stored data even if the semiconductor storage device is taken out from the system, the inventor of the present application can protect data and programs stored in the semiconductor storage device alone from the system. Developed semiconductor memory devices.
[0005]
Specifically, a password storage area that can be arbitrarily set by the user is provided in the non-volatile storage area, and only access commands that specify a password that matches the password stored in the password storage area can be executed. Data protection is realized.
[0006]
However, it is difficult to specify and manufacture data stored in each memory cell in the password storage area of the semiconductor storage device. Therefore, since it is unclear what data is set in the password storage area of the semiconductor memory device immediately after manufacture, it becomes a problem how to perform the test.
[0007]
In addition, when an access form that can be used only at the time of testing is provided, it is necessary to devise measures to prevent unauthorized access using the access form after product shipment.
[0008]
Thus, handling and protection of passwords including the manufacturing process becomes a problem.
[0009]
The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide an electrically rewritable non-volatile semiconductor memory capable of protecting data stored by itself even by itself. It is to provide an apparatus and a test method thereof.
[0010]
[Means for Solving the Problems]
The present invention relates to a semiconductor memory device including an electrically rewritable and erasable nonvolatile memory, an electrically rewritable nonvolatile password storage area, and a password corresponding to an operation request signal for the semiconductor memory device And a data protection circuit for preventing the operation requested by the operation request signal when the data does not match the password data stored in the password storage area.
[0011]
The nonvolatile memory that can be electrically rewritten and erased is, for example, a flash EEPROM. Therefore, the semiconductor memory device in the present invention includes, for example, a flash EEPROM having a built-in data protection function.
[0012]
The data erasure of the nonvolatile memory is, for example, a case where data is erased by flashing over.
[0013]
The password data corresponding to the request signal is password data received together with the request signal when the password data is received for each request signal. If the password data set in the register etc. at any time prior to the request signal is commonly applied to the operation request signal received thereafter, the password data set in the register etc. is requested at any time Password data corresponding to the signal.
[0014]
The operation request signal for the semiconductor memory device is, for example, a signal for requesting at least one of access and erase to the nonvolatile memory.
[0015]
The operation requested by the operation request signal is, for example, an operation related to access to a nonvolatile storage area such as a nonvolatile memory or a password storage area or data erasure.
[0016]
The password storage area may be provided in a memory cell array unit configured by the nonvolatile memory, or may be provided as a nonvolatile storage area that can be electrically rewritten in the data protection circuit.
[0017]
When the password data received in response to the operation request signal does not match the password data stored in the nonvolatile password storage area, the semiconductor memory device of the present invention has the nonvolatile memory and the nonvolatile password storage. Access to the area and data erasure can be prevented.
[0018]
Moreover, the data in the nonvolatile memory is protected from unauthorized access and unauthorized data erasure by a protection circuit and a password storage area provided in the semiconductor memory device. Therefore, even when the semiconductor memory device is taken out from the system or the like, data in the nonvolatile memory can be protected from unauthorized access and data erasure.
[0019]
The password storage area of the present invention is provided in a part of a memory cell array composed of a nonvolatile memory that can be electrically rewritten and erased.
[0020]
The semiconductor storage device of the present invention includes an electrically rewritable non-volatile unauthorized access allowable number storage area, and the password data corresponding to the operation request signal and the password data stored in the password storage area are continuous. The data in the nonvolatile memory is erased when the number of mismatches exceeds the unauthorized access allowable number data stored in the unauthorized access allowable number storage area.
[0021]
If unlimited access is possible, all combinations with a limited number of bits can be tried, and the data protection function using passwords will be ineffective.
[0022]
However, according to the present invention, when the number of password mismatches exceeds the set number of allowable unauthorized accesses, the data in the nonvolatile memory can be erased. Unauthorized access can be prevented.
[0023]
The circuit for counting the number of mismatches is preferably configured to clear the count value when the passwords match. In this way, the number of mismatches that occur continuously can be counted.
[0024]
The unauthorized access allowable number is preferably set according to the number of bits in the password storage area or the number of bits of the set password.
[0025]
The semiconductor memory device of the present invention includes an electrically rewritable nonvolatile unauthorized access count permission bit storage area, and operates when no bits representing permission are stored in the unauthorized access count permission bit storage area. The data in the non-volatile memory even when the number of consecutive mismatches between the password data corresponding to the request signal and the password data stored in the password storage area exceeds the unauthorized access allowable number of times data stored in the unauthorized access allowable number of times storage area It is characterized in that no erasure is performed.
[0026]
According to the present invention, when a bit indicating non-permission is stored in the unauthorized access count permission bit storage area, the data in the nonvolatile memory is not erased regardless of the number of consecutive unauthorized accesses.
[0027]
Therefore, it is possible to meet the needs of users who want to protect data to some extent but do not want to erase the data in non-volatile memory, and when the number of bits in the password area is large or all combinations of passwords for unauthorized access This is convenient when it is not necessary to consider the case of being tried.
[0028]
The data protection circuit of the semiconductor memory device according to the present invention includes a comparison circuit for comparing whether or not password data corresponding to the operation request signal matches password data stored in a password storage area, If the results match, the nonvolatile memory and a circuit that outputs an access permission signal that permits access to the nonvolatile storage area and data erasure, and when the access permission signal is received, The operation content requested by the operation request signal is executed.
[0029]
Here, the nonvolatile storage area means any one of a password storage area, an unauthorized access allowable number storage area, and an unauthorized access count permission bit storage area.
[0030]
The data protection circuit of the semiconductor memory device of the present invention includes a circuit that counts the number of mismatches based on the comparison result of the comparison circuit, and an illegal number in which the number of mismatches counted continuously is stored in the unauthorized access allowable number storage area. And a circuit for erasing the data in the nonvolatile memory when the allowable access count is exceeded.
[0031]
The semiconductor memory device of the present invention includes an I / O pad that is not output as a package terminal, and when a first level voltage is applied to the I / O pad, a password corresponding to the operation request signal. Regardless of whether or not the data matches the password data stored in the password storage area, access to the nonvolatile memory and the nonvolatile storage area is permitted.
[0032]
Here, the nonvolatile storage area means any one of a password storage area, an unauthorized access allowable number storage area, and an unauthorized access count permission bit storage area.
[0033]
The I / O pads that are not output as package terminals include, for example, I / O pads that are on the wafer and are not bonded. A terminal connected to the I / O pad can be applied with an external voltage at the wafer stage, but cannot be externally input after packaging.
[0034]
In general, it is difficult to identify and manufacture data stored in each memory cell of a password storage area of a semiconductor storage device, so what data is set in the password storage area of a semiconductor storage device immediately after manufacture. It is unclear and it is difficult to test.
[0035]
However, according to the present invention, since the first level voltage can be applied to the I / O pad via the terminal connected to the I / O pad in the wafer test stage, the password data can be used in the wafer test stage. It is possible to perform an operation test without any problems.
[0036]
In the semiconductor memory device of the present invention, when the first level voltage is applied to the I / O pad, the password data corresponding to the request signal is the password data stored in the password storage area. And a circuit for outputting the access permission signal regardless of whether or not they match.
[0037]
According to another aspect of the semiconductor memory device of the present invention, a terminal connected to the I / O pad that is not output as a package terminal is supplied with a pull-up terminal or a pull-down terminal for supplying a second level voltage different from the first level. It is configured as a terminal.
[0038]
If the terminal of the I / O pad is at a voltage of a second level different from the first level, the nonvolatile memory is accessed if it does not match the password data stored in the password storage area. It becomes impossible.
[0039]
Therefore, after packaging, only when the passwords match, the nonvolatile memory and the nonvolatile area can be accessed and data can be erased, and data protection is possible.
[0040]
The present invention provides a test method for a semiconductor memory device as described above, wherein the first level voltage is applied to the I / O pad during the test of the semiconductor memory device, so that the wafer level of the semiconductor memory device is increased. It is characterized by performing an operation test.
[0041]
However, according to the present invention, since the first level voltage can be applied to the I / O pad via the terminal connected to the I / O pad in the wafer test stage, the password data can be used in the wafer test stage. It is possible to perform an operation test without any problems.
[0042]
According to the test method of the present invention, given password data is set in the password storage area by applying the voltage of the first level to the I / O pad before the package of the semiconductor storage device. The operation test at the package stage is performed using the given password data after the package.
[0043]
By using a given password set at the wafer test stage, it becomes possible to access the nonvolatile memory and the nonvolatile area after packaging, and an operation test at the package stage can be performed.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0045]
FIG. 1 is a diagram for explaining an example of the configuration of the semiconductor memory device of this embodiment.
[0046]
The semiconductor memory device 100 includes a memory cell array 110 (nonvolatile memory) composed of a plurality of nonvolatile memory cells, an X decoder 120, a Y decoder 130, a sense amplifier 140, an output buffer 150, an input buffer 160, and a control circuit 170. .
[0047]
Here, the memory cell array 110 includes a password storage area 112, an unauthorized access allowable number storage area 114, and an unauthorized access count permission bit storage area 116. In this embodiment, when the password data received together with the operation request signal for requesting at least one of access and erasure coincides with the password data stored in the password storage area 112, the memory cell array can be accessed.
[0048]
The control circuit 170 controls the X decoder 120, the Y decoder 130, the sense amplifier 140, the output buffer 150, and the input buffer 160 based on a signal or a control signal requesting at least one of access and erasure to the memory cell array 110 from the outside. Do.
[0049]
Here, the control circuit 170 includes a data protection circuit 200. The data protection circuit 200 is a circuit for performing control necessary for protecting data stored in the memory cell array 110 from unauthorized access from the outside.
[0050]
For example, a comparison circuit for detecting whether or not the password data received together with the operation request signal matches the password data stored in the password storage area 112 provided in a part of the memory cell array 110, and the comparison circuit If the comparison results match, a circuit that outputs an access permission signal for permitting access to the memory cell array 110 may be included.
[0051]
In addition, a circuit that counts the number of mismatches based on the comparison result of the comparison circuit, and the data of the memory cell array when the continuously counted number of mismatches exceeds the unauthorized access permission number stored in the unauthorized access permission number storage area And a circuit for erasing data.
[0052]
In the semiconductor memory device of this embodiment, the password storage area 112 is provided on the memory cell array 110, and the semiconductor memory device itself is provided with a data protection circuit. It is possible to protect data against.
[0053]
Here, since it is difficult to specify and manufacture data stored in each memory cell of the password storage area 112 of the semiconductor memory device, the following measures are taken in this embodiment. That is, when an I / O pad that is not output as a package terminal and a first level voltage is applied to the I / O pad, the password data received together with the operation request signal is a part of the memory cell array 110. Regardless of whether or not the password data matches the password data stored in the password storage area, the circuit for outputting the access permission signal is included.
[0054]
FIG. 2 is a diagram for explaining an example of the configuration of the data protection circuit of this embodiment.
[0055]
A password setting register 210 is set to the same value as the password data stored in the password storage area 112 of the memory cell array 110.
[0056]
Reference numeral 220 denotes access password data which is input together with command data for each access.
[0057]
A comparison circuit 230 compares the value set in the password setting register 210 with the inputted access password data 220 and outputs a password match signal 232.
[0058]
Reference numeral 240 denotes an I / O pad connected to an access permission terminal 242 that is not output as a package terminal. The access permission terminal 242 is pulled up or pulled down at the time of shipment.
[0059]
An OR circuit 250 receives the password match signal 232 and the signal 244 from the access permission terminal and outputs an access permission signal 252.
[0060]
Here, it is assumed that access to the memory cell array is permitted when the access permission signal is at H level, and the password match signal is at H level when the passwords match. In this case, it is preferable to pull down the access permission terminal 242 so as to apply an H level voltage in the wafer test stage.
[0061]
In this way, at the wafer test stage, the signal 244 from the access permission terminal is always at H level, and the access permission signal 252 is at H level regardless of whether the password match signal 232 is at H level or L level. Since the signal 244 from the pulled-down access permission terminal is always at the L level after packaging, the access permission signal 252 is at the H level only when the password match signal 232 is at the H level.
[0062]
Therefore, in the wafer test stage, access is permitted regardless of whether the passwords match, and after the package, access is permitted only if the passwords match.
[0063]
Reference numeral 270 denotes an unauthorized access allowable number register in which a value stored in the unauthorized access allowable number storage area is set. The unauthorized access allowable number is the number of times unauthorized access that does not match the password set in the password storage area is permitted. In the present embodiment, if unauthorized accesses exceeding the unauthorized access allowable number occur continuously, the data in the memory cell array can be erased.
[0064]
The unauthorized access allowable number is preferably set according to the number of bits in the password storage area or the number of bits of the password to be set. The number of combinations that can be specified is determined based on the number of bits. If unauthorized access is permitted for more than this number of combinations, all combinations can be tried, and as a result, unauthorized access is permitted.
[0065]
Reference numeral 280 denotes an unauthorized access permission bit, and a value stored in the unauthorized access permission bit storage area is set. The unauthorized access permission bit 280 is a bit for designating whether or not data in the memory cell array is to be erased when unauthorized accesses exceeding the permitted number of unauthorized access occur continuously. For example, when the relevant bit is ON, the data It is possible to prevent the erasure of the image.
[0066]
An unauthorized access count circuit 260 receives the password match signal 232 that is output from the comparison circuit 230 and counts the number of unauthorized accesses. The counted value is held in the unauthorized access count register 262. Since the number of times that unauthorized access has occurred continuously becomes a problem, the value of the unauthorized access count register is cleared when the password match signal indicates password match.
[0067]
The unauthorized access count circuit 260 compares the value of the unauthorized access count register 262 with the value of the unauthorized access allowable number register 270 and a circuit that outputs the erase signal 264 based on the comparison result and the value of the unauthorized access permission bit 280. Including. The erase signal 264 is a signal for instructing erasure of data in the memory cell array when the number of consecutive unauthorized accesses exceeds the set number of unauthorized accesses.
[0068]
As a result, if the unauthorized access permission bit 280 is not turned ON, if the value of the unauthorized access count register 262 exceeds the value of the unauthorized access allowable number register 270, an instruction to erase data in the memory cell array is issued. An erase signal is output.
[0069]
FIG. 3 is a flowchart for explaining the test method of the present embodiment.
[0070]
During the wafer test, the access permission terminal is set to the H level and the memory test is performed (step S10). In this way, since the memory cell array can be accessed regardless of the password, the operation of each memory cell can be confirmed at the wafer stage.
[0071]
If the test at the wafer stage is OK, the temporary password is written in the password storage area for assembly. In the assembly process, the pulled-down access permission terminal is not output as a package terminal (steps S20 and S30).
[0072]
If the assembly is OK, the memory test is performed in the package test using the temporary password designated before the assembly (steps S40 and S50).
[0073]
If the package test is OK, the temporary password designated at the time of the test is specified and shipped (steps S60 and S70).
[0074]
FIG. 4 is a flowchart for explaining a user use example of the present embodiment.
[0075]
The user can write data into the memory cell array using the temporary password specified at the time of shipment (step S110).
[0076]
First, a new password dedicated to the user is written in the non-volatile password storage area using the temporary password (step S120). Since the new password is applied at the time of writing, the next instruction to the semiconductor memory device is performed using the new password.
[0077]
Next, using the new password, the unauthorized access allowable number is written into the nonvolatile unauthorized access allowable number storage area (step S130).
[0078]
Next, ON / OFF of the unauthorized access permission bit is written in the unauthorized access permission bit storage area using the new password (step S140).
[0079]
Then, the semiconductor memory device is incorporated into the product (step S150).
[0080]
In addition, this invention is not limited to this embodiment, A various deformation | transformation implementation is possible within the range of the summary of this invention.
[0081]
In this embodiment, the case where the password storage area, the unauthorized access allowable number storage area, and the unauthorized access count permission bit storage area are provided in the nonvolatile memory cell array is described as an example, but the present invention is not limited to this. For example, an electrically rewritable nonvolatile storage area may be provided in the data protection circuit.
[0082]
In this embodiment, the case where password data corresponding to the request signal is input for each access has been described as an example, but the present invention is not limited to this. For example, password data set in a register or the like at an arbitrary time prior to a request signal may be commonly applied to an operation request command received thereafter.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an example of a configuration of a semiconductor memory device according to an embodiment;
FIG. 2 is a diagram for describing an example of a configuration of a data protection circuit of an embodiment;
FIG. 3 is a flowchart for explaining a test method of the present embodiment.
FIG. 4 is a flowchart for explaining a user use example of the present embodiment;
[Explanation of symbols]
100 Semiconductor memory device 110 Memory cell array 112 Password storage area 114 Unauthorized access allowable number storage area 116 Unauthorized access count permission bit storage area 120 X decoder 130 Y decoder 140 Sense amplifier 150 Output buffer 160 Input buffer 170 Control circuit 200 Data protection circuit 210 Password Setting register 220 Access password data 230 Comparison circuit 232 Password match signal 240 I / O pad 242 Access permission terminal 244 Signal 250 from access permission terminal OR circuit 252 Access permission signal 260 Unauthorized access count circuit 262 Unauthorized access count register 264 Erase Signal 270 Unauthorized access allowable number register 280 Unauthorized access permission bit

Claims (9)

A semiconductor memory device including a nonvolatile memory that can be electrically rewritten and erased,
An electrically rewritable non-volatile password storage area;
An electrically rewritable non-volatile unauthorized access allowable storage area,
A data protection circuit for preventing the operation requested by the operation request signal when the password data corresponding to the operation request signal for the semiconductor memory device does not match the password data stored in the password storage area When,
I / O pads that are not output as package terminals ,
If the number of consecutive mismatches between the password data corresponding to the operation request signal and the password data stored in the password storage area exceeds the unauthorized access allowable number of times data stored in the unauthorized access allowable number storage area, the nonvolatile data Erase data in the memory ,
When a first level voltage is applied to the I / O pad, regardless of whether the password data corresponding to the operation request signal matches the password data stored in the password storage area. A semiconductor memory device, wherein access to the nonvolatile memory and the nonvolatile storage area is permitted . In claim 1,
The semiconductor memory device, wherein the password storage area is provided in a part of a memory cell array composed of a nonvolatile memory that can be electrically rewritten and erased. In either claim 1 or 2,
Including an electrically rewritable nonvolatile unauthorized access count permission bit storage area,
When a bit indicating permission is not stored in the unauthorized access count permission bit storage area, the number of consecutive mismatches between the password data corresponding to the operation request signal and the password data stored in the password storage area is the unauthorized access count. A semiconductor memory device, wherein data in the nonvolatile memory is not erased even when the unauthorized access allowable number of times data stored in the allowable number of times storage area is exceeded. In any one of Claims 1 thru | or 3,
The data protection circuit is:
A comparison circuit for comparing whether or not the password data corresponding to the operation request signal matches the password data stored in the password storage area;
If the comparison results match, the nonvolatile memory and a circuit that outputs an access permission signal for permitting access to the nonvolatile storage area and data erasure,
When the access permission signal is received, the operation content requested by the operation request signal is executed. In claim 4,
The data protection circuit is:
A circuit for counting the number of mismatches based on the comparison result of the comparison circuit;
And a circuit for erasing data in the non-volatile memory when the number of mismatches counted continuously exceeds the allowable number of unauthorized accesses stored in the unauthorized access allowable number storage area. In any one of Claims 1 thru | or 5 ,
When a first level voltage is applied to the I / O pad, regardless of whether the password data corresponding to the request signal matches the password data stored in the password storage area. A circuit for outputting the access permission signal;
A semiconductor memory device comprising: In any one of Claims 1 thru | or 6 .
A terminal connected to the I / O pad that is not output as a package terminal is configured as a pull-up terminal or a pull-down terminal for supplying a second level voltage different from the first level. Semiconductor memory device. A claims 1 to 7 test method of the semiconductor memory device according,
A test method for a semiconductor memory device, comprising: performing an operation test at a wafer stage of the semiconductor memory device by applying the first level voltage to the I / O pad during the test of the semiconductor memory device. In claim 8 ,
Setting given password data in the password storage area by applying the first level voltage to the I / O pad before packaging the semiconductor memory device;
A test method for a semiconductor memory device, comprising: performing an operation test at a package stage using the given password data after packaging of the semiconductor memory device.

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