JP4091283B2 - Thin film transistor manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a bottom gate thin film transistor, a liquid crystal display device using the bottom gate thin film transistor, and a method for manufacturing an organic EL device.
[0002]
[Prior art]
Thin film transistors (TFTs) are used as switching elements in active matrix liquid crystal display devices, active matrix organic EL display devices, and the like. Thin film transistors are roughly classified into bottom gate type and top gate type because of their structure. Of these, bottom gate type thin film transistors are provided with a gate electrode under the active layer, and are more reliable than top gate type thin film transistors. ing. Regarding the structure of the bottom gate type thin film transistor, for example, “'99 latest liquid crystal process technology” (published in Press Journal 1998, pp 53-59), “flat panel display 1999” (Nikkei Business Publications, 1998, pp 132- pp139) and JP-A-8-279618.
[0003]
FIG. 6 shows a schematic cross-sectional view of one embodiment of a liquid crystal display device using a bottom-gate thin film transistor, and FIGS. 7 and 8 show manufacturing steps of the liquid crystal display device.
[0004]
In this manufacturing process, first, the gate electrode 2 is formed on the transparent glass substrate 1 with a thickness of about 200 nm using a metal such as Cr, Al, Mo, Ta or the like. Similarly, the Cs electrode 3 is formed (FIG. 7A).
[0005]
On the gate electrode 2, as the gate insulating film 6, for example, a silicon nitride film 4 is stacked with a thickness of 50 nm and a silicon oxide film 5 is stacked with a thickness of 150 nm. After the gate insulating film 6 is stacked, an amorphous silicon film is subsequently stacked by 50 nm. Thereafter, the amorphous silicon film is crystallized by a technique such as thermal annealing or laser annealing using an infrared lamp to form a polysilicon film 7 (FIG. 7B).
[0006]
Next, a protective insulating film 8 made of silicon oxide is formed to a thickness of 200 nm (FIG. 7C), a resist is formed on the protective insulating film 8, and the gate electrode 2 is exposed from the back surface using the gate electrode 2 as a mask. A resist is patterned on the channel formation portion self-aligned with the gate electrode, and the protective insulating film 8 is removed by etching using the resist as a mask to leave the protective insulating film 8 in the channel formation portion self-aligned with the gate electrode 2 (FIG. 7D). )). Usually, hydrofluoric acid wet etching or fluorine dry etching is used for this etching.
[0007]
Next, using the protective insulating film 8 made of silicon oxide as a mask, ions of phosphorus, arsenic, etc. are implanted to form LDD (lightly doped drain) regions 9 (FIG. 7E), and then N-channel source / drain implantation is performed. A resist mask (SD implantation mask) 11 is formed of a resist or the like, and then protection is performed on the polysilicon film 7 in the source / drain region (SD region) and the auxiliary capacitance region formed by the polysilicon film 7 and the gate electrode 2. The insulating film 8 is removed by hydrofluoric acid wet etching or fluorine dry etching (FIG. 7F). Thereafter, an N-channel source / drain region (SD region) 10 is formed by implanting high-concentration phosphorus, arsenic, or the like. Further, in order to activate the implanted dopant such as phosphorus, thermal annealing or laser annealing is performed, and the polysilicon film 7 in the non-implanted portion of the dopant is used as an active layer to obtain the TFT 100 (FIG. 7G).
[0008]
Next, a resist is formed on the portion of the substrate 1 where the TFT 100 is formed, and an unnecessary portion of the protective insulating film and the polysilicon film 7 are patterned (FIG. 8H). Also in this case, hydrofluoric acid-based wet etching or fluorine-based dry etching is usually used for etching the protective insulating film. For the etching of the polysilicon film 7, F-based or Cl-based dry etching is often used.
[0009]
Next, in order to form the interlayer insulating film 13, a silicon nitride film 14 (300 nm) and a silicon oxide film 15 (200 nm) are successively formed (FIG. 8 (i)).
[0010]
The interlayer insulating film 13 and the gate insulating film 6 are removed by etching at a contact formation portion on the polysilicon film 7 and a contact formation portion (not shown) on the gate electrode 2 to form a contact hole 16 (FIG. 8 ( j)). Then, a source electrode 17 and a drain electrode 18 are formed by embedding a metal such as Al in the contact hole 16 (FIG. 8 (k)).
[0011]
Next, a flattening film 19 such as an organic flattening film or a silicon nitride flattening film is formed in a region excluding a portion for forming a contact with the transparent electrode and a pad forming portion of the liquid crystal display panel, and then a pixel portion. A transparent electrode 20 such as ITO is formed so as to cover the transparent electrode 20, and an alignment film 21 is formed on the transparent electrode 20. Thus, a TFT substrate 201 for a liquid crystal display device is formed (FIG. 8L).
[0012]
The liquid crystal display device 200 of FIG. 6 forms a panel structure from the TFT substrate 201 formed as described above, the counter substrate 203 provided with the counter electrode 202, and the liquid crystal 204 held therebetween. Is obtained.
[0013]
[Problems to be solved by the invention]
In the structure of the TFT 100 used in the conventional liquid crystal display device shown in FIGS. 6 to 8, the auxiliary capacitor is composed of a polysilicon film 7 doped with phosphorus or the like at a high concentration and the Cs electrode 3 (the same layer as the gate electrode 2). However, the protective insulating film 8 on the polysilicon film 7 must be removed by etching twice in order to form the shape (FIGS. 7D and 7F). This complicates the process and hinders productivity improvement.
[0014]
In the region where the protective insulating film 8 is removed by etching at the first time (FIG. 7D), the polysilicon film 7 is exposed from the initial stage of etching in the step of performing the second etching removal of the protective insulating film 8. (FIG. 7 (f)). On the other hand, at this time, the polysilicon film 7 is formed with the N-channel LDD region 9 by ion implantation of phosphorous, arsenic, etc., so that it is eroded by an alkaline resist stripping solution or a hydrofluoric acid etching solution. As a result, pinholes and the like are likely to occur. For this reason, the polysilicon film 7 in this portion and the gate insulating film 6 (particularly the silicon oxide film 5) therebelow are etched with a hydrofluoric acid-based etchant, and the polysilicon film 7 and the Cs electrode 3 (or the gate electrode 2). ), The withstand voltage of the gate insulating film 6 decreases.
[0015]
The present invention is intended to solve the above-mentioned problems of the prior art, and in the bottom gate type TFT, it is possible to improve the productivity by reducing the manufacturing process and prevent the breakdown voltage of the gate insulating film. The goal is to improve product yield.
[0016]
[Means for Solving the Problems]
  In order to achieve this object, the present invention provides (1) a step of forming a gate electrode on a substrate, (2) a step of forming a gate insulating film on the gate electrode, in order to manufacture a bottom gate type thin film transistor. (3) A step of forming a laminate in which an active layer precursor film and a protective insulating film are laminated on a gate insulating film, and the protective insulating film has a thickness of 100 nm or less, (4)The protective insulating film is left on the LDD region or the source / drain region without being etched.A step of implanting a dopant into the LDD region or the source / drain region of the active layer precursor film through the protective insulating film, (5) a step of activating the implanted dopant and making the dopant non-implanted portion an active layer, (6) the protection All or part of the insulation filmTreatment to clean the surface of the protective insulating film and remove or repair defects in the protective insulating filmProcess, (7)processingForming an interlayer insulating film on the protective insulating film, and (8) forming a source / drain electrode on the interlayer insulating film.
[0017]
  Preferably,Step (6)Water containing oxidizing additivesWith the outer protective insulation filmWashingThen, the surface of the protective insulating film is cleaned and defects in the protective insulating film are removed or repaired.. In this case, the oxidizing additive is one kind or several kinds of ozone, hydrogen peroxide solution, sulfuric acid, nitric acid, and carbonic acid. or,Step (6)Below the temperature that does not cause distortion to the substrateThe protective insulating filmHeat treatmentClean the surface of the protective insulating film and remove or repair defects in the protective insulating film.You can also. In this case, the heat treatment is performed in an atmosphere containing oxygen. Alternatively, the heat treatment is performed in an atmosphere containing water vapor. or,Step (6)Atmosphere containing oxygenThe protective insulation filmPlasma treatmentClean the surface of the protective insulating film and remove or repair defects in the protective insulating film.It may be. For example,Step (6)Performed by plasma treatment in a dinitrogen monoxide atmosphere.
[0018]
Preferably, the active layer is made of a polysilicon film. In this case, in step (3), an amorphous silicon film is formed on the gate insulating film, the amorphous silicon film is crystallized to form a polysilicon film, and a protective insulating film is formed on the polysilicon film with a film thickness of 100 nm or less. To do. Alternatively, in step (3), an amorphous silicon film may be formed on the gate insulating film, a protective insulating film may be continuously formed on the amorphous silicon film, and then the amorphous silicon film may be crystallized to form a polysilicon film. . In step (3), an amorphous silicon film is formed on the gate insulating film, and the amorphous silicon film is surface oxidized to form a protective insulating film on the surface of the amorphous silicon film, and then the amorphous silicon film is crystallized. It can also be made into a polysilicon film.
[0019]
In the manufacturing process of the conventional bottom gate type TFT, the present inventors set the protective insulating film formed to a film thickness of about 200 nm to 100 nm or less, and when forming the LDD region or the source / drain region thereafter, the protective insulating film It has been found that by injecting the dopant through the protective film, the etching process of the protective insulating film can be reduced, and the problem of defective breakdown voltage of the gate insulating film can be solved. Furthermore, it has been found that such a TFT manufacturing method can be applied to a liquid crystal display device or an organic EL device driven by the TFT.
[0020]
  By the way, in the manufacturing method of the present invention described above, the interface of the protective insulating film that greatly affects the element characteristics and reliability of the thin film transistor (TFT) is very close to the active layer. Therefore, depending on the state of the interface of the protective insulating film, there is a possibility that a change in element characteristics or the like may occur when long-term driving is performed. For example, there is a possibility that a threshold voltage shift due to hot carrier trapping or a change in resistance value of the LDD region may occur. Therefore, in the present invention, particularly immediately before forming the interlayer insulating film on the protective insulating film, the protective insulating filmProcessA measure is taken to improve the reliability of the TFT.thisThe contents of the treatment are roughly classified into surface cleaning of the protective insulating film and removal of defects by introducing oxygen into the protective insulating film.thisBy performing the treatment, it is possible to ensure long-term reliability of the thin film transistor.Hereinafter, this process may be referred to as a reforming process in the present specification.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. In each figure, the same numerals indicate the same or equivalent components.
[0022]
FIG. 1 is a schematic cross-sectional view of an embodiment of a liquid crystal display device using a bottom-gate thin film transistor of the present invention, and FIGS. 2 and 3 are manufacturing process diagrams thereof.
[0023]
In the manufacturing method of this aspect, (1) the step of forming a gate electrode on the substrate and (2) the step of forming a gate insulating film on the gate electrode can be the same as the above-described conventional manufacturing method. . That is, first, in the step (1), the gate electrode 2 is formed to 10 to 400 nm on the transparent glass substrate 1 using a metal such as Cr, Al, Mo, and Ta. The gate electrode 2 may be oxidized as necessary, and an insulating layer functioning as a part of the gate oxide film may be formed on the gate electrode 2. Similarly, the Cs electrode 3 is formed (FIG. 2A).
[0024]
In step (2), as the gate insulating film 6, for example, a silicon nitride film 4 is laminated by 10 to 100 nm by a plasma CVD method, and a silicon oxide film 5 is laminated by 50 to 200 nm by a plasma CVD method on the gate electrode 2 ( FIG. 2 (B)). The silicon nitride film 4 and the silicon oxide film 5 may be formed by an ECR-CVD method, a thermal CVD method, or the like.
[0025]
In the manufacturing method of this aspect, step (3) in the manufacturing method of the present invention, that is, “an active layer precursor film and a protective insulating film are laminated on a gate insulating film, and the protective insulating film has a thickness of 100 nm or less. As the step of forming a laminated body that is, after the gate insulating film 6 is laminated, an amorphous silicon film is first laminated by a plasma CVD method to a thickness of 10 to 100 nm, and the amorphous silicon film is subjected to thermal annealing using an infrared lamp, Crystallization is performed by a technique such as laser annealing to form a polysilicon film 7 (FIG. 2C). This polysilicon film 7 becomes an active layer. As a method for forming the polysilicon film 7, the polysilicon film 7 may be directly formed by a thermal CVD method or the like.
[0026]
Subsequently, a protective insulating film 8 made of silicon oxide is formed to a thickness of 100 nm or less by a thermal CVD method, a plasma CVD method, or the like (FIG. 2C).
[0027]
In the present invention, the protective insulating film 8 is formed to have a thickness of 100 nm or less in this way, and in the subsequent process of forming the LDD region or the source / drain region, the protective insulating film 8 is not etched and phosphorus is passed through the protective insulating film 8. It is characterized by implanting a dopant such as arsenic. Thereby, the etching process (FIGS. 7D and 7F) of the protective insulating film 8 according to the conventional method can be reduced, so that productivity can be improved. Further, since the polysilicon film 7 is not etched unnecessarily, the breakdown voltage failure of the gate insulating film 6 can be prevented, point defects and line defects of the polysilicon film 7 can be remarkably reduced, and the product yield can be improved. .
[0028]
Here, the thickness of the protective insulating film 8 is set to 100 nm or less from the viewpoint of the limit of the acceleration voltage of the implantation apparatus when a dopant such as phosphorus or arsenic is implanted through the protective insulating film 8, but the acceleration voltage is low. From the viewpoint of reducing the manufacturing cost by using an injection device, the thickness of the protective insulating film 8 is preferably 50 nm or less. On the other hand, if the protective insulating film 8 is not formed, the LDD region forming resist mask (LDD implantation mask) is in direct contact with the polysilicon film 7 serving as an active layer in the LDD region forming step, and the subsequent source / drain regions Also in this forming process, the N channel SD implantation mask and the P channel SD implantation mask are in direct contact with each other, so that the problem of contamination of the polysilicon film 7 occurs. Therefore, the thickness of the protective insulating film 8 is preferably 5 nm or more.
[0029]
In the manufacturing method of this aspect, as the step (4) in the manufacturing method of the present invention, that is, “the step of implanting a dopant into the LDD region or the source / drain region of the active layer precursor film through the protective insulating film” An LDD implantation mask 22 is formed on the protective insulating film 8, and phosphorus, arsenic, etc. are implanted to form an LDD region 9 (FIG. 2D), and then an N channel source / drain region (SD region) 10 is formed. Is formed, an N channel SD implantation mask 11 is formed, and high concentration phosphorus, arsenic, or the like is implanted. At this time, since the implantation is also performed on the polysilicon film 7 in the auxiliary capacitance region formed by the polysilicon film 7 and the gate electrode 2, the resist mask is not formed in the auxiliary capacitance region. When forming a C-MOS circuit or the like here, in order to form a P-channel source / drain region, a mask is again formed with resist or the like, and boron or the like is implanted.
[0030]
Thereafter, as step (5) of the present invention, thermal annealing or laser annealing is performed to activate the implanted dopant such as phosphorus. Thus, the TFT 100A of the present invention is obtained (FIG. 2E).
[0031]
In order to manufacture a liquid crystal display device using the TFT 100A as a driving element, next, a resist is formed on the formation portion of the TFT 100A, and unnecessary portions of the protective insulating film 8 and the polysilicon film 7 are patterned (FIG. 2F). )). Also in this case, hydrofluoric acid-based wet etching or fluorine-based dry etching is usually used for etching the protective insulating film 8. For the etching of the polysilicon film 7, F-based or Cl-based dry etching is often used.
[0032]
Subsequently, as a step (6) of the present invention, the protective insulating film 8 is reformed. Specifically, an oxidizing atmosphere such as N₂Plasma treatment is performed in an O atmosphere. Thereby, the foreign matter remaining on the surface of the protective insulating film 8 is ashed (ashed) and removed. Mainly, carbon-based foreign matters such as resist residues are incinerated by plasma irradiation in an atmosphere containing oxygen. Further, oxygen particles accelerated by the plasma also enter the composition of the protective insulating film 8 and can be repaired by filling the defects in the film. As described above, the modification treatment includes cleaning of the surface of the protective insulating film 8 and removal or repair of defects in the protective insulating film 8.
[0033]
  The surface of the protective insulating film 8 is cleaned and defects in the protective insulating film 8 are removed or repaired.Therefore, various reforming means can be taken. For example, pure water is supplied to the surface of the etched protective insulating film 8 to perform cleaning. By this pure water cleaning, foreign matter adhering to the surface of the protective insulating film 8 can be removed. In some cases, the surface of the protective insulating film 8 may be washed with water containing an oxidizing additive. As the oxidizing additive, one kind or a combination of two or more kinds of ozone, hydrogen peroxide solution, sulfuric acid, nitric acid and carbonic acid can be used. Surface cleaning can be performed by utilizing the oxidizing action of such an additive. Alternatively, desired modification can be performed by performing heat treatment within a range that does not impair the heat resistance of the substrate 1 made of glass or the like. Specifically, the substrate is heated at a temperature not causing distortion. This heat treatment can be performed in an atmosphere containing oxygen. Thereby, the foreign matter adhering to the surface of the protective insulating film 8 can be removed by ashing. At the same time, defects in the protective insulating film 8 can be removed or repaired by introducing oxygen element. Instead of oxygen gas, heat treatment may be performed in an atmosphere containing water vapor. In addition, it is preferable to use a rapid heating method (RTA) as a heating means. RTA can heat a substrate rapidly by using an infrared lamp or an ultraviolet lamp as a heat source and irradiating the substrate with light energy for a short time. For example, the substrate temperature can be raised to 600 ° C. or higher within a few seconds. Thereby, the modification treatment of the protective insulating film 8 can be performed without thermally damaging the glass substrate 1. Furthermore, the surface layer of the protective insulating film 8 can be partially removed by etching with hydrofluoric acid or the like, so that modifications including surface cleaning can be performed. By combining one or several of these means, the protective insulating film 8 is modified and the long-term reliability of the thin film transistor is improved.
[0034]
Thereafter, the interlayer insulating film 13, the source electrode 17 and the drain electrode 18, the planarization film 19, the transparent electrode 20, and the alignment film 21 are formed on the transparent electrode 20. This can be the same as the conventional method described above. That is, after the modification of the protective insulating film 8, the silicon nitride film 14 (50 to 500 nm) and the silicon oxide film 15 (50 to 500 nm) are continuously formed in order to form the interlayer insulating film 13 without being exposed to the air as it is. Next, the interlayer insulating film 13 and the gate insulating film 6 are removed by etching to form a contact hole 16 (FIG. 3H), and a metal such as Al is embedded in the contact hole 16. Thus, the source electrode 17 and the drain electrode 18 are formed (FIG. 3I). Then, a flattening film 19 such as an organic flattening film or a silicon nitride flattening film is formed in a region excluding a portion for forming a contact with the transparent electrode of the liquid crystal display panel and a pad forming portion, and then a pixel portion. A transparent electrode 20 made of ITO or the like is formed so as to cover, and an alignment film 21 is formed on the transparent electrode 20. Thus, a TFT substrate 201A for a liquid crystal display device using the TFT 100A of the present invention as a drive element is obtained (FIG. 3J).
[0035]
The liquid crystal display device 200A of FIG. 1 is manufactured by combining the above-described TFT substrate 201A and a counter substrate 203 having a known counter electrode 202, and sandwiching the liquid crystal 204 between the two substrates by a conventional method. Can do.
[0036]
As described above, the manufacturing method of the TFT according to one embodiment of the present invention has been described using the liquid crystal display device 200A using the TFT as an example. However, the manufacturing method of the TFT of the present invention includes the protective insulating film 8 on the active layer precursor film. As long as the thickness is 100 nm or less and a dopant is implanted through the protective insulating film 8 to form an LDD region or a source / drain region, various modes can be adopted.
[0037]
For example, in the TFT of the present invention described above, the active layer precursor film into which the dopant is implanted is the polysilicon film 7. However, in the present invention, the active layer precursor film is not limited thereto. For example, an amorphous silicon film, a silicon germanium film, a silicon carbide film, or the like may be used as the active layer precursor film. From the viewpoint of consistency with the process, it is preferable to use a polysilicon film.
[0038]
Further, in the TFT 100A of the present invention described above, in step (3), an amorphous silicon film is laminated on the gate insulating film 6, and the amorphous silicon film is crystallized to form a polysilicon film 7. On the polysilicon film 7, as shown in FIG. The protective insulating film 8 is formed on the surface, but after the amorphous silicon film is formed by the CVD method or the like, the amorphous silicon film is continuously crystallized without breaking the vacuum degree of the chamber without crystallization. The polysilicon film 7 may be formed by forming the insulating film 8 and then crystallizing the amorphous silicon film. Thereby, the contamination of the polysilicon film 7 can be further prevented.
[0039]
Further, in the TFT of the present invention described above, the protective insulating film 8 made of silicon oxide is formed by the plasma CVD method or the like in the step (3), but by the surface oxidation of the amorphous silicon film to be the polysilicon film 7. A protective insulating film 8 may be formed. As a method for surface oxidation, for example, the surface is exposed to hot water vapor or ozone gas at about 400 ° C., or is irradiated with ultraviolet rays in an atmosphere containing oxygen. According to this method, a silicon oxide film of 5 to 20 nm can be formed with good film thickness control. Therefore, when the polysilicon film 7 is formed by crystallization of the amorphous silicon film by laser annealing or the like, the film thickness and crystallization of the polysilicon film are formed. Controllability is improved.
[0040]
The TFT manufacturing method of the present invention can be applied not only to a liquid crystal display device but also to a method for manufacturing an organic EL device using a TFT as a drive element.
[0041]
For example, in the organic EL device 300 of FIG. 4, a TFT substrate is manufactured according to the above-described manufacturing method, and a known organic EL device manufacturing method (Japanese Patent Laid-Open Nos. 11-251069, 10-189252, etc.) Therefore, it can be manufactured as follows. First, a TFT 100A is formed on a transparent glass substrate 1 in which a gate electrode 2, a gate insulating film 6, an active layer made of a polysilicon film 7, and a protective insulating film 8 having a thickness of 100 nm or less are sequentially stacked. Next, after modifying the protective insulating film 8 according to the present invention, preferably without exposure to the atmosphere, the interlayer insulating film 13 is formed on the protective insulating film 8, and the source electrode 17 and the drain electrode 18 are further formed. Then, a planarizing film 19 is formed, and a contact hole 23 is opened in the planarizing film 19. A cathode layer 31 of the organic EL element 30 is formed on the planarizing film 19, and the source electrode 17 and the cathode layer 31 of the TFT 100 </ b> A are brought into conduction through the contact hole 23. On the cathode layer 31, an electron transport layer 32, a light emitting layer 33, and a hole transport layer 34 are sequentially formed, and an anode layer 35 is formed on the hole transport layer 34. Thus, the organic EL element 30 in which the holes injected from the anode layer 35 and the electrons injected from the cathode layer 31 are recombined inside the light emitting layer 33 to emit light, and the light emission is the TFT of the present invention. The organic EL device 300 driven by can be manufactured. In the organic EL device 300, light can be extracted from the anode layer 35 side.
[0042]
Here, there are no particular restrictions on the layer configuration of the organic EL element 30 itself, the formation material of each layer, and the like, and there are no particular restrictions on the formation material and formation method of the planarization film 19 between the TFT 100A and the organic EL element 30. Absent.
[0043]
For example, the planarizing film 19 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicate glass film, an SOG film, a polyimide-based, an acrylic-based synthetic resin film, or the like.
[0044]
The cathode layer 31 can be formed of magnesium / indium alloy, aluminum / lithium alloy, or the like. The electron transport layer 32 can be formed from Bebq2 (10-benzo [h] quinolinol-beryllium complex) or the like, and the light-emitting layer 33 can be formed from Bebq2, 8-quinolinol aluminum complex or the like containing a quinacridone derivative. The transport layer 34 includes TPD (4,4 ′, 4 ″ -tris- (methylphenylphenylamino) triphenylamine), MTDATA (4,4′-bis (3-methylphenylphenyl) biphenyl), α-NPD (α-naphthylminyl) and the like. The anode layer 35 can be formed from Pt, Rh, Pd, or the like. Each of these layers can be formed by a vapor deposition method or the like. The anode layer 35 may be formed from ITO or the like by sputtering.
[0045]
As an organic EL device driven by a TFT, as shown in FIG. 5, the layer configuration of the organic EL element 30 on the TFT 100 </ b> A is reversed, and the anode layer 35, the hole transport layer 34, and the light emission are formed on the planarizing film 19. The layer 33, the electron transport layer 32, and the cathode layer 31 may be sequentially stacked. In this organic EL device, light can be extracted from the substrate 1 side.
[0046]
In addition, the organic EL device includes various modes as long as the TFT produced in the present invention is used.
[0047]
【The invention's effect】
According to the present invention, in the bottom gate TFT, the thickness of the protective insulating film on the polysilicon film serving as the active layer is 100 nm or less, and the LDD region or the source / drain region is formed through the protective insulating film. Alternatively, the step of etching the protective insulating film is not required for forming the source / drain regions. Therefore, it is possible to reduce the manufacturing process and improve the productivity of the TFT. Further, the breakdown voltage failure of the gate insulating film can be prevented, the point defects and line defects of the active layer are remarkably reduced, and the product yield is improved.
[0048]
In particular, in the present invention, before the interlayer insulating film is formed, the protective insulating film covering the active layer of the TFT is modified to clean the surface and remove defects in the film. Thereby, variation in the initial threshold voltage of the thin film transistor can be reduced. Further, variation in initial current characteristics of the thin film transistor can be reduced. Furthermore, it is possible to suppress changes in characteristics of the thin film transistor over time. In addition, by cleaning the interface between the protective insulating film and the interlayer insulating film, the shape abnormality of the contact between the semiconductor thin film and the metal wiring such as aluminum can be reduced. For the same reason, it is possible to improve the withstand voltage between the semiconductor thin film made of polycrystalline silicon or the like and the metal wiring made of aluminum or the like. In addition, in the portion where the gate insulating film is exposed in the very vicinity of the semiconductor thin film made of polycrystalline silicon or the like, the same modification and cleaning action can be obtained, and in terms of initial TFT characteristics and long-term reliability, etc. Improvement effect is obtained. Further, in the portion where the gate insulating film is exposed on the gate electrode, the same modification and cleaning action can be obtained, and the abnormal shape of the contact between the gate electrode and the metal wiring made of aluminum or the like can be reduced. For the same reason, the withstand voltage between the gate electrode and the metal wiring made of aluminum or the like can be improved. Furthermore, ionic impurities such as sodium can be removed by cleaning the surface of the protective insulating film by light etching or the like.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a liquid crystal display device using a TFT prepared according to the present invention.
FIG. 2 is a manufacturing process diagram of a liquid crystal display device using a TFT according to the present invention.
FIG. 3 is a manufacturing process diagram of a liquid crystal display device using a TFT according to the present invention.
FIG. 4 is a schematic cross-sectional view of an organic EL device using a TFT prepared according to the present invention.
FIG. 5 is a schematic cross-sectional view of an organic EL device using a TFT prepared according to the present invention.
FIG. 6 is a schematic cross-sectional view of a liquid crystal display device using a conventional TFT.
FIG. 7 is a manufacturing process diagram of a liquid crystal display device using a conventional TFT.
FIG. 8 is a manufacturing process diagram of a liquid crystal display device using a conventional TFT.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Transparent glass substrate, 2 ... Gate electrode, 3 ... Cs electrode, 4 ... Silicon nitride film, 5 ... Silicon oxide film, 6 ... Gate insulating film, 7 ... Polysilicon film, 8 ... Protective insulating film, 9 ... LDD area | region DESCRIPTION OF SYMBOLS 10 ... Source / drain region, 11 ... SD implantation mask, 13 ... Interlayer insulation film, 14 ... Silicon nitride film, 15 ... Silicon oxide film, 17 ... Source electrode, 18 ... Drain electrode, 20 ... Transparent electrode, 21 ... Orientation Membrane, 30 ... Organic EL element, 31 ... Cathode layer, 32 ... Electron transport layer, 33 ... Light-emitting layer, 34 ... Hole transport layer, 35 ... Anode layer, 100A ... TFT, 200A ... Liquid crystal display device, 201A ... TFT substrate 202 ... Counter electrode 203 ... Counter substrate 204 ... Liquid crystal 300 ... Organic EL device

Claims (14)

(1) forming a gate electrode on the substrate;
(2) forming a gate insulating film on the gate electrode;
(3) A step of forming a laminate in which an active layer precursor film and a protective insulating film are stacked on a gate insulating film, and the protective insulating film has a thickness of 100 nm or less;
(4) A step of implanting a dopant into the LDD region or the source / drain region of the active layer precursor film through the protective insulating film while leaving the protective insulating film on the LDD region or the source / drain region without etching. ,
(5) activating the implanted dopant and making the dopant non-implanted portion an active layer;
(6) Process of treating all or a part of the protective insulating film to clean the surface of the protective insulating film and removing or repairing defects in the protective insulating film ;
(7) forming an interlayer insulating film on the treated protective insulating film; and (8) forming a source / drain electrode on the interlayer insulating film;
A method for producing a bottom-gate thin film transistor, comprising: In step (6) , the protective insulating film is washed with water containing an oxidizing additive to clean the surface of the protective insulating film and remove or repair defects in the protective insulating film. The manufacturing method according to claim 1.   3. The production method according to claim 2, wherein the oxidizing additive is one kind or several kinds of ozone, hydrogen peroxide solution, sulfuric acid, nitric acid, and carbonic acid. The step (6) is characterized in that the protective insulating film is heat-treated at a temperature that does not cause distortion of the substrate to clean the surface of the protective insulating film and remove or repair defects in the protective insulating film. The manufacturing method according to claim 1.   The manufacturing method according to claim 4, wherein the heat treatment is performed in an atmosphere containing oxygen.   The manufacturing method according to claim 4, wherein the heat treatment is performed in an atmosphere containing water vapor. The step (6) is characterized in that the protective insulating film is plasma-treated in an atmosphere containing oxygen to clean the surface of the protective insulating film and remove or repair defects in the protective insulating film. 1. The production method according to 1. The step (6) is characterized in that the protective insulating film is plasma-treated in a dinitrogen monoxide atmosphere to clean the surface of the protective insulating film and remove or repair defects in the protective insulating film. Item 2. The production method according to Item 1.   2. The manufacturing method according to claim 1, wherein the active layer is made of a polysilicon film.   In the step (3), an amorphous silicon film is formed on the gate insulating film, the amorphous silicon film is crystallized to form a polysilicon film, and a protective insulating film is formed on the polysilicon film with a film thickness of 100 nm or less. 9. The production method according to 9.   10. In the step (3), an amorphous silicon film is formed on the gate insulating film, a protective insulating film is continuously formed on the amorphous silicon film, and then the amorphous silicon film is crystallized to form a polysilicon film. The manufacturing method as described.   In step (3), an amorphous silicon film is formed on the gate insulating film, a surface of the amorphous silicon film is oxidized to form a protective insulating film on the surface of the amorphous silicon film, and then the amorphous silicon film is crystallized. The manufacturing method according to claim 9, wherein a polysilicon film is used.   A source / drain electrode is formed in the step (8) in the method of manufacturing a bottom gate type thin film transistor according to any one of claims 1 to 12, and then a transparent electrode and an alignment film are formed to produce a TFT substrate. A method for manufacturing a liquid crystal display device, characterized in that liquid crystal is sandwiched between a substrate and a counter substrate provided with a counter electrode.   An organic EL driven by the bottom gate type thin film transistor on the interlayer insulating film after forming the source / drain electrodes in the step (8) in the method of manufacturing a bottom gate type thin film transistor according to any one of claims 1 to 12. A method of manufacturing an organic EL device, wherein an element is formed.

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