JP4087684B2 - Semiconductor integrated circuit for communication and offset correction method for amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique that is effective when applied to a signal amplifier circuit, for example, a variable signal amplifier circuit, or an amplifier circuit for a received signal in a wireless communication device, such as EDGE (Enhanced Data Rates for GMS Evolution) mode. The present invention relates to a technique effective when used in an amplifier used in a wireless communication system having a transmission / reception mode, for example, a variable gain amplifier.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, there is a system called a superheterodyne system in a semiconductor integrated circuit for wireless communication that is used in a mobile phone and processes transmission / reception signals. This superheterodyne method has a problem that the circuit scale is large because the received signal is once down-converted to an intermediate frequency signal and then demodulated. Therefore, a direct conversion method has been proposed in which a received signal is directly down-converted into a baseband signal (I, Q) of an audio frequency and demodulated.
[0003]
In the superheterodyne method, the AC connection that transmits the received signal through the capacitor from the low noise amplifier circuit (LNA) to the previous stage of the demodulator is used, so that the reference voltage for the current source that sends the operating current to the amplifier of each stage is set. Even if there is a DC offset in the output of the amplifier due to fluctuations in the voltage generated by the generated reference voltage generation circuit, the DC component is not transmitted in the case of AC coupling. For this reason, since the DC offset at the front stage does not affect the circuit at the rear stage, the DC voltage fluctuation at the output of the amplifier at the last stage is extremely small.
[0004]
However, since a direct conversion type receiving circuit down-converts and demodulates a received signal such as 900 MHz to a signal of an audio frequency (0 to 70 kHz) at the same time by a mixer, the mixer and the variable gain amplifier must be DC coupled. If a DC offset occurs in the output of the mixer, the DC offset is amplified by the variable gain amplifier. In addition, an analog amplifier circuit such as a variable gain amplifier causes a direct current offset due to variations in elements. Therefore, an invention for canceling the DC offset of the variable gain amplifier has been proposed (Japanese Patent Application No. 2002-11049).
[0005]
In a superheterodyne mobile phone, the gain required for the variable gain amplifier for amplifying the received signal is not so high, so that only one stage of amplifier is required. On the other hand, since a maximum gain of close to 60 dB is required for the amplification unit subsequent to the mixer in the direct conversion type receiver circuit, a circuit in which several stages of low-pass filter LPF and variable gain amplifier PGA are alternately connected is provided. It is used.
[0006]
In the receiving circuit of the prior invention, an offset cancel circuit is provided for each variable gain amplifier. Further, in the GSM mobile phone, the transmission mode and the reception mode are switched in a unit of time called a time slot as shown in FIG. 6 (for example, 577 microseconds). The offset cancellation of all the variable gain amplifiers is performed within a short time such as 20 μs allowed at the time of slot switching.
[0007]
On the other hand, in recent years, digital communication systems are becoming mainstream in wireless communication devices represented by mobile phones. Various modulation methods such as a frequency modulation method, a phase modulation method, and a time division multiple access method are employed as modulation methods in digital communication. Even in the same communication device, for example, communication of an audio signal is performed by a GMSK modulation method in which a transmission signal is first shaped by a Gaussian filter and then the phase of a carrier wave is phase-shifted according to transmission data. Is an EDGE-compatible communication device that performs high-speed operation using an EDGE modulation method in which an amplitude shift is further added to the phase shift of GMSK modulation.
[0008]
[Problems to be solved by the invention]
In the high gain amplifying unit comprising a low pass filter and a variable gain amplifier in the receiving circuit of the EDGE mobile phone, as shown in FIG. 7, the amplitude modulation is applied to the high frequency signal. The signal level increases by about 3 to 3.5 dB. If the signal is received as a jamming wave and it is higher than the desired wave level, the gain of the amplifier is clipped by the jamming wave and the dynamic range of the amplifier circuit is determined, so the desired wave can be sufficiently amplified. Disappear.
[0009]
Therefore, in the receiving circuit of the EDGE cellular phone, it is necessary to attenuate the interference wave by setting the frequency characteristic of the low-pass filter steeper than the frequency characteristic of GSM as shown in FIG. In order to increase the attenuation in the high band without changing the passband, it is effective to increase the order of the low-pass filter. However, if the order of the low-pass filter is increased, compared to a filter with a lower order. As a result, the transient response characteristic becomes slow, and it has become clear that there is a problem that it is difficult to finish offset cancellation of the variable gain amplifier within a specified time of 20 μs.
[0010]
An object of the present invention is to provide a predetermined conversion time in a direct conversion communication semiconductor integrated circuit (high frequency IC) having a high gain amplifier circuit in which a plurality of variable gain amplifiers for amplifying a received signal and low pass filters are connected in multiple stages. The offset cancel operation of the high gain amplification unit can be completed.
[0011]
Another object of the present invention is to provide a highly versatile communication semiconductor integrated circuit capable of supporting a plurality of wireless communication systems.
[0012]
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
[0013]
[Means for Solving the Problems]
Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
[0014]
That is, in a semiconductor integrated circuit for communication such as a high-frequency IC that performs signal processing of a direct conversion system having a high gain amplifier circuit in which a plurality of differential variable gain amplifiers and low-pass filters are connected in multiple stages to amplify a received signal, Each low-pass filter is provided with a short-circuiting switch element for making the differential signal the same potential, and each variable gain amplifier is provided with an offset cancel circuit, while a high-order filter is used as the low-pass filter and a resistive element constituting the filter In addition, a switch element is provided in parallel with the switch element so that the order of the filter can be switched according to whether the switch element is on or off.
[0015]
When each variable gain amplifier is operated in order to cancel the offset in order from the first stage, both the short-circuit switch element and the order switching switch element are turned on to make the low-pass filter a low-order filter and offset correction. After that, the switch element for short-circuiting is turned off with the filter being a low-order filter to quickly converge the output of the variable gain amplifier, and then the switch element for order switching is turned off to turn the low-pass filter into a high-order filter. The output of the variable gain amplifier at the previous stage is input to the variable gain amplifier at the subsequent stage by switching to this filter, and the process proceeds to the offset cancel operation of the variable gain amplifier at the subsequent stage.
[0016]
According to such means, the offset cancellation can be performed in a shorter time than when only the short-circuiting switch element is turned on, and the order switching switch immediately after the offset cancellation of the variable gain amplifier is completed. Since the switch element for short circuit is turned off while the element is turned on and connected as a low-order filter, it is more variable than when the switch element for short circuit is turned off with a high-order filter connected The output of the gain amplifier can be quickly converged. After that, when the switching element for switching the order is turned off and the output of the preceding variable gain amplifier is input to the subsequent variable gain amplifier through the filter, the change in potential is in-phase component with respect to the subsequent variable gain amplifier. Therefore, the influence of potential change due to the off operation of the switching element for order switching does not appear in the output of the subsequent variable gain amplifier constituted by the differential amplifier. As a result, it is possible to complete the offset cancellation operation of the multiple stages of variable gain amplifiers in a short time.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0018]
FIG. 1 shows a configuration example of a high-frequency IC and an entire system constituting an EDGE-compatible mobile communication system as an example of a preferred system to which the present invention is applied.
[0019]
In FIG. 1, reference numeral 100 denotes a transmission / reception antenna for signal radio waves, 110 denotes a switch for transmission / reception switching, 120 denotes a high-frequency filter for removing unnecessary waves from the received signal, 200 denotes a high-frequency IC having a modulation / demodulation circuit, and 300 denotes a desired high-frequency IC 200. A baseband circuit (IC) for extracting data from a received signal down-converted to a frequency, converting transmission data into I and Q signals, and controlling the high frequency IC 200, and 130 is a high frequency power amplifier circuit for amplifying the transmission signal 140 are high frequency oscillators (RFVCO) that generate an oscillation signal φRF having a frequency corresponding to a desired band.
[0020]
The high frequency IC 200 includes a reception system circuit 210, a transmission system circuit 220, and a control system circuit. Although not particularly limited, in this embodiment, the high-frequency oscillator (RFVCO) 140 is shared by the transmission system circuit and the reception system circuit. The reception system circuit 210 directly generates a signal of 900 MHz to 1.9 GHz by synthesizing the low-noise amplifier circuit (LNA) 211, the amplified reception signal, and the oscillation signal φRF ′ divided by the frequency dividing circuit 241. It comprises a demodulation circuit 212 that down-converts to a signal in the audio frequency band of ˜70 kHz and performs demodulation, and a high gain amplification circuit (PGA) 213 that amplifies the demodulated reception signal with high gain.
[0021]
Although not shown in FIG. 1, the demodulation circuit 212 is provided with two mixers, a mixer that synthesizes a sine wave signal with a received signal and a mixer that synthesizes a cosine wave signal with a received signal, and a high gain circuit. Two 223 are provided corresponding to each mixer, and are demodulated as an I signal and a Q signal, respectively amplified, and supplied to the baseband circuit 300.
[0022]
The control system circuit divides the oscillation signal φRF generated by the high-frequency oscillator (RFVCO) 140, generates a control signal inside the RF chip according to the control code from the baseband circuit 300, A control circuit 242 for controlling the gain of the variable gain amplifier in the high gain amplifier circuit 213 and executing offset cancellation; a local oscillation circuit 243 for generating a local oscillation signal φIF having an intermediate frequency such as 320 MHz; The frequency dividing circuit 244 generates a carrier wave TXIF such as 80 MHz by dividing the oscillation signal φIF generated by the oscillation circuit 243.
[0023]
The transmission system circuit 220 includes a transmission oscillator (TXVCO) 221, a modulation circuit 222 that applies quadrature modulation to the carrier wave TXIF output from the frequency dividing circuit 244 by the I signal and the Q signal supplied from the baseband circuit 300, A mixer 223 that synthesizes the oscillation signal φRF ′ divided by the frequency circuit 241 and the transmission signal φTX fed back from the transmission oscillator (TXVCO) 221 to generate a signal φmix having a frequency corresponding to the frequency difference between the two signals. A harmonic filter 224 that cuts off harmonic components that leak from the mixer 223, a phase detection circuit 225 that detects a phase difference between the signal from the mixer 223 and the modulation signal from the modulation circuit 222, and the phase detection circuit Charge pump 226 operated by signals (UP, DOWN) output from 270, and the charge pump And a like loop filter 227 which generates a voltage Vc corresponding to the phase difference by 226.
[0024]
The control circuit 242 has a control register CRG. The register CRG is set based on a signal from the baseband circuit 300, and performs control based on the control data. Specifically, a clock signal CLK for synchronization, a data signal SDATA, and a load enable signal LEN as a control signal are supplied from the baseband circuit 300 to the high frequency IC 200, and the control circuit 330 When the signal LEN is asserted to a valid level, the data signal SDATA transmitted from the baseband circuit 300 is sequentially fetched in synchronization with the clock signal CLK, set in the control register CRG, and a predetermined control sequence is started. . Although not particularly limited, the data signal SDATA is transmitted serially. The baseband circuit 300 is composed of a microprocessor or the like.
[0025]
FIG. 2 shows an embodiment of the high gain amplifier circuit 223.
[0026]
In this embodiment, a first variable gain amplifier PGA1 is provided downstream of the first low-pass filter LPF1, a second low-pass filter LPF2 is provided downstream of the variable gain amplifier PGA1, and a second low-pass filter LPF2 is connected downstream of the first low-pass filter LPF1. A variable gain amplifier PGA2 is connected. Further, the third low-pass filter LPF3 is connected to the subsequent stage of the second variable gain amplifier PGA2, and the third variable gain amplifier PGA3 is connected to the subsequent stage. Further, a fourth low-pass filter LPF4 is connected to the subsequent stage of the third variable gain amplifier PGA3, and a final amplifier PGA4 capable of switching the gain to about four stages is connected to the subsequent stage. The variable gain amplifiers PGA <b> 1 to PGA <b> 3 are amplifiers that can adjust the gain in almost a linear or multistage manner compared to the final amplifier PGA <b> 4.
[0027]
The final amplifier PGA4 can use a fixed-gain amplifier because the gain is uniquely determined according to the system configuration when the system configuration is determined, that is, the type of baseband circuit to be used is determined. In the example, the versatility of the high-frequency IC 200 is enhanced by using an amplifier whose gain can be switched to about four stages.
[0028]
In the high frequency IC 200 of this embodiment, the first offset correction circuit OFC1 corresponds to the first variable gain amplifier PGA1, and the second offset correction circuit OFC1 corresponds to the second variable gain amplifier PGA2. However, a third offset correction circuit OFC3 is connected corresponding to the third variable gain amplifier PGA3.
[0029]
The offset correction circuits OFC1 to OFC3 are held in an AD conversion circuit ADC1 that AD-converts the output potential difference of the amplifier PGA1 and a register REG1 in the control circuit 340 as representatively shown for the first offset correction circuit OFC1. DA converter circuit DAC1 which correct | amends an offset by DA-converting the value which adjusts the value of the electric current which flows into the current source provided in amplifier PGA1. In the control circuit 242, registers REG1 to REG3 that hold offset correction values corresponding to the offset correction circuits OFC1 to OFC3 are provided, and signals output from the amplifiers in a state where the input terminals of the amplifiers are short-circuited. Based on the value obtained by AD-converting the level difference, that is, the offset voltage, a correction value that sets the difference (offset voltage) to “0” is determined and stored in the corresponding register.
[0030]
Further, in the control circuit 242, a register for holding data specifying the gain of the variable gain amplifier supplied from the baseband circuit 300 is provided. Based on the set value of the register, each of the amplifiers PGA1 to PGA1. The gain control signals GC1 to GC4 for the PGA 4 are generated and supplied.
[0031]
In the high gain amplifying circuit 223 of this embodiment, the offset correction of the variable gain amplifiers PGA1 to PGA3 is performed by the offset correction circuits OFC1 to OFC3 within the time of 20 μs allowed at the time of switching between slots. Yes. This is because the gains of the variable gain amplifiers PGA1 to PGA3 vary depending on the level (intensity) of the received signal, and offset cancellation must be performed every time. The offset cancellation of the variable gain amplifiers PGA1 to PGA3 is performed in the order of the offset correction circuits OFC1 to OFC2, OFC3 in the first stage in a state where each amplifier is adjusted to a gain determined in the baseband based on the received signal level in the immediately preceding slot. For example, the operation is completed every 4 μs, and then a stabilization period of about 8 μs is provided.
[0032]
As will be described later, offset cancellation of the variable gain amplifiers PGA1 to PGA3 is performed in order from the first stage, so that the AD conversion circuits of the offset correction circuits OFC1 to OFC3 are used in a time-sharing manner. It is possible to configure. The DA converter circuit DAC1 outputs n types of weight currents (n is a positive integer, for example, a value such as 6) having a current value of i, 2i, 4i, 8i,. By combining and converting to a voltage according to the input signal of the bit, 2 ⁿ It is possible to select and output one of the stage voltage values. The same applies to the AD conversion circuits of the other offset correction circuits OFC2, OFC3.
[0033]
Next, a specific circuit example of each stage of the variable gain amplifier PGA and the low-pass filter LPF and a specific procedure of the offset cancellation method according to the present invention will be described with reference to FIG.
[0034]
The amplifier PGA includes variable resistors VR, Q1, Q2 connected between the collectors of the input differential transistors Q1, Q2 and Q1, Q2 and the emitters of the resistors Rc1, Rc2, Q1, Q2 connected between the power supply voltage Vcc. Differential amplifier stage composed of constant current sources CC1 and CC2 connected between the emitters of the transistors Q1 and Q2 and the emitters of the transistors Q3 and Q4 and Q3 and Q4 whose bases are connected to the collectors of Q1 and Q2 and the ground point And an emitter follower output stage composed of constant current sources CC3 and CC4 connected to each other, and variable current sources VC1 and VC2 connected between the collectors of Q1 and Q2 and the ground point. The gain is changed by changing the resistance value of the variable resistor VR between the emitters by the gain control signal GC from the control circuit 242. Transistors Q1-Q4 are NPN bipolar transistors.
[0035]
The offset correction circuit OFC including the AD conversion circuit and the DA conversion circuit receives the collector voltage of the transistors Q1 and Q2, and the collector potential difference becomes “0” when the base potential difference between Q1 and Q2 is “0”. The currents of the variable current sources VC1 and VC2 are adjusted. The emitter voltage of the emitter follower transistors Q3 and Q4 is input to the offset correction circuit OFC, and the currents of the variable current sources VC1 and VC2 positioned as shown in FIG. 3 are adjusted to include the emitter follower output stage. It may be configured to correct the offset in the state.
[0036]
Further, instead of providing the variable current sources VC1 and VC2 between the collectors of the transistors Q1 and Q2 and the grounding point, the constant current sources CC3 and CC4 of the emitter followers are replaced with variable current sources, and the current is generated by the offset correction circuit OFC. Adjustment may be made to correct the offset. Further, variable current sources VC1 and VC2 are provided between the input terminals, that is, the base terminals of the transistors Q1 and Q2 and the ground point, and the input terminals are positioned as shown in FIG. 3 or emitter follower transistors Q3 and Q4. The currents of the variable current sources VC1 and VC2 may be adjusted by the offset correction circuit OFC connected to the emitters of the first and second emitters. In that case, it is desirable to connect base resistors such as resistors R11 and R12 between the base terminals of the transistors Q1 and Q2 and the preceding circuit.
[0037]
The low-pass filter LPF is a constant current connected between the emitters of the PNP transistors Q5, Q6 and Q5, Q6 whose bases are connected to the emitters of the transistors Q3, Q4 in the emitter follower output stage and the power supply voltage Vcc. An emitter-follower type input stage comprising sources CC5 and CC6, resistors R1 and R2 having one ends connected to the emitters of Q1 and Q2, resistors R3 and R4 connected in series with R1 and R2, and resistors R3 and R4 The capacitor C0 connected between the terminals, and the NPN transistors Q7, Q8 and Q7, Q8 whose bases are connected to the connection node between the resistors R3, R4 and the capacitor C0 are connected between the ground and the emitter. Between the emitter follower amplification stage composed of the constant current sources CC7 and CC8 and the connection node N1 between the emitter of the transistor Q7 and the resistors R1 and R3 And a capacitor connected C1, and a connected capacitor C2 Metropolitan between a connection node N2 between the emitter and the resistor R2 and R4 of transistor Q8, as a secondary filter. Q11 and Q12 are transistors constituting the input buffer of the amplifier in the subsequent stage.
[0038]
The resistors R1 to R4 are each set to a resistance value such as 22 kΩ, the capacitance C0 is set to 10 pF, and C1 and C2 are set to a capacitance value such as 90 pF. In this embodiment, the switch element SW0 is connected in parallel with the capacitor C0, the switch element SW1 is connected in parallel with the resistor R1, and the switch element SW2 is connected in parallel with the resistor R2, and these switch elements SW0 to SW2 are connected. It is controlled to be on or off during offset cancellation. Among them, the switch elements SW1 and SW2 are controlled by the same control signal S1, and the switch SW0 is controlled by a control signal S0 different from S1. Even if the switches SW1 and SW2 are not provided, accurate offset cancellation is possible if time is taken. However, by providing the switches SW1 and SW2 and turning them on, the offset cancellation can be performed in a shorter time than when SW and SW2 are not provided. Can do.
[0039]
FIG. 4 shows the timing of the control signals S0 and S1 at the time of offset cancellation.
[0040]
As shown in FIG. 4, in this embodiment, the control signals S0 and S1 are simultaneously changed to a high level, then the control signal S0 is first changed to a low level, and then the control signal S1 is changed to a low level. The Thereby, the switches SW0 to SW2 are simultaneously turned on, and then the switch SW0 is first turned off, and then the switches SW1 and SW2 are turned off. When the switches SW1 and SW2 are turned on and the switch SW0 is turned off, the resistors R1 and R2 cannot be seen from the output terminal of the amplifier PGA. Therefore, the filter LPF acts as a primary filter composed of the resistors R3 and R4 and the capacitor C0. To do.
[0041]
The reason why the switch element SW0 is turned on at the time of offset cancellation is that an accurate offset cancellation cannot be performed if the offset cancel operation is performed with the charge remaining in the capacitor C0. Since the offset cancellation of the amplifiers PGA1 to PGA3 is performed in the same order from the first stage, the calibration operation of the first stage amplifier PGA1 will be described below as a representative, and the description of the calibration operations of other amplifiers will be omitted. .
[0042]
In the calibration of the first-stage amplifier PGA1, when the switches SW0 to SW2 are all turned on, for example, the switch element provided on the input side of the amplifier PGA1 is turned on, so that the same level voltage is applied to the input terminals IN1 and IN2. Entered. In this state, the offset correction circuit OFC is operated, and the currents of the variable current sources VC1 and VC2 are adjusted by the successive approximation method so that the output offset of the amplification stage of the amplifier PGA approaches “0” (period T1 in FIG. 4).
[0043]
As a result, the output offset of the amplifier is calibrated to a value less than the resolution of 4 mV, for example. Therefore, the input potential difference of the filter LPF immediately after the offset correction is set to 4 mV or less. When calibrating the first-stage amplifier PGA1, correction may be performed in a state including the offset of the mixer by turning on a switch element provided between the input terminals of the previous-stage mixer. As a result, the offset of the mixer can be corrected simultaneously with the correction of the offset of the amplifier at the first stage, and the accuracy of the receiving system circuit is improved. In FIG. 3, a switch denoted by reference numeral SW00 is provided between the input terminals of the first-stage amplifier PGA1 or between the input terminals of the mixer and other input sides of the amplifier PGA1, and is used for setting the input potential of the amplifier PGA1 to the same potential. This is a virtual representation of the switch.
[0044]
When the offset correction of the first-stage amplifier PGA1 is completed, SW0 is turned off while the switches SW1 and SW2 in the filter LPF are on (timing t1 in FIG. 4). While the switch SW0 is on, the input potential difference of the rear stage amplifier PGA2 is “0”. However, when the switch SW0 is turned off, the output offset (4 mV or less) remaining in the front stage amplifier is passed through the filter LPF. The input potentials Vin1 and Vin2 of the subsequent stage amplifier PGA2 are opened by the offset ΔVoff as shown in the period T2 of FIG. However, at this time, the filter LPF operates as a primary filter with good transient response characteristics because the switches SW1 and SW2 are turned on, and the input potentials Vin1 and Vin2 are stabilized in a short time without causing ringing.
[0045]
Subsequently, the switches SW1 and SW2 are turned off (timing t2 in FIG. 4). Then, since the filter LPF changes from the primary filter to the secondary filter having a slow transient response, the input potentials Vin1 and Vin2 of the subsequent amplifier vary as shown by a period T3 in FIG. 4 due to the output offset of the previous amplifier. However, since this variation occurs in the same way on the positive phase side and the negative phase side, it is input as an in-phase component to the subsequent amplifier. Here, since the subsequent amplifier is a differential amplifier, the output of the subsequent amplifier does not change due to its CRMM (common-mode component removal ratio) characteristics.
[0046]
Therefore, after the calibration of the previous amplifier is completed, the switch SW0 is turned off, and the output offset of the previous amplifier is transmitted to the input terminal of the subsequent amplifier, so that the calibration operation of the subsequent amplifier can be started immediately. Thus, the time required for offset correction of the entire high gain amplifying unit can be shortened to a time substantially equal to that when a first-order filter is used as a filter.
[0047]
FIG. 5 shows a case where the switches SW1 and SW2 are turned on and off at the same timing as SW0 in the high gain amplifying unit using the secondary filter having the switches SW0 to SW2 as the low pass filter LPF of FIG. 4 shows a waveform obtained by simulation of the output of the amplifier in the subsequent stage when the switches SW1 and SW2 are turned off at a timing different from that of SW0 as shown in FIG.
[0048]
In FIG. 5, the solid line A indicates the output waveform of the amplifier in the subsequent stage when the switches SW1 and SW2 are turned off at a timing different from that of SW0, as in the embodiment of the present invention. This is the output waveform of the amplifier in the subsequent stage when the switches SW1 and SW2 are turned off at the same timing as SW0. In addition, the code | symbol t0-t2 shown by FIG. 5 represents the same timing as the same code | symbol shown by FIG.
[0049]
From FIG. 5, when only the switch SW0 is turned off at the timing t1, the differential output (waveform A) of the subsequent amplifier spreads toward the predetermined level, and the switches SW1 and SW2 are turned off at the timing t2 when the predetermined level is reached. It can be seen that noise appears in the waveform for a moment but immediately settles to a predetermined level. On the other hand, when the switches SW0 to SW2 are all turned off at the same timing t1, the differential output (waveform B) of the subsequent amplifier overshoots a predetermined level when the switches are turned off. It can be seen that after widening, undershoot occurs, that is, ringing occurs and gradually settles to a predetermined level. Therefore, as in the embodiment of the present invention, by controlling the switches SW1 and SW2 to be turned off at a later timing than SW0 at the time of calibration, the output of the subsequent amplifier can be stabilized at an early stage. .
[0050]
Also, without providing the switch SW0, the values of the resistors R1 and R2 and the capacitors C1 and C2 are reduced to lower the time constant. Although there is a concept of making it faster, an offset cancellation time can be maintained while maintaining the filter characteristics sharply by providing a switch SW0 and controlling the switches SW1 and SW2 to be turned off at a timing later than SW0 as in the embodiment. Can be shortened.
[0051]
In the above embodiment, the offset cancel operation is performed in order from the first stage amplifier. However, a short-circuit switch element (SW0 in FIG. 3) for setting the differential signal to the same potential is input to the subsequent stage amplifier, for example. By providing it at a position such as between the base terminals of the transistors Q11 and Q12, it is possible to simultaneously perform offset cancellation of all three stages of amplifiers in parallel. However, by performing the offset cancel operation in order from the first-stage amplifier as in the embodiment, even if some offset remains in the previous-stage circuit, it is transmitted to the subsequent-stage amplifier and includes the offset remaining in the previous-stage amplifier. Therefore, there is an advantage that the offset of the entire high gain amplification section can be reduced.
[0052]
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto. For example, in the above-described embodiment, the case where four stages of variable gain amplifiers constituting the PGA circuit are described. However, the number of stages of the variable gain amplifiers is not limited to four stages, but two stages, three stages, or five stages or more. There may be. In the above embodiment, the filter circuit is a secondary filter circuit and is changed to the primary filter circuit in response to the switch element in parallel with the resistor being turned on. A third or higher order filter may be used, and this may be configured to be switched to a second order or first order filter at the time of offset cancellation.
[0053]
In the circuit of the embodiment (FIG. 3), the switch element SW0 provided in the filter circuit for setting the differential signal to the same potential is provided between the base terminals of the transistors Q7 and Q8. Or between the connection nodes N1 and N2 of the resistors R1 to R4, between the emitter terminals of the transistors Q3 and Q4, between the emitter terminals of the transistors Q7 and Q8, and between the emitter terminals of the transistors Q11 and Q12. . The filter circuit is not limited to the one shown in FIG. 3, for example, instead of connecting the capacitors C1, C2 between the connection nodes N1, N2 of the resistors R1 to R4 and the emitter terminals of the transistors Q7, Q8. A circuit in which a capacitor is connected between the nodes N1 and N2, an active filter using an operational amplifier, or the like may be used.
[0054]
Further, in the above-described embodiment, the offset canceling method in the amplifying unit composed of the variable gain amplifier and the filter circuit has been described. However, the present invention is an amplifying unit composed of a differential amplifier having a fixed gain and a filter circuit. It can also be applied to offset cancellation in
[0055]
In the above description, the case where the invention made by the present inventor is applied to a high frequency IC used in an EDGE-compatible mobile phone, which is the field of use behind the invention, has been described, but the present invention is not limited thereto. In general, it can be widely used for direct conversion high frequency processing semiconductor integrated circuits constituting a wireless communication system.
[0056]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0057]
That is, according to the present invention, in a direct conversion type communication semiconductor integrated circuit (high frequency IC) that requires a high gain amplifier circuit in which a plurality of variable gain amplifiers and low pass filters for amplifying a received signal are connected in multiple stages, The offset cancel operation of the high gain amplifier circuit can be completed within a predetermined time.
[0058]
Furthermore, according to the present invention, even when a high-gain amplifier circuit for amplifying a reception signal accompanied by amplitude modulation such as the EDGE system is provided with a high-order low-pass filter having a sharp frequency characteristic, The offset canceling operation can be completed within a time, thereby providing an advantageous effect that a highly versatile communication semiconductor integrated circuit capable of supporting a plurality of wireless communication systems can be provided.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a high-frequency IC and an entire system that constitute an EDGE-compatible mobile communication system as an example of a preferred system to which the present invention is applied.
FIG. 2 is a block diagram showing an embodiment of a high gain amplifier circuit.
FIG. 3 is a circuit diagram showing a specific example of a variable gain amplifier.
FIG. 4 is a timing chart showing ON / OFF timing of a switch at the time of offset cancellation in a high gain amplifier circuit.
FIG. 5 shows a high gain amplifying unit using a secondary filter as a low-pass filter when switches SW0 to SW2 in the filter are turned on and off at the same timing, and switches SW1 and SW2 are turned off at a timing different from SW0. It is a wave form diagram which shows the waveform which calculated | required the output of the back | latter stage amplifier at the time of controlling by simulation.
FIG. 6 is an explanatory diagram showing an example of a time slot in a GSM wireless communication system effective by applying the present invention.
FIG. 7 is a waveform diagram showing a signal waveform and an EDGE signal waveform in a GSM wireless communication system.
FIG. 8 is a frequency characteristic diagram showing filter characteristics required in a GSM wireless communication system and filter characteristics required in an EDGE wireless communication system.
[Explanation of symbols]
PGA1 to PGA3 variable gain amplifier
FLT1-FLT4 filter
PGA4 final amplifier
OFC1 to OFC3 offset correction circuit
100 Transmitting and receiving antenna
110 Switch for transmission / reception switching
120 high frequency filter
130 High Frequency Power Amplifier Circuit
140 High Frequency Oscillator (RFVCO)
200 high frequency IC
210 Receiving system circuit
211 Low noise amplifier
212 Receiving side mixer
213 High gain amplifier
220 Transmission system circuit
221 modulation circuit
222 Transmitter oscillator (TXVCO)
223 mixer
225 Phase detection circuit
226 charge pump
227 Loop filter
240 Control circuit
241,244 frequency divider
300 Baseband circuit

Claims (14)

A plurality of differential variable gain amplifiers and a plurality of filter circuits are connected in multiple stages, and includes an amplifier circuit that has an offset correction circuit capable of correcting each offset of the plurality of variable gain amplifiers and amplifies a received signal. A communication semiconductor integrated circuit,
Each of the plurality of filter circuits is configured as a second-order or higher-order filter circuit including a resistance element, and the switch element is connected in parallel with any of the resistance elements so that the switch element is turned on. In response to the offset correction of the corresponding variable gain amplifier by the offset correction circuit, the filter circuit in the next stage of the variable gain amplifier is switched to the low order filter, A semiconductor integrated circuit for communication, wherein the filter circuit is switched to a high-order filter after the correction is completed. 2. The communication semiconductor integrated circuit according to claim 1, wherein the filter circuit is a secondary filter circuit, and is changed to a primary filter circuit in response to the switch element being turned on. . 2. The amplifier circuit according to claim 1, wherein a variable gain amplifier and a filter circuit are connected in three stages, respectively, and a control circuit for sequentially performing offset correction by the offset correction circuit from the first stage amplifier to the subsequent stage is provided. 3. A semiconductor integrated circuit for communication according to 1 or 2. Corresponding to the first-stage variable gain amplifier among the plurality of variable gain amplifiers, a first switch element is provided for setting the differential input of the variable gain amplifier to the same potential, and the differential output is provided to the filter circuit. After the second switch element to be set to the same potential is provided, and the offset correction is performed in a state where the first and second switch elements and the order switching switch element are turned on at the time of offset correction, 4. The structure according to claim 1, wherein the second switching element is configured to be turned off before the switching element for switching the order is changed from an on state to an off state. 5. Semiconductor integrated circuit for communication. A mixer circuit that synthesizes a received signal and a signal of a predetermined frequency is connected to a preceding stage of the first stage variable gain amplifier among the plurality of variable gain amplifiers, and a differential is connected between the input terminals of the mixer circuit. The first switch element for making the input the same potential is provided, and when the offset of the first stage variable gain amplifier is corrected, the first switch element is turned on and the mixer circuit is included to correct the offset. The communication semiconductor integrated circuit according to claim 4, wherein the communication is performed. A mixer circuit that combines a received signal and a signal of a predetermined frequency to simultaneously perform frequency conversion and demodulation;
A differential variable gain amplifier that amplifies the demodulated received signal and a second-order or higher-order filter including a resistance element, and a switch element is connected in parallel with any of the resistance elements, and the switch element is turned on A plurality of filter circuits that are switchable to a low-order filter in response to the switching and provided with a switch element for setting the differential signal to the same potential. An amplifier circuit having an offset correction circuit capable of correcting the offset of the variable gain amplifier;
An offset correction method for a variable gain amplifier in a communication semiconductor integrated circuit comprising:
When correcting the offset of the variable gain amplifier at each stage, both the switch element for setting the differential signal to the same potential and the switch element for order switching are turned on, and the filter circuit is switched to a low-order filter. In this state, the offset is corrected, and then the switch element for making the differential signal the same potential is turned off to converge the output of the variable gain amplifier, and then the order switching switch element is turned off. An offset correction method for a variable gain amplifier, characterized in that the circuit is switched to a high-order filter and the output of the preceding variable gain amplifier is input to the subsequent circuit. The filter circuit is a second-order filter circuit, and the filter circuit is changed to a first-order filter circuit when the switching element for order switching is turned on during offset correction of the corresponding variable gain amplifier. 7. The variable gain amplifier offset correction method according to claim 6, wherein the second-order filter is changed after completion of the offset correction. 8. The offset correction method for a variable gain amplifier according to claim 6, wherein the offset correction by the offset correction circuit is sequentially executed from the first stage amplifier to the subsequent stage. When correcting the offset of the first stage variable gain amplifier among the plurality of variable gain amplifiers, the differential input of the mixer circuit is set to the same potential and the differential output of the mixer circuit is input to the first stage variable gain amplifier. 9. The offset correction method for a variable gain amplifier according to claim 6, wherein the offset correction of the first stage variable gain amplifier is performed including a mixer circuit. The offset correction method for a variable gain amplifier according to any one of claims 6 to 9, wherein an offset correction by the offset correction circuit is performed every time a reception operation is started. A first differential amplifier; a filter circuit coupled between an output of the first differential amplifier and an input of the second differential amplifier; and the first differential An offset correction circuit capable of correcting the offset of the type amplifier, and a communication semiconductor integrated circuit for amplifying a received signal,
The filter circuit is configured as a second-order or higher-order filter circuit including a resistance element, a switch element is connected in parallel with the resistance element, and a low-order filter is set in response to the switch element being turned on. When the offset correction of the first differential amplifier is performed by the offset correction circuit, the filter circuit is switched to a low-order filter, and after the offset correction is completed, the filter circuit is switched to a high-order filter. A semiconductor integrated circuit for communication, characterized in that it can be switched to. 12. The communication semiconductor integrated circuit according to claim 11, wherein the filter circuit is a secondary filter circuit, and is changed to a primary filter circuit in response to the switch element being turned on. . A mixer circuit that performs frequency conversion and demodulation by combining a received signal and a signal of a predetermined frequency;
An amplifying circuit for amplifying a demodulated received signal, between the first and second differential amplifiers, and the output of the first differential amplifier and the input of the second differential amplifier Is configured as a second-order or higher-order filter including a resistance element, connected in parallel with the resistance element, and can be changed to a low-order filter in response to turning it on. Amplification having a first switch element, a filter circuit provided with a second switch element for making the differential signal the same potential, and an offset correction circuit capable of correcting the offset of the first differential amplifier Circuit,
An offset correction method for a differential amplifier in a communication semiconductor integrated circuit comprising:
In a state where both the first switch element and the second switch element are turned on and the filter circuit is switched to a low-order filter, the offset of the first differential amplifier is corrected, Thereafter, the second switch element is turned off to converge the output of the differential amplifier, and then the first switch element is turned off to switch the filter circuit to a high-order filter. An offset correction method for a differential amplifier, wherein an output of the differential amplifier is supplied to an input of the second differential amplifier. The filter circuit is a secondary filter circuit, and the filter circuit is changed to a primary filter circuit in response to the first switch element being turned on during offset correction of the first differential amplifier. 14. The differential amplifier offset correction method according to claim 13, wherein the second-order filter is changed after the offset correction is completed.

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