CN110198284B - Correction circuit of wireless transceiver - Google Patents
Correction circuit of wireless transceiver Download PDFInfo
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- CN110198284B CN110198284B CN201910314313.7A CN201910314313A CN110198284B CN 110198284 B CN110198284 B CN 110198284B CN 201910314313 A CN201910314313 A CN 201910314313A CN 110198284 B CN110198284 B CN 110198284B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
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- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
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Abstract
The invention discloses a correction circuit of a wireless transceiver, which comprises a radio frequency input unit, a radio frequency receiving correction circuit, a baseband processing unit, a radio frequency transmitting correction circuit and a radio frequency output unit, wherein the radio frequency transmitting correction circuit comprises a radio frequency transmitting processing circuit, a radio frequency transmitting stabilizing circuit and a second phase shift correction circuit, and the second phase shift correction circuit comprises a phase shift input circuit, a phase shift common mode feedback circuit, a first load phase shift adjusting circuit, a second load phase shift adjusting circuit and a wake flow phase shift adjusting circuit. The phase shift correction circuit corrects the phase and the amplitude of the signal in the circuit transmission to be corrected, so that the problem of mismatching of the signal in the transmission process is solved, and the problem of signal-to-noise ratio deterioration caused by mismatching is solved.
Description
Technical Field
The invention belongs to the field of radio frequency circuits, and particularly relates to a correction circuit of a wireless transceiver.
Background
With the increasing demand of radio frequency applications and the continuous innovation of advanced CMOS manufacturing processes, radio transceivers have made higher demands for low power consumption of chips.
At present, in the development process of wireless transceivers, most attention is paid to the design of wireless radio frequency chip circuits, and most low-power-consumption circuits implemented in the wireless radio frequency chips are implemented by adopting digital circuits. As the functions of the wireless transceiver become more complex, the number of modules integrated by the chip system thereof becomes more and more, so that the volume of the whole wireless radio frequency chip becomes larger and larger. The superheterodyne wireless transceiver is a relatively wide transceiver used at present, and compared with the superheterodyne wireless transceiver, the transceiver with direct frequency conversion has a smaller volume, does not need an additional off-chip filter, and has lower power consumption.
However, the direct conversion wireless transceiver has some problems, in which the signal-to-noise ratio of the wireless transceiver is seriously deteriorated due to the mismatch of signals during transmission.
Disclosure of Invention
To solve the above problems in the prior art, the present invention provides a phase shift correction circuit and a correction circuit of a wireless transceiver thereof.
An embodiment of the present invention provides a phase shift correction circuit, where the phase shift correction circuit includes:
a phase shift input circuit, a phase shift common mode feedback circuit, a first load phase shift adjusting circuit, a second load phase shift adjusting circuit, a wake flow phase shift adjusting circuit,
the phase shift input circuit is used for extracting a phase shift differential signal from a first input signal, a second input signal, a third input signal and a fourth input signal to obtain a first phase shift differential signal and a second phase shift differential signal;
the phase-shift common-mode feedback circuit is connected with the phase-shift input circuit and is used for carrying out common-mode feedback processing on the first phase-shift differential signal and the second phase-shift differential signal, and obtaining and outputting a control signal when a common-mode working voltage point of the phase-shift input circuit is determined;
the first load phase shift adjusting circuit is connected with the phase shift input circuit and the phase shift common mode feedback circuit, and is used for carrying out amplitude and phase correction processing on the first phase shift differential signal according to the control signal to obtain a first phase shift correction differential signal;
the second load phase shift adjusting circuit is connected with the phase shift input circuit and the phase shift common mode feedback circuit, and is used for carrying out amplitude and phase correction processing on the second phase shift differential signal according to the control signal to obtain a second phase shift correction differential signal;
the wake phase shift adjusting circuit is connected to the phase shift input circuit, and is configured to perform correction processing on the wake signal on the first phase shift corrected differential signal and the second phase shift corrected differential signal to obtain a first output signal, a second output signal, a third output signal, and a fourth output signal.
In one embodiment of the present invention, the phase shift input circuit includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2, a resistor R3, and a resistor R4, the first load phase shift adjustment circuit includes a transistor M5, a capacitor bank C3, a resistor R5, and a current source V2, the second load phase shift adjustment circuit includes a transistor M6, a capacitor bank C4, a resistor R6, and a current source V3, the tail current phase shift adjustment circuit includes a resistor R1, a resistor R2, and a current source V3, wherein,
a gate of the transistor M1 is connected to the input terminal of the first input signal, a drain of the transistor M1 is connected to one end of the capacitor C1, one end of the resistor R3, and a drain of the transistor M3, a source of the transistor M1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the input terminal of the current source V1 and one end of the resistor R2, an output terminal of the current source V1 is grounded, the other end of the resistor R2 is connected to the source of the transistor M2, a gate of the transistor M2 is connected to the input terminal of the second input signal, a drain of the transistor M2 is connected to one end of the capacitor C2, one end of the resistor R4, and a drain of the transistor M4, the other end of the resistor R4 is connected to the other end of the resistor R3, the other end of the capacitor C1, the other end of the capacitor C2, and the other end of, The input end of the phase shift common mode feedback circuit is connected, the gate of the transistor M3 is connected to the input end of the third input signal, the source of the transistor M3 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to one end of the capacitor bank C3, the output end of the current source V2, and the drain of the transistor M5, the gate of the transistor M5 is connected to the gate of the transistor M6 and the output end of the phase shift common mode feedback circuit, the gate of the transistor M4 is connected to the input end of the fourth input signal, the source of the transistor M4 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to one end of the capacitor bank C4, the output end of the current source V3, and the drain of the transistor M6, the other end of the capacitor bank C3, the input end of the current source V2, the source M5, the source of the capacitor, The other end of the capacitor bank C4, the input end of the current source V3, and the source of the transistor M6 are all connected to a power supply VDD.
In an embodiment of the present invention, the capacitor bank C3 and the capacitor bank C4 are both variable capacitor arrays, and each variable capacitor array includes a plurality of switched capacitor banks connected in parallel, each switched capacitor bank includes a switch and a capacitor, and the switch is connected in series with the capacitor.
In one embodiment of the present invention, the phase shift common mode feedback circuit comprises a transistor M7, a transistor M8, a transistor M9, a transistor M10, a resistor R7, a resistor R8, a capacitor C5, a current source V4, wherein,
a gate of the transistor M7 is connected to one end of the capacitor C1, one end of the capacitor C2, one end of the resistor R3, and one end of the resistor R4, a source of the transistor M7 is connected to the input of the current source V4, a source of the transistor M8, the drain of the transistor M7 is connected with the drain of the transistor M9, the gate of the transistor M5, the gate of the transistor M6, the source of the transistor M9 is connected with the source of the transistor M10 and one end of the resistor R8, the gate of the transistor M9 is connected with the gate of the transistor M10, the drain of the transistor M10, the drain of the transistor M8, the gate of the transistor M8 is connected to the other end of the resistor R8, one end of the resistor R7, and one end of the capacitor C5, the output end of the current source V4, the other end of the resistor R7 and the other end of the capacitor C5 are all grounded.
In one embodiment of the present invention, the current source V1, the current source V2, the current source V3 and the current source V4 are all variable current sources.
In one embodiment of the present invention, the resistor R1, the resistor R2, the resistor R5, the resistor R6 and the resistor R7 are all variable resistors.
Yet another embodiment of the present invention provides a correction circuit for a wireless transceiver, the correction circuit comprising a number of phase shift correction circuits as described in any one of the above, the correction circuit comprising a first phase shift correction circuit and a second phase shift correction circuit.
In one embodiment of the present invention, the calibration circuit further comprises a radio frequency input unit, a radio frequency receiving calibration circuit, a baseband processing unit, a radio frequency transmitting calibration circuit, a radio frequency output unit, wherein,
the radio frequency input unit is used for generating a radio frequency signal and inputting the radio frequency signal to the radio frequency receiving and correcting circuit;
the radio frequency receiving and correcting circuit is connected with the radio frequency input unit and is used for receiving and correcting the radio frequency signal to obtain a first correcting signal, and the first correcting signal comprises a first sub-correcting signal and a second sub-correcting signal;
the baseband processing unit is connected with the radio frequency receiving and correcting circuit and is used for carrying out digital baseband processing on the first correcting signal to obtain a baseband processing signal;
the radio frequency emission correction circuit is connected with the baseband processing unit and is used for correcting and emitting the baseband processing signal to obtain a second correction signal;
and the radio frequency output unit is connected with the radio frequency emission correction circuit and used for receiving and outputting the second correction signal.
In one embodiment of the invention, the rf receiving calibration circuit includes a low noise amplifier circuit, an I-path rf receiving circuit, a Q-path rf receiving circuit, an rf receiving stabilizing circuit, and a phase shifting circuit, wherein,
the low-noise amplifying circuit is connected with the radio frequency input unit and is used for amplifying the radio frequency signal to obtain an amplified radio frequency signal, and the amplified radio frequency signal comprises an I-path radio frequency signal and a Q-path radio frequency signal;
the I path of radio frequency receiving circuit is connected with the low-noise amplifying circuit and is used for carrying out first processing on the I path of radio frequency signals to obtain first processing signals, and the first processing sequentially comprises frequency shifting, stabilizing, first filtering, second amplifying, second filtering and analog-to-digital conversion;
the Q-path radio frequency receiving circuit is connected with the low-noise amplifying circuit and is used for carrying out second processing on the Q-path radio frequency signal to obtain a second processing signal, and the second processing sequentially comprises frequency shifting, stabilizing, first filtering, second amplifying, second filtering and analog-to-digital conversion processing;
the radio frequency receiving stabilizing circuit is connected with the baseband processing unit and is used for performing receiving stabilizing processing on the baseband processing signal after the baseband processing unit performs digital baseband processing on the first processing signal and the second processing signal to obtain an I-path radio frequency receiving stabilizing signal and a Q-path radio frequency receiving stabilizing signal, wherein the receiving stabilizing processing sequentially comprises digital-to-analog conversion, clock stabilizing processing and local oscillator stabilizing processing;
the phase shift circuit is connected with the radio frequency receiving stabilizing circuit and the first phase shift correction circuit, and is configured to perform phase shift processing on the I-path radio frequency receiving stabilizing signal and the Q-path radio frequency receiving stabilizing signal to obtain the first input signal, the second input signal, the third input signal, and the fourth input signal, and input the first input signal, the second input signal, the third input signal, and the fourth input signal to the first phase shift correction circuit;
the I-path radio frequency receiving circuit is further connected to the first phase shift correction circuit, and is further configured to perform the first processing on the first output signal and the second output signal to obtain the first sub-correction signal;
the Q-path radio frequency receiving circuit is further connected to the first phase shift correction circuit, and is further configured to perform the second processing on the third output signal and the fourth output signal to obtain the second sub-correction signal.
In one embodiment of the invention, the radio frequency emission correction circuit comprises a radio frequency emission processing circuit, a radio frequency emission stabilizing circuit, wherein,
the radio frequency transmitting processing circuit is connected with the baseband processing unit and is used for carrying out third processing on the baseband processing signal to obtain a third processing signal, and the third processing sequentially comprises digital-to-analog conversion, first filtering, first amplification, frequency shifting, stabilization, second filtering and power amplification;
the radio frequency transmitting stabilization circuit is connected with the baseband processing unit and the second phase shift correction circuit, and is configured to perform transmitting stabilization processing on the baseband processing signal to obtain a fifth input signal, a sixth input signal, a seventh input signal, and an eighth input signal, and input the fifth input signal, the sixth input signal, the seventh input signal, and the eighth input signal to the second phase shift correction circuit, where the transmitting stabilization processing sequentially includes digital-to-analog conversion, clock stabilization processing, and local oscillator stabilization processing;
the radio frequency transmitting and processing circuit is further connected to the second phase shift correction circuit, and is further configured to perform the third processing according to a fifth output signal, a sixth output signal, a seventh output signal, and an eighth output signal obtained by the second phase shift correction circuit, so as to obtain a second correction signal.
Compared with the prior art, the invention has the beneficial effects that:
1. the phase shift correction circuit corrects the phase and the amplitude of the signal in the circuit transmission to be corrected, so that the problem of mismatching of the signal in the transmission process is solved, and the problem of signal-to-noise ratio deterioration caused by mismatching is solved.
2. The invention adds phase shift correction circuits in the receiving and transmitting links of the wireless transceiver respectively to correct the IQ signals mismatched in the receiving and transmitting links of the wireless transceiver, thereby solving the problem of IQ signal mismatch in the wireless transceiver, wherein the IQ signal mismatch comprises IQ signal amplitude imbalance and phase imbalance, and further solving the problem of deterioration of the signal-to-noise ratio of the wireless transceiver caused by the IQ mismatch problem.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic circuit diagram of a phase shift correction circuit according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of another circuit structure of a phase shift correction circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a phase shift common mode feedback circuit in a phase shift correction circuit according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a variable capacitor array in a phase shift correction circuit according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a calibration circuit of a wireless transceiver according to an embodiment of the present invention;
fig. 6 is a schematic circuit diagram of a radio frequency receiving calibration circuit in a calibration circuit of a wireless transceiver according to an embodiment of the present invention;
fig. 7 is an IQ phase mismatch diagram of a conventional wireless transceiver according to an embodiment of the present invention;
fig. 8 is a schematic circuit diagram of an rf transmission calibration circuit in a calibration circuit of a wireless transceiver according to an embodiment of the present invention;
fig. 9 is a schematic circuit diagram of another circuit structure of a calibration circuit of a wireless transceiver according to an embodiment of the present invention.
Description of the reference numerals
A phase shift correction circuit 10; a radio frequency input unit 20; a radio frequency reception correction circuit 30; a baseband processing unit 40; a radio frequency emission correction circuit 50; a radio frequency output unit 60; a phase shift input circuit 101; a phase-shifted common mode feedback circuit 102; a first load phase shift adjustment circuit 103; a second load phase shift adjustment circuit 104; a wake phase shift adjusting circuit 105; a low-noise amplification circuit 301; an I-path radio frequency receiving circuit 302; q-path rf receiving circuit 303; a radio frequency reception stabilizing circuit 304; a phase shift circuit 305; a first phase shift correction circuit 306; a radio frequency transmission processing circuit 501; a radio frequency transmit stabilization circuit 502; a second phase shift correction circuit 503.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 2, fig. 3, and fig. 4, fig. 1 is a schematic circuit structure diagram of a phase shift correction circuit according to an embodiment of the present invention, fig. 2 is another schematic circuit structure diagram of a phase shift correction circuit according to an embodiment of the present invention, fig. 3 is a schematic circuit structure diagram of a phase shift common mode feedback circuit in a phase shift correction circuit according to an embodiment of the present invention, and fig. 4 is a schematic circuit structure diagram of a variable capacitor array in a phase shift correction circuit according to an embodiment of the present invention. An embodiment of the present invention provides a phase shift correction circuit, including:
a phase shift input circuit 101, configured to extract a phase shift differential signal from a first input signal, a second input signal, a third input signal, and a fourth input signal to obtain a first phase shift differential signal and a second phase shift differential signal;
the phase-shift common-mode feedback circuit 102 is connected with the phase-shift input circuit 101, and is used for performing common-mode feedback processing on the first phase-shift differential signal and the second phase-shift differential signal, and obtaining and outputting a control signal when a common-mode working point of the phase-shift input circuit 101 is determined;
the first load phase shift adjusting circuit 103 is connected to the phase shift input circuit 101 and the phase shift common mode feedback circuit 102, and is configured to perform amplitude and phase correction processing on the first phase shift differential signal according to the control signal to obtain a first phase shift correction differential signal;
the second load phase shift adjusting circuit 104 is connected to the phase shift input circuit 101 and the phase shift common mode feedback circuit 102, and is configured to perform amplitude and phase correction processing on the second phase shift differential signal according to the control signal to obtain a second phase shift correction differential signal;
and the wake phase shift adjusting circuit 105 is connected to the phase shift input circuit 101, and is configured to perform correction processing on the wake signal on the first phase shift corrected differential signal and the second phase shift corrected differential signal to obtain a first output signal, a second output signal, a third output signal, and a fourth output signal.
The phase shift input circuit 101 includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2, a resistor R3, and a resistor R4, the phase shift common mode feedback circuit 102 includes a transistor M7, a transistor M8, a transistor M9, a transistor M10, a resistor R7, a resistor R8, a capacitor C5, and a current source V4, the first load phase shift adjustment circuit 103 includes a transistor M5, a capacitor group C3, a resistor R5, and a current source V2, the second load phase shift adjustment circuit 104 includes a transistor M6, a capacitor group C4, a resistor R6, and a current source V3, the tail current phase shift adjustment circuit 105 includes a resistor R1, a resistor R2, and a current source V3, and the circuit connection relationship between the internal modules is as described above, which will not be described in detail.
Preferably, the current source V1, the current source V2, the current source V3 and the current source V4 are all variable current sources, the resistor R1, the resistor R2, the resistor R5, the resistor R6 and the resistor R7 are all variable resistors, and the capacitor group C3 and the capacitor group C4 are all variable capacitor arrays.
Specifically, in the present embodiment, the phase shift input circuit 101 extracts the phase shift differential signal from the first input signal, the second input signal, the third input signal, and the fourth input signal to obtain the first phase shift differential signal and the second phase shift differential signal. For example, in this embodiment, the first input signal is a Q-path signal in the wireless transceiver, the second input signal is a signal having a phase difference of 180 ° from the Q-path signal in the wireless transceiver, the third input signal is an I-path signal in the wireless transceiver, and the fourth input signal is a signal having a phase difference of 180 ° from the I-path signal in the wireless transceiver, such four signals form an input signal of the phase shift input circuit 101, and the phase shift input circuit 101 performs phase shift differential signal extraction on the four input signals to obtain a first phase shift differential signal and a second phase shift differential signal.
Further, the phase shift common mode feedback circuit 102, the resistor R3 and the resistor R4 in the phase shift input circuit 101, the transistor M5 in the first load phase shift adjusting circuit 103, and the transistor M6 in the second load phase shift adjusting circuit 104 form a common mode feedback loop, the phase shift common mode feedback circuit 102 extracts a common mode signal in the circuit through such a loop, and then performs feedback processing on the common mode signal, so as to control a common mode operating voltage point of the phase shift correction circuit 10, and after the common mode operating voltage point of the phase shift correction circuit 10 is determined, the phase shift common mode feedback circuit generates a control signal, so that subsequent correction work is performed after the phase shift correction circuit 10 is stabilized at the common mode operating voltage point.
Further, the first load phase shift adjusting circuit 103 and the second load phase shift adjusting circuit 104 are both phase shift amplitude and phase adjustable circuits, a resistor R5 and a current source V2 in the first load phase shift adjusting circuit 103, and a resistor R6 and a current source V3 in the second load phase shift adjusting circuit 104 respectively form an amplitude tuning circuit to adjust amplitude mismatch of an input signal of the phase shift correcting circuit 10, a capacitor group C3 in the first load phase shift adjusting circuit 103 and a capacitor group C4 in the second load phase shift adjusting circuit 104 respectively form a phase tunable circuit to adjust phase mismatch of an input signal of the phase shift correcting circuit 10. The first load phase shift adjusting circuit 103 is connected to the phase shift input circuit 101 through a resistor R5, and corrects the amplitude and phase of the extracted first phase-shifted differential signal; the second load phase shift adjusting circuit 104 is connected to the phase shift input circuit 101 through a resistor R6, and corrects the amplitude and phase of the extracted second phase-shifted differential signal.
Referring to fig. 4 again, the capacitor bank C3 and the capacitor bank C4 have the same structure and are both variable capacitor arrays, each variable capacitor array includes a plurality of switched capacitor banks, the switched capacitor banks are connected in parallel, each switched capacitor bank includes a switch and a capacitor, and the switches are connected in series with the capacitors. Specifically, the capacitor bank C3 and a plurality of switch capacitor banks in the capacitor bank C4 comprise a capacitor Cu1And switch S11A first switch capacitor and a capacitor C connected in seriesu2And switch S22A second switched capacitor, a capacitor Cu3And switch S33The first switched capacitor, the second switched capacitor and the third switched capacitor are connected in parallel between a power supply VDD and a resistor R5 for a capacitor bank C3, and the first switched capacitor, the second switched capacitor and the third switched capacitor are connected in parallel between the power supply VDD and the resistor R6 for a capacitor bank C4. By controlling switch S11Switch S22Switch S33Thereby adjusting the capacitance values of capacitor bank C3 and capacitor bank C4. Wherein, the capacitor Cu1Capacitor Cu2Capacitor Cu3= 1:2:4, in the present embodiment, the capacitor Cu1Is Cu，CuIs a unit capacitance, then a capacitance Cu2Is 2CuCapacitor Cu3Is 4Cu。
Further, the wake-up phase shift adjusting circuit 105 is configured to adjust the wake-up signals of the first phase-shifted differential signal and the second phase-shifted differential signal extracted by the phase shift correcting circuit 10, wherein the resistor R1, the resistor R2, and the current source V1 form an amplitude tuning circuit, so as to achieve fine tuning of the amplitude of the input signal of the phase shift correcting circuit 10.
In this embodiment, the phase shift common mode feedback circuit 102 in the phase shift correction circuit 10 stabilizes the circuit at a common mode voltage point to work, and the first load phase shift adjustment circuit 103, the second load phase shift adjustment circuit 104, and the wake-up phase shift adjustment circuit 105 perform phase and amplitude correction on the extracted signal of the input signal of the phase shift correction circuit 10, so as to solve the mismatch problem of the signal in the transmission process, and further solve the problem of signal-to-noise ratio degradation caused by mismatch.
Please refer to fig. 5, 6, 7, 8, and 9, in which fig. 5 is a schematic circuit structure diagram of a calibration circuit of a wireless transceiver according to an embodiment of the present invention, fig. 6 is a schematic circuit structure diagram of a radio frequency receiving calibration circuit in the calibration circuit of the wireless transceiver according to the embodiment of the present invention, fig. 7 is a schematic IQ phase mismatch diagram of a conventional wireless transceiver according to the embodiment of the present invention, fig. 8 is a schematic circuit structure diagram of a radio frequency transmitting calibration circuit in the calibration circuit of the wireless transceiver according to the embodiment of the present invention, and fig. 9 is another schematic circuit structure diagram of the calibration circuit of the wireless transceiver according to the embodiment of the present invention. The embodiment of the present invention further provides a calibration circuit of a wireless transceiver, which includes a plurality of phase shift calibration circuits 10 as above, and the plurality of phase shift calibration circuits includes a first phase shift calibration circuit 306 and a second phase shift calibration circuit 503.
Specifically, the first phase shift correction circuit 306 and the second phase shift correction circuit 503 are respectively connected to the receiving link and the transmitting link of the wireless transceiver, and then perform correction processing on the transmission signals of the receiving link and the transmitting link, respectively, so as to solve the problem of mismatch of the signals in the transmission process.
Further, the calibration circuit of the wireless transceiver in this embodiment further includes:
a radio frequency input unit 20 for generating a radio frequency signal and inputting the radio frequency signal to the radio frequency receiving and correcting circuit 30;
the radio frequency receiving and correcting circuit 30 is connected to the radio frequency input unit 20 and configured to receive and correct the radio frequency signal to obtain a first correction signal, where the first correction signal includes a first sub-correction signal and a second sub-correction signal;
the baseband processing unit 40 is connected to the radio frequency receiving and correcting circuit 30, and is configured to perform digital baseband processing on the first correction signal to obtain a baseband processing signal;
the radio frequency emission correction circuit 50 is connected with the baseband processing unit 40 and is used for correcting and emitting the baseband processing signal to obtain a second correction signal;
and a radio frequency output unit 60, connected to the radio frequency transmission correction circuit 50, for receiving and outputting the second correction signal.
The rf receiving and correcting circuit 30 includes a low-noise amplifier circuit 301, where the low-noise amplifier circuit 301 includes a low-noise amplifier LNA, and is configured to amplify the rf signal input by the rf input unit 20, where the amplified rf signal includes an I-path rf signal and a Q-path rf signal, and the low-noise amplifier LNA can maintain good noise performance.
The I-channel radio frequency receiving circuit 302 is connected to the low-noise amplifying circuit 301, and sequentially includes a mixing circuit Mix1, a low-pass filter LPF1, a gain amplifier PGA1, a low-pass filter LPF2, and an analog-to-digital converter ADC1, and sequentially performs first processing including frequency shifting, stabilization, first filtering, second amplification, second filtering, and analog-to-digital conversion on the I-channel radio frequency signal, and the I-channel radio frequency receiving circuit 302 obtains a first processing signal after the first processing.
The Q-path radio frequency receiving circuit 303 is connected to the low-noise amplifying circuit 301, and sequentially includes a mixing circuit Mix2, a low-pass filter LPF3, a gain amplifier PGA2, a low-pass filter LPF4, and a digital-to-analog converter ADC2, and sequentially performs second processing including frequency shifting, stabilization, first filtering, second amplification, second filtering, and analog-to-digital conversion processing on the Q-path radio frequency signal, and the Q-path radio frequency receiving circuit 303 obtains a second processing signal after the second processing.
Referring to FIG. 7, r (t) in FIG. 7 is the RF signal input function, SI(t) is the frequency shift function of the I-channel video signal, SQ(t) is the frequency shift function of Q paths of radio frequency signals, HI (f) represents the transmission function of the I path receiving link composed of the I path low pass filter LPF1, the gain amplifier PGA1, the low pass filter LPF2 and the analog-to-digital converter ADC1, and HQ (f) represents the transmission function of the Q path receiving link composed of the Q path low pass filter LPF3, the gain amplifier PGA2, the low pass filter LPF4 and the digital-to-analog converter ADC2,x I(t) is the output function of the I-path radio frequency signal,x Qand (t) is an output function of the Q paths of radio frequency signals, and the I path of radio frequency signals and the Q path of radio frequency signals have mismatching of amplitude g and phase phi.
The radio frequency receiving and stabilizing circuit 304 is connected to the baseband processing unit 304, and sequentially includes a digital-to-analog converter DAC1, a voltage-controlled oscillator VCXO1, and a phase-locked loop PLL1, the baseband processing unit 304 receives the first processed signal and the second processed signal, performs digital baseband processing on the first processed signal and the second processed signal to obtain a baseband processed signal, the baseband processed signal includes an IQ mismatch signal obtained by processing the first processed signal and the second processed signal by a baseband, and the radio frequency receiving and stabilizing circuit 304 receives the mismatch signal, and is configured to perform receiving and stabilizing processing including the digital-to-analog converter DAC1, the voltage-controlled oscillator VCXO1, and the phase-locked loop PLL1 on the mismatch signal of the receiving link of the I path and the Q path.
The phase shift circuit 305, which is a phase shift converter of 0/90 in this embodiment, performs a phase shift process on the mismatch signal input by the radio frequency receiving and stabilizing circuit 304 to obtain a first input signal, a second input signal, a third input signal, and a fourth input signal, and inputs the first input signal, the second input signal, the third input signal, and the fourth input signal to the first phase shift correction circuit 306. The first input signal and the second input signal are a set of phase-shifted differential signals of the Q-path, the third input signal and the fourth input signal are a set of phase-shifted differential signals of the I-path, and local oscillation signals required by the wireless transceiver of this embodiment can be generated by the phase-shifting circuit 305.
The first phase shift correction circuit 306 performs the correction processing on the first input signal, the second input signal, the third input signal, and the fourth input signal by the phase shift correction circuit 10 as described above to obtain a first output signal, a second output signal, a third output signal, and a fourth output signal, inputs the first output signal and the second output signal to the I-path rf receiving circuit 302 for the first processing to obtain a first sub-correction signal, and inputs the third output signal and the fourth output signal to the Q-path rf receiving circuit 302 for the second processing to obtain a second sub-correction signal.
The invention of the rf receiving and correcting circuit 30 of this embodiment is to receive the mismatch signal sent from the baseband through the rf receiving and stabilizing circuit 304, input the mismatch signal to the phase shift circuit 305 for phase shift processing, and then perform the correction processing on the phase-shifted mismatch signal by the first phase shift correcting circuit 306, so that the rf receiving and correcting circuit 30 outputs the corrected first correction signal, thereby solving the problem of signal mismatch of the rf signal receiving link. Other parts of the rf receive calibration circuit 30 are not the invention of the present application, and therefore, the circuit connection and the operation principle thereof will not be described in detail, and for the specific circuit connection, refer to fig. 9.
The baseband processing unit 40 implements digital baseband processing on the first correction signal by using a digital circuit method, and the digital baseband processing of the baseband processing unit 40 in this embodiment is not the invention of the present application, so detailed description of circuit connection and working principle thereof is not provided herein, and for specific circuit connection, refer to fig. 6. The baseband processing unit 40 detects the mismatch degree of the IQ signal in the rf receiving and correcting circuit 30 through the first correction signal, and sends the IQ mismatch signal to the rf receiving and correcting circuit 30 and the rf transmitting and correcting circuit 50 for performing correction processing on the mismatch signal of the IQ receiving link and the transmitting link.
The radio frequency emission correction circuit 50 includes a radio frequency emission processing circuit 501, the radio frequency emission processing circuit 501 includes a digital-to-analog converter DAC2, a low pass filter LPF5, a gain control amplifier AGC, a mixer circuit Mix3, a low pass filter LPF6, and a power amplifier PA in sequence, third processing including digital-to-analog conversion, first filtering, first amplification, frequency shifting, stabilization, second filtering, and power amplification is performed on a baseband processing signal sent by the baseband processing unit 40 in sequence, and the radio frequency emission correction circuit 50 obtains a third processing signal through the third processing;
the rf transmitting and stabilizing circuit 502 sequentially includes a digital-to-analog converter DAC3, a voltage-controlled oscillator VCXO2, and a phase-locked loop PLL2, the baseband processing unit 304 performs digital baseband processing on the rf receiving and correcting circuit 30 to obtain a baseband processing signal, inputs a mismatch signal in the baseband processing signal to the rf transmitting and stabilizing circuit 502, the rf transmitting and stabilizing circuit 502 receives the mismatch signal, and performs receiving and stabilizing processing on the mismatch signal including the digital-to-analog converter DAC1, the voltage-controlled oscillator VCXO1, and the phase-locked loop PLL1 to obtain a fifth input signal, a sixth input signal, a seventh input signal, and an eighth input signal, wherein, because the signal of the rf transmitting and correcting circuit 50 can implement separate processing of I-path and Q-path signals and can also perform simultaneous processing on the I-path and Q-path signals, in this embodiment, the I-path and Q-path signals are simultaneously processed, and in the input end of the second phase shift correcting circuit 503, the input terminal of the fifth input signal is connected to the gate of the transistor M1 in the second phase shift correction circuit 503, the input terminal of the sixth input signal is connected to the gate of the transistor M2 in the second phase shift correction circuit 503, the input terminal of the seventh input signal is connected to the gate of the transistor M3 in the second phase shift correction circuit 503, the input terminal of the eighth input signal is connected to the gate of the transistor M4 in the second phase shift correction circuit 503, the input terminals of the fifth input signal and the eighth input signal are both input with the first signal, the input terminals of the sixth input signal and the seventh input signal are both input with the second signal, and the first signal and the second signal are a set of phase-shifted differential signals output from the radio frequency emission stabilization circuit 502.
The second phase shift correction circuit 503 performs the correction processing on the fifth input signal, the sixth input signal, the seventh input signal, and the eighth input signal by the above phase shift correction circuit 10 to obtain a fifth output signal, a sixth output signal, a seventh output signal, and an eighth output signal, inputs the fifth output signal, the sixth output signal, the seventh output signal, and the eighth output signal to the rf transmission processing circuit 501, and performs the third processing to obtain a second correction signal.
The invention of the rf transmission correction circuit 50 of this embodiment is that the rf transmission stabilizing circuit 502 receives the mismatch signal sent from the baseband, and inputs the mismatch signal to the second phase shift correction circuit 503 for correction processing, so that the rf transmission correction circuit 50 outputs the corrected second correction signal, thereby solving the problem of signal mismatch of the transmission link. Other parts of the rf transmission calibration circuit 50 are not the invention of the present application, and therefore, the circuit connection and the operation principle thereof will not be described in detail, and for the specific circuit connection, refer to fig. 9.
In summary, in the present embodiment, phase shift correction circuits are respectively added in the receiving and transmitting links of the wireless transceiver to correct mismatched IQ signals in the receiving and transmitting links, so as to solve the problem of IQ signal mismatch in the wireless transceiver, where the IQ signal mismatch includes an imbalance of the amplitude and an imbalance of the phase of the IQ signal, and further solve the problem of deterioration of the signal-to-noise ratio of the wireless transceiver due to the IQ mismatch problem.
In this embodiment, the first input signal, the second input signal, the third input signal, and the fourth input signal input by the first phase shift correction circuit 306 and the fifth input signal, the sixth input signal, the seventh input signal, and the eighth input signal input by the second phase shift correction circuit 503 are different signals processed by the first phase shift correction circuit 306 and the second phase shift correction circuit 503, and are respectively the first input signal, the second input signal, the third input signal, and the fourth input signal described in the phase shift correction circuit 10, and the correction processing by the up shift correction circuit 10 is performed. Similarly, to illustrate that the signals output by the first phase shift correction circuit 306 and the second phase shift correction circuit 503 are different, in this embodiment, the output signal of the first phase shift correction circuit 306 is the first output signal, the second output signal, the third output signal, and the fourth output signal, and the output signal of the second phase shift correction circuit 503 is the fifth output signal, the sixth output signal, the seventh output signal, and the eighth output signal, which are respectively the first output signal, the second output signal, the third output signal, and the fourth output signal of the phase shift correction circuit 10.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (7)
1. A calibration circuit of a wireless transceiver comprises a radio frequency input unit (20), a radio frequency receiving calibration circuit (30), a baseband processing unit (40), a radio frequency transmitting calibration circuit (50) and a radio frequency output unit (60), wherein,
the radio frequency input unit (20) is used for generating a radio frequency signal and inputting the radio frequency signal to the radio frequency receiving and correcting circuit (30);
the radio frequency receiving and correcting circuit (30) is connected with the radio frequency input unit (20) and is used for receiving and correcting the radio frequency signal to obtain a first correcting signal, and the first correcting signal comprises a first sub-correcting signal and a second sub-correcting signal;
the baseband processing unit (40) is connected to the radio frequency receiving and correcting circuit (30) and configured to perform digital baseband processing on the first correction signal to obtain a baseband processing signal;
the radio frequency emission correction circuit (50) is connected with the baseband processing unit (40) and is used for correcting and emitting the baseband processing signal to obtain a second correction signal; the radio frequency output unit (60) is connected with the radio frequency emission correction circuit (50) and is used for receiving and outputting the second correction signal;
wherein the radio frequency transmission correction circuit (50) comprises a radio frequency transmission processing circuit (501), a radio frequency transmission stabilization circuit (502) and a second phase shift correction circuit (503),
the radio frequency transmitting and processing circuit (501) is connected with the baseband processing unit (40) and is used for performing third processing on the baseband processing signal to obtain a third processing signal, wherein the third processing sequentially comprises digital-to-analog conversion, first filtering, first amplification, frequency shifting, stabilization, second filtering and power amplification;
the radio frequency transmitting stabilization circuit (502) is connected with the baseband processing unit (40) and is used for transmitting stabilization processing on the baseband processing signal to obtain a fifth input signal, a sixth input signal, a seventh input signal and an eighth input signal, wherein the transmitting stabilization processing sequentially comprises digital-to-analog conversion, clock stabilization processing and local oscillator stabilization processing;
the second phase shift correction circuit (503) is connected to the radio frequency transmission stabilization circuit (502), and is configured to perform correction processing on the fifth input signal, the sixth input signal, the seventh input signal, and the eighth input signal to obtain a fifth output signal, a sixth output signal, a seventh output signal, and an eighth output signal;
the radio frequency transmission processing circuit (501) is further connected to the second phase shift correction circuit (503), and is further configured to perform the third processing according to the fifth output signal, the sixth output signal, the seventh output signal, and the eighth output signal to obtain the second correction signal;
wherein the second phase shift correction circuit (503) comprises a phase shift input circuit (101), a phase shift common mode feedback circuit (102), a first load phase shift adjusting circuit (103), a second load phase shift adjusting circuit (104), and a wake phase shift adjusting circuit (105), wherein,
the phase shift input circuit (101) is configured to extract a phase shift differential signal from the fifth input signal, the sixth input signal, the seventh input signal, and the eighth input signal to obtain a first phase shift differential signal and a second phase shift differential signal;
the phase-shift common-mode feedback circuit (102) is connected with the phase-shift input circuit (101) and is used for performing common-mode feedback processing on the first phase-shift differential signal and the second phase-shift differential signal, and obtaining and outputting a control signal when a common-mode working voltage point of the phase-shift input circuit (101) is determined;
the first load phase shift adjusting circuit (103) is connected to the phase shift input circuit (101) and the phase shift common mode feedback circuit (102), and is configured to perform amplitude and phase correction processing on the first phase shift differential signal according to the control signal to obtain a first phase shift correction differential signal;
the second load phase shift adjusting circuit (104) is connected to the phase shift input circuit (101) and the phase shift common mode feedback circuit (102), and is configured to perform amplitude and phase correction processing on the second phase shift differential signal according to the control signal to obtain a second phase shift corrected differential signal;
the wake-up phase shift adjusting circuit (105) is connected to the phase shift input circuit (101), and configured to perform correction processing on the wake-up signal on the first phase shift corrected differential signal and the second phase shift corrected differential signal to obtain a fifth output signal, a sixth output signal, a seventh output signal, and an eighth output signal.
2. The calibration circuit of claim 1, wherein the RF reception calibration circuit (30) comprises a low noise amplifier circuit (301), an I-way RF receiver circuit (302), a Q-way RF receiver circuit (303), an RF reception stabilization circuit (304), a phase shift circuit (305), and a first phase shift calibration circuit (306), wherein,
the low-noise amplification circuit (301) is connected to the radio frequency input unit (20) and is configured to amplify the radio frequency signal to obtain an amplified radio frequency signal, where the amplified radio frequency signal includes an I-path radio frequency signal and a Q-path radio frequency signal;
the I-path radio frequency receiving circuit (302) is connected with the low-noise amplifying circuit (301) and is used for carrying out first processing on the I-path radio frequency signal to obtain a first processing signal, and the first processing sequentially comprises frequency shifting, stabilizing, first filtering, second amplifying, second filtering and analog-to-digital conversion;
the Q-path radio frequency receiving circuit (303) is connected with the low-noise amplifying circuit (301) and is used for carrying out second processing on the Q-path radio frequency signal to obtain a second processing signal, and the second processing sequentially comprises frequency shifting, stabilizing, primary filtering, secondary amplifying, secondary filtering and analog-to-digital conversion processing;
the radio frequency receiving stabilizing circuit (304) is connected to the baseband processing unit (40) and configured to perform receiving stabilizing processing on the baseband processing signal after the baseband processing unit (40) performs digital baseband processing on the first processing signal and the second processing signal to obtain an I-path radio frequency receiving stabilizing signal and a Q-path radio frequency receiving stabilizing signal, where the receiving stabilizing processing sequentially includes digital-to-analog conversion, clock stabilizing processing, and local oscillator stabilizing processing;
the phase shift circuit (305) is connected to the rf receiving stabilizing circuit (304) and configured to perform phase shift processing on the I-path rf receiving stabilizing signal and the Q-path rf receiving stabilizing signal to obtain a first input signal, a second input signal, a third input signal, and a fourth input signal;
the first phase shift correction circuit (306) is connected to the phase shift circuit (305) and corrects the first input signal, the second input signal, the third input signal and the fourth input signal to obtain a first output signal, a second output signal, a third output signal and a fourth output signal;
the I-path radio frequency receiving circuit (302) is further connected to the first phase shift correction circuit (306), and is further configured to perform the first processing on the first output signal and the second output signal to obtain the first sub-correction signal;
the Q-path radio frequency receiving circuit (303) is further connected to the first phase shift correction circuit (306), and is further configured to perform the second processing on the third output signal and the fourth output signal to obtain the second sub-correction signal.
3. The calibration circuit of claim 1, wherein the phase shift input circuit (101) comprises a transistor M1, a transistor M2, a transistor M3, a transistor M4, a capacitor C1, a capacitor C2, a resistor R3, a resistor R4, the first load phase shift adjustment circuit (103) comprises a transistor M5, a capacitor group C3, a resistor R5, a current source V2, the second load phase shift adjustment circuit (104) comprises a transistor M6, a capacitor group C4, a resistor R6, a current source V3, and the tail current phase shift adjustment circuit (105) comprises a resistor R1, a resistor R2, a current source V1, wherein,
a gate of the transistor M1 is connected to the input terminal of the fifth input signal, a drain of the transistor M1 is connected to one end of the capacitor C1, one end of the resistor R3, and a drain of the transistor M3, a source of the transistor M1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the input terminal of the current source V1 and one end of the resistor R2, an output terminal of the current source V1 is grounded, the other end of the resistor R2 is connected to the source of the transistor M2, a gate of the transistor M2 is connected to the input terminal of the sixth input signal, a drain of the transistor M2 is connected to one end of the capacitor C2, one end of the resistor R4, and a drain of the transistor M4, the other end of the resistor R4 is connected to the other end of the resistor R3, the other end of the capacitor C1, the other end of the capacitor C2, and the other end of, An input terminal of the phase shift common mode feedback circuit (102) is connected, a gate of the transistor M3 is connected to an input terminal of the seventh input signal, a source of the transistor M3 is connected to one terminal of the resistor R5, another terminal of the resistor R5 is connected to one terminal of the capacitor bank C3, an output terminal of the current source V2, and a drain of the transistor M5, a gate of the transistor M5 is connected to a gate of the transistor M6 and an output terminal of the phase shift common mode feedback circuit (102), a gate of the transistor M4 is connected to an input terminal of an eighth input signal, a source of the transistor M4 is connected to one terminal of the resistor R6, another terminal of the resistor R6 is connected to one terminal of the capacitor bank C4, an output terminal of the current source V3, and a drain of the transistor M6, another terminal of the capacitor bank C3, an input terminal of the current source V2, and a source of the transistor M5, The other end of the capacitor bank C4, the input end of the current source V3, and the source of the transistor M6 are all connected to a power supply VDD.
4. The calibration circuit of claim 3, wherein said capacitor bank C3 and said capacitor bank C4 are both variable capacitor arrays, said variable capacitor arrays comprising a plurality of switched capacitor banks, said plurality of switched capacitor banks being connected in parallel, each said switched capacitor bank comprising a switch and a capacitor, said switch being connected in series with said capacitor.
5. The correction circuit of claim 3, wherein the phase-shifted common mode feedback circuit (102) comprises a transistor M7, a transistor M8, a transistor M9, a transistor M10, a resistor R7, a resistor R8, a capacitor C5, a current source V4, wherein,
a gate of the transistor M7 is connected to one end of the capacitor C1, one end of the capacitor C2, one end of the resistor R3, and one end of the resistor R4, a source of the transistor M7 is connected to the input of the current source V4, a source of the transistor M8, the drain of the transistor M7 is connected with the drain of the transistor M9, the gate of the transistor M5, the gate of the transistor M6, the source of the transistor M9 is connected with the source of the transistor M10 and one end of the resistor R8, the gate of the transistor M9 is connected with the gate of the transistor M10, the drain of the transistor M10, the drain of the transistor M8, the gate of the transistor M8 is connected to the other end of the resistor R8, one end of the resistor R7, and one end of the capacitor C5, the output end of the current source V4, the other end of the resistor R7 and the other end of the capacitor C5 are all grounded.
6. The calibration circuit of claim 5, wherein the current source V1, the current source V2, the current source V3 and the current source V4 are all variable current sources.
7. The calibration circuit of claim 5, wherein the resistor R1, the resistor R2, the resistor R5, the resistor R6 and the resistor R7 are all variable resistors.
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