JP4084969B2 - Pattern inspection apparatus and pattern inspection method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pattern inspection apparatus and a pattern inspection method for inspecting appearance of a pattern defect in, for example, a printed board, a semiconductor package, a flat panel display, and the like.
[0002]
[Prior art]
Generally, in this type of pattern inspection apparatus, predetermined detection is performed from a grayscale image (binarized image or multivalued image) generated based on imaging data of a pattern to be inspected (for example, a wiring pattern or a pad) on a printed circuit board or the like. An algorithm is used to detect defects such as disconnection and short circuit on the pattern. Conventionally, a feature extraction algorithm (also referred to as a design rule check (DRC) method) and pattern matching (also referred to as a complete comparison method) are used as detection algorithms at that time.
[0003]
The feature extraction algorithm extracts a defective portion in the inspected pattern as a singular point by performing local window processing in a predetermined processing area on the gray image of the inspected pattern. Further, the measurement results such as the wiring width and interval of the pattern are compared with the reference object, and if the measurement result is different from the reference object, the difference is determined to be a defect. On the other hand, the pattern matching directly compares the shapes of the reference non-defective pattern and the pattern to be inspected.
[0004]
[Problems to be solved by the invention]
However, in recent years, wiring patterns and the like on printed circuit boards tend to be complex and have a high density, and in particular, many are formed such that the widths of wiring patterns and intervals between wiring patterns vary depending on the location. . When a printed circuit board having such a wiring pattern is inspected, there is the following problem in the case of pattern inspection using a feature extraction algorithm.
[0005]
That is, when a line width inspection is performed on a pattern whose line width changes in this way, a method based on a uniform pattern width recognizes a portion that is not originally a defect as a defect, and cannot perform an appropriate inspection. It was. In other words, when a thin wiring pattern and a thick wiring pattern are mixed on the printed circuit board to be inspected, the tolerance in each pattern cannot be set independently, and the optimum according to the thickness of the wiring pattern Pattern inspection was difficult. For general line width in pattern inspection, for example, 2/3 or more and 4/3 or less of the reference line width are allowed. However, it is difficult to compare by the ratio that the tolerance changes depending on the line width in the pattern inspection using only the minimum line width using feature extraction, and in the pattern inspection using pattern matching, due to the nature of the algorithm, the wiring shape The line width itself could not be inspected.
[0006]
The present invention has been made in view of such circumstances, and the object thereof is to prevent erroneous detection even if the pattern has a high density and a complicated shape with different line widths and pattern intervals depending on locations. Another object of the present invention is to provide a pattern inspection apparatus and a pattern inspection method that enable relatively easy defect inspection.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 is characterized in that the pattern to be inspected is based on a grayscale image of imaging data obtained by imaging an inspection object provided with a pattern to be inspected within a predetermined imaging range. In the pattern inspection apparatus for detecting defects, a plurality of feature extraction filters having different numbers of recognized pixels for a single pattern to be inspected in the grayscale image are changed by changing the rotation angle at the same measurement position. A width measuring unit that measures and sets the narrowest pattern dimension of all the pattern dimensions as the pattern dimension at the measurement position , and a reference position corresponding to the pattern dimension of the measurement position in the gray image of the non-defective pattern as a comparison reference a reference data storage means for storing reference data relating to pattern dimension in the, with respect to the pattern to be inspected Comparison means for comparing the measurement data obtained from the measurement result of the width measurement means with the reference data stored in the reference data storage means, and the presence or absence of defects in the inspected pattern based on the comparison result of the comparison means The gist of the invention is that it comprises defect judging means for judging the above.
[0008]
According to a second aspect of the present invention, in the pattern inspection apparatus according to the first aspect, the reference data storage means automatically generates the reference data based on a measurement result when the non-defective product pattern is an inspection pattern. The gist of the present invention is to provide a reference data generating means.
[0009]
According to a third aspect of the present invention, in the pattern inspection apparatus according to the first or second aspect, the reference data storage means has a predetermined direction dimension at one position in a predetermined region in the grayscale image of the good product pattern. A plurality of reference data having the same data value as that of the reference data is stored as each reference data at a plurality of other positions located in the vicinity of the one position in the predetermined area. It is a summary.
[0010]
According to a fourth aspect of the present invention, in the pattern inspection apparatus according to any one of the first to third aspects of the present invention, the defect determination unit is configured such that the comparison result of the comparison unit is defective with respect to the pattern to be inspected. The gist is to determine that there is a defect when a predetermined allowable condition range that has been set in advance to determine that there is no defect is present.
[0011]
On the other hand, the invention of claim 5 according to the pattern inspection method, with the one of the inspection pattern in gray image of the imaging data obtained by photographing the inspection object which the test pattern is provided at a predetermined imaging range For each of a plurality of feature extraction filters having different numbers of pixels to be recognized, a plurality of pattern dimensions are measured by changing the rotation angle at the same measurement position, and the narrowest pattern dimension among all the pattern dimensions is the measurement position. after the pattern dimension in a comparison between the measured data relating to the pattern size, and a reference data according to the pattern size of the reference position corresponding to the measurement position in the gray image of the non-defective pattern serving as comparison reference, then, The gist is to determine the presence or absence of defects in the pattern to be inspected based on the comparison result.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment in which the present invention is embodied in a printed circuit board pattern inspection apparatus will be described with reference to FIGS.
[0013]
As shown in FIG. 1, the pattern inspection apparatus 1 according to this embodiment includes a CCD 2, a preprocessing circuit 3, a width measurement circuit 4, a switching circuit 5, an expansion processing circuit 6, a reference image memory 7, a comparison circuit 8, and an allowable error memory. 9. A determination circuit 10 is provided.
[0014]
In the CCD 2, a wiring pattern as a pattern to be inspected formed on a printed circuit board that is an inspection object is photographed in an imaging range of a predetermined shape (rectangular shape in the present embodiment). Imaging data obtained by imaging is sent to the preprocessing circuit 3. The preprocessing circuit 3 includes an A / D converter and a binarization circuit (not shown). In the A / D converter, the imaging data output from the CCD 2 is converted into a digital signal. The digitized image data is binarized by a binarization circuit with a predetermined threshold, and a binary value that is a kind of grayscale image in which the set value (pixel value) of each pixel is 0 and 1 is used. Image data is generated.
[0015]
In the width measuring circuit 4 as the width measuring unit and the reference data generating unit, the wiring width as the pattern dimension is measured using the feature extraction filter in the entire area of the binarized image data. In the switching circuit 5, the circuit for transmitting the wiring width measurement data is switched between when the reference wiring width is generated and when the wiring width inspection is executed. That is, the wiring width measurement data is transmitted to the expansion processing circuit 6 as the reference data generating means when the reference wiring width is generated, and is transmitted to the comparison circuit 8 as the comparing means when executing the wiring width inspection. In the expansion processing circuit 6, the wiring width measurement data output from the width measurement circuit 4 is expanded to a predetermined area at the time of generating the reference wiring width.
[0016]
In the reference image memory 7 as reference data storage means, the expanded wiring width measurement data is stored as reference data. The comparison circuit 8 compares the reference data with the wiring width at the position corresponding to the reference data in the wiring pattern of the binarized image data when the wiring width inspection is executed. When the comparison is made, allowable error information set in advance in the allowable error memory 9 is referred to. In the determination circuit 10 as defect determination means, the presence or absence of a defect is determined based on the result of comparison in the comparison circuit 8.
[0017]
Next, a method for performing pattern inspection using the pattern inspection apparatus according to the present embodiment configured as described above will be described. The pattern inspection includes a process of automatically generating reference data and a process of performing a line width inspection of the wiring pattern. First, the process of automatically generating reference data will be described.
[0018]
Imaging data regarding the non-defective pattern wiring pattern on the printed circuit board, which is imaged by the CCD 2, is sent to the preprocessing circuit 3, and is converted into multi-value 8 bits (256 gradations) by the A / D converter (not shown). Digitally converted. Then, binarized image data separated into a wiring pattern area and other areas is generated by the binarization circuit using a predetermined threshold (128 in the present embodiment) from the digitally converted imaging data. FIG. 2 is a binarized image B which is a part of the binarized image data obtained by imaging the non-defective pattern and is an enlarged region where the wiring patterns 21 to 23 are arranged. In the present embodiment, the pixel values of the wiring pattern areas 21a to 23a in the wiring patterns 21 to 23 are 1, and the pixel values of the other areas 24 are 0. The generated binarized image data is sent to the width measurement circuit 4.
[0019]
In the width measuring circuit 4, the wiring widths of the wiring patterns 21 to 23 are measured using a feature extraction filter. A wiring width measuring method using the feature extraction filter in the width measuring circuit 4 will be described below. FIG. 3 shows the shapes of three types of feature extraction filters (first to third feature extraction filters 31 to 33) in the present embodiment. Each of the feature extraction filters 31 to 33 includes wiring detection units 31a to 33a for detecting the wiring pattern regions 21a to 23a in the binarized image B and non-wiring detection units 31b to 33b for detecting the other regions 24. Each is equipped.
[0020]
The first feature extraction filter 31 is a filter for recognizing a wiring width of 3 to 5 pixels, and includes a first wiring detection unit 31a and a pair of first non-wiring detection units 31b. The first wiring detection unit 31a has a shape in which the unit pixels 30 in the binarized image B are continuously arranged for three pixels in a specific direction (vertical direction in FIG. 3), and the first non-wiring detection unit 31b has the unit pixel 30. Is a shape in which three pixels are continuously arranged in a direction orthogonal to the specific direction (the left-right direction in FIG. 3). In addition, the longitudinal ends of the first wiring detection unit 31a and the central portions of the pair of first non-wiring detection units 31b are formed so as to be positioned on the same straight line, and further, they are recognized. In order to give a width to the wiring width (3 to 5 pixels), it is formed to have an arrangement configuration separated by one pixel.
[0021]
The first feature extraction filter 31 outputs 1 as an output code when the pixel value of the binarized image data at a position corresponding to the first wiring detection unit 31a is 1 (wiring pattern regions 21a to 23a). When the pixel value is 0 (other area 24), 0 is output as the output code. Further, when the pixel value of the binarized image data at the position corresponding to the pair of first non-wiring detectors 31b is 0 (other area 24), 1 is output as the output code, and the pixel value is 1 (wiring) In the case of the pattern areas 21a to 23a), 0 is output as the output code. The output result of the first feature extraction filter 31 is obtained only when all the output codes of the output code of the first wiring detection unit 31a and the output codes of the pair of first non-wiring detection units 31b are 1. 1
[0022]
The second feature extraction filter 32 is a filter for recognizing the wiring width of 5 to 7 pixels, and includes a second wiring detection unit 32a and a pair of second non-wiring detection units 32b. The second wiring detection unit 32a has a shape in which unit pixels 30 in the binarized image B are continuously arranged for five pixels in a specific direction (vertical direction in FIG. 3), and the second non-wiring detection unit 32b has a unit. The pixel 30 has a shape in which three pixels are continuously arranged in a direction orthogonal to the specific direction (left-right direction in FIG. 3). Further, both end portions in the longitudinal direction of the second wiring detection unit 32a and the respective central portions of the pair of second non-wiring detection units 32b are formed on the same straight line, and further, they are recognized. In order to give a width to the wiring width (5 to 7 pixels), it is formed to have an arrangement configuration separated by one pixel.
[0023]
The third feature extraction filter 33 is a filter for recognizing the wiring width of 7 to 9 pixels, and includes a third wiring detection unit 33a and a pair of third non-wiring detection units 33b. The third wiring detection unit 33a has a shape in which the unit pixels 30 in the binarized image B are continuously arranged for seven pixels in a specific direction (vertical direction in FIG. 3), and the third non-wiring detection unit 33b has the unit pixel 30. Is a shape in which three pixels are continuously arranged in a direction orthogonal to the specific direction (the left-right direction in FIG. 3). Further, both end portions in the longitudinal direction of the third wiring detection unit 33a and the respective central portions of the pair of third non-wiring detection units 33b are formed on the same straight line, and further, they are recognized. In order to give a width to the wiring width (7 to 9 pixels), it is formed to have an arrangement configuration separated by one pixel. The conditions of the output results from the second feature extraction filter 32 and the third feature extraction filter 33 are the same as those of the first feature extraction filter 31.
[0024]
Further, the feature extraction filters 31 to 33 are rotated by a predetermined angle (for example, 22.5 degrees, 45 degrees, 67.5 degrees, and 90 degrees with the feature extraction filters 31 to 33 shown in FIG. 3 as a reference (0 degree)). , 112.5 degrees, 135 degrees, and 157.5 degrees), and width measurement using these feature extraction filters is simultaneously performed. Thereby, it becomes possible to measure the line width of the wiring pattern arrange | positioned toward various directions. Therefore, for each pixel of the binarized image B, eight patterns of filters rotated in increments of 22.5 degrees are prepared for each of the three types of feature extraction filters 31 to 33, and a total of 24 types of filtering are performed. become.
[0025]
For example, when only the output result of the second feature extraction filter 32 is 1 at a certain measurement position on the binarized image B, it can be seen that the wiring pattern width at that measurement position is 6. When the output results of the second feature extraction filter 32 and the third feature extraction filter 33 are 1 at a certain measurement position, it can be seen that the wiring pattern width at the measurement position is 7. When the output results of all the feature extraction filters 31 to 33 are 0, that is, when the wiring width cannot be detected, what is detected at the measurement position exceeds the measurement range of these feature extraction filters or is not a wiring pattern. It is judged.
[0026]
Then, for each feature extraction filter 31 to 33, the width of the wiring pattern obtained by the feature extraction filter of each pattern having the same shape and size with different rotation angles at the same measurement position (hereinafter referred to as wiring width). The narrowest wiring width is the wiring width at the measurement position. If the output results of all the feature extraction filters 31 to 33 at all the rotation angles are 0, that is, the wiring width cannot be detected, the detection result at that position is the measurement range of these feature extraction filters. It is judged that the wiring pattern is not exceeded. In this way, the wiring width obtained from the output results of the feature extraction filters 31 to 33 is output as a digitized code 25 along a position corresponding to the center of the wiring patterns 21 to 23 as shown in FIG. Is done. FIG. 5 is an enlarged view of a P portion surrounded and displayed by a dotted line in FIG. Each digitized code 25 representing each wiring width of 3 to 5 is output at a position corresponding to the center in the width direction of the wiring pattern 23.
[0027]
When generating the reference wiring width, the digitized code 25 generated by the width measuring circuit 4 is sent to the expansion processing circuit 6 connected via the switching circuit 5. The expansion processing circuit 6 executes a process of expanding the digitized code 25 to the peripheral position assuming a positional deviation at the time of inspection. The expansion range at this time may be arbitrary, and is expanded within an appropriate range based on the assumed positional deviation amount. FIG. 6 shows the result of the expansion process. FIG. 7 is an enlarged view of the Q portion surrounded by the dotted line in FIG. In the present embodiment, as shown in the figure, the wiring pattern 23 is expanded by three pixels in the left-right width direction. Then, the digitized code 25 generated in this way and the digitized code 26 that is expanded to the surrounding area and has the same data value as the digitized code 25 are used as reference data together with the position information as a reference image. Stored in the memory 7.
[0028]
Next, the process of performing the line width inspection of the wiring pattern will be described. Note that the method of generating the binarized image B is the same as that described above, and is omitted here. FIG. 8 is a diagram of a binarized image B obtained by enlarging a part of the binarized image data generated by imaging and binarizing a printed circuit board that is an inspection target provided with a pattern to be inspected. It is. In the wiring patterns 41a to 43a in the same figure, the pinholes are shown in the portions surrounded by the dotted line 44 in the wiring pattern regions 41a to 43a, the chipped portions are shown in the dotted line 45, and the portions are shown surrounded by the dotted line 46. There are protrusions on the surface.
[0029]
In the width measurement circuit 4, the wiring width in each of the wiring patterns 41 to 43 is measured by the method described above for all the positions of all the wiring pattern regions 41 a to 43 a in the binarized image B. A digitized code (hereinafter also referred to as measurement data) generated by the width measurement circuit 4 at the time of executing the wiring width inspection is sent to the comparison circuit 8 connected via the switching circuit 5. The comparison circuit 8 compares the reference data stored in the reference image memory 7 with the measurement data at the position corresponding to the reference data. When the comparison is made, the allowable error information set in the allowable error memory 9 is referred to. That is, an allowable error condition range is set in advance, and it is determined whether or not the measurement data matches the reference data in consideration of the allowable condition range. This is because, when comparing the reference data and the measurement data, it is not practically preferable to determine that the defect is not always the same wiring width because a false detection occurs frequently.
[0030]
The allowable error condition range is stored in advance in the allowable error memory 9 for each wiring width of the assumed reference data. In the present embodiment, when the wiring width of the reference data is 3 pixels or less, 2 to 4 pixels are allowed, and when the wiring width is 4 to 7 pixels, 3 pixels or more and 1/2 pixel of the reference data The above is the allowable range. When the wiring width of the reference data is 8 pixels or more, the allowable range is 2/3 pixels or more and 4/3 pixels or less of the reference data. As described above, an optimum tolerance can be set by giving an appropriate tolerance for each wiring width. The comparison result obtained in this way is sent to the determination circuit 10.
[0031]
FIG. 9 shows the result of comparison between reference data and measurement data. In the portion surrounded by the dotted line 44 in the wiring pattern 41, there are two wiring widths measured due to the presence of pinholes, and each width is shorter than the reference data. Further, in the portion surrounded by the dotted line 45 in the wiring pattern 42, the wiring width measured due to the presence of a chip is shorter than the reference data. In the portion surrounded by the dotted line 46 in the wiring pattern 43, the wiring width measured by the presence of the protrusion is longer than the reference data.
[0032]
The determination circuit 10 determines whether there is a defect. In the determination circuit 10, when the measurement data is smaller than the allowable error range (dotted lines 44 and 45 in FIG. 9), it is determined that there is a chip or a pinhole at that position, and the determination data is smaller than the allowable error range. If it is larger (the portion indicated by the dotted line 46 in FIG. 9), it is determined that there is a protrusion at that position. On the other hand, if it is within the allowable error range, it is determined that there is no defect at that position. The determination result obtained in this way is output to an external output device such as a television monitor. At this time, as shown in FIG. 10, a defect and a defect position can be easily recognized by additionally displaying a mark having a predetermined shape in the vicinity of the defect position (× mark in FIG. 10).
[0033]
Therefore, in the present embodiment, the following effects can be obtained by configuring the pattern inspection apparatus as described above.
(1) In the present embodiment, a system is adopted in which the line width is measured for each position of the wiring patterns 41 to 43 of the pattern to be inspected and the wiring patterns 21 to 23 of the non-defective pattern and sequentially compared. Therefore, even for a printed circuit board on which a wiring pattern having a high density and a complicated shape is formed, it is possible to detect defects based on a line width inspection which is relatively easy and sure and is unlikely to cause erroneous detection.
[0034]
(2) In the present embodiment, the width measurement circuit 4 measures the line width of the non-defective pattern, and stores the measured data as reference data in the reference image memory 7 via the switching circuit 5 and the expansion processing circuit 6. be able to. That is, the reference data can be automatically created.
[0035]
(3) In this embodiment, the expansion processing circuit 6 expands the reference data of the non-defective pattern to the peripheral area, so that there is a slight deviation when comparing the reference data and the measurement data related to the pattern to be inspected. Even if it occurs, accurate line width inspection can be performed.
[0036]
(4) In the present embodiment, an excessive error detection in the determination circuit 10 can be suppressed by providing an allowable error range with a predetermined width or a predetermined ratio for the measurement data.
[0037]
In addition, you may change the said embodiment as follows.
In the above embodiment, the binarized image B has been described as an example. However, the present invention is not limited to this, and pattern inspection may also be performed for a multi-value image (for example, an 8-bit 256 gradation image) that is a grayscale image. In this case, the preprocessing circuit 3 is configured without including a binarization circuit. That is, the preprocessing circuit 3 includes an A / D converter (not shown), and the imaging data output from the CCD 2 is converted into a digital signal by the A / D converter to generate multi-value image data.
[0038]
In the above embodiment, the wiring patterns 21 to 23 are described as examples of the pattern to be inspected. However, the present invention is not limited to this, and a pad having a predetermined shape that is an end point of the wiring pattern and the interval between the wiring patterns are added to the pattern to be inspected. Also good.
[0039]
In the above embodiment, the line width measurement is performed at all positions (measurement positions) of the wiring pattern areas 21a to 23a (41a to 43a) in the binarized image B. However, the predetermined range in the pattern formation direction or the like is limited. The line width may be measured.
[0040]
In the above embodiment, three types of feature extraction filters 31 to 33 are used. However, the present invention is not limited to this, and a necessary number of filters that can detect the minimum width and maximum width of the wiring pattern are used. Is desirable. Further, the feature extraction filters 31 to 33 are not limited to the shapes described in the present embodiment and the drawings, and may adopt a predetermined shape suitable for measuring the line width.
[0041]
In the above embodiment, the reference data related to the non-defective pattern is automatically generated by the expansion processing circuit 6, but it may be input from an input device such as a keyboard (not shown) each time. Further, it may be set in advance.
[0042]
In the above-described embodiment, when generating the reference data related to the non-defective pattern, the printed circuit board of the non-defective pattern serving as the comparison reference is imaged by the CCD 2, but the reference data may be generated using CAD data.
[0043]
In the above embodiment, the allowable error is stored in advance in the allowable error memory 9, but the allowable error may be calculated by calculation. For example, a method that uses a deviation within a certain pixel (for example, two pixels) from the reference data as an allowable error (example by addition), or a ratio between measurement data and reference data is obtained, and within a certain ratio (for example, 80% to 120%) There is a method (an example based on a ratio) in which the deviation is an allowable error. Further, it may be defined as a deviation within a certain pixel and within a certain ratio (for example, a deviation within 2 pixels and 80% to 120% of the reference data).
[0044]
In the above embodiment, the expansion processing circuit 6 executes the process of expanding the digitized code 25 to the peripheral position, but this process may be omitted. That is, the digitized code 25 generated by the width measuring circuit 4 may be transmitted directly to the reference image memory 7.
[0045]
In the above embodiment, the presence or absence of a defect is determined based on the allowable error information set in the allowable error memory 9, but the defect may be determined without setting the allowable error.
[0046]
【The invention's effect】
As described above in detail, according to the present invention, even if the wiring pattern has a complicated shape with a high density and a different line width or pattern interval depending on the location, it is difficult for false detection to occur, and defect detection is relatively easy. It can be carried out.
[Brief description of the drawings]
FIG. 1 is a system configuration diagram of a pattern inspection apparatus according to an embodiment.
FIG. 2 is an explanatory diagram of a binarized image of reference data.
FIG. 3 is an explanatory diagram of a feature extraction filter.
FIG. 4 is an explanatory diagram at the time of wiring width measurement.
FIG. 5 is an explanatory diagram at the time of wiring width measurement.
FIG. 6 is an explanatory diagram of expansion processing.
FIG. 7 is an explanatory diagram of expansion processing.
FIG. 8 is an explanatory diagram of a binarized image of a pattern to be inspected.
FIG. 9 is an explanatory diagram at the time of defect inspection.
FIG. 10 is an explanatory diagram of a defect position display example.
[Explanation of symbols]
4 Width measurement circuit as width measurement means and reference data generation means 6 Expansion processing circuit 7 as reference data generation means 7 Reference image memory as reference data storage means 8 Comparison circuit as comparison means 9 Determination circuit as defect determination means

Claims (5)

In a pattern inspection apparatus for detecting a defect in the inspection pattern based on a grayscale image of imaging data obtained by imaging an inspection object provided with an inspection pattern in a predetermined imaging range,
For one feature pattern in the grayscale image, for each of a plurality of feature extraction filters having different numbers of pixels to be recognized, a plurality of pattern dimensions are measured by changing the rotation angle at the same measurement position. Among them, the width measuring means whose narrowest pattern dimension is the pattern dimension at the measurement position ,
A reference data storage means for storing reference data relating pattern dimension of the measurement position in the gray image of the non-defective pattern as a comparison reference and the pattern dimension in the corresponding reference position,
Comparison means for comparing the measurement data obtained from the measurement result of the width measurement means with respect to the inspection pattern and the reference data stored in the reference data storage means;
A pattern inspection apparatus comprising: defect determination means for determining the presence or absence of defects in the pattern to be inspected based on a comparison result of the comparison means. 2. The pattern according to claim 1, wherein the reference data storage means includes reference data generation means for automatically generating the reference data based on a measurement result when the non-defective product pattern is an inspection pattern. Inspection device. The reference data storage means includes a plurality of reference data having the same data value as the reference data, together with reference data relating to a predetermined direction dimension at one position in a predetermined region in the gray image of the good product pattern. The pattern inspection apparatus according to claim 1, wherein each pattern data is stored as reference data at a plurality of other positions located in the vicinity of the one position in the region. The defect determination means determines that there is a defect when a comparison result of the comparison means is outside a predetermined allowable condition range set in advance for determining that the pattern to be inspected has no defect. The pattern inspection apparatus as described in any one of Claims 1-3. About one pattern to be inspected in the gray image of the imaging data obtained by photographing the inspection object which the test pattern is provided at a predetermined imaging range, the number for each different feature extraction filter to each other pixels recognized, A plurality of pattern dimensions are measured by changing the rotation angle at the same measurement position, and the narrowest pattern dimension among all the pattern dimensions is the pattern dimension at the measurement position .
It compares the measured data relating to the pattern size, and a reference data according to the pattern size of the reference position corresponding to the measurement position in the gray image of the non-defective pattern serving as comparison reference,
Then, the pattern inspection method which determines the presence or absence of the defect in the said to-be-inspected pattern based on the compared result.

Images