JP4080624B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, a semiconductor device including a capacitor in which a lower capacitor electrode and a capacitor insulating film have a perovskite structure, and the lower capacitor electrode is connected to a semiconductor substrate through a plug electrode, and the same It relates to a manufacturing method.
[0002]
[Prior art]
In recent years, along with the high integration of semiconductor integrated circuits, the miniaturization of elements continues to progress, and for example, the cell area of capacitors has become very small. When the cell area is reduced, the capacitance of the capacitor is also reduced. However, there is a demand that the capacitance of the capacitor cannot be reduced so much in terms of sensitivity and soft error.
[0003]
As a method for securing the capacitance, a method of forming a capacitor three-dimensionally to increase the cell area as much as possible and a method of using an insulating film having a high dielectric constant for the capacitor insulating film are being studied.
[0004]
A typical example of an insulating film having a high dielectric constant is (Ba, Sr) TiO._Three Oxide dielectric films such as films are known. When this kind of oxide dielectric film is used as a capacitor insulating film, it is not oxidized or oxidized in order to prevent a low dielectric constant layer from being formed at the interface between the capacitor electrode and the capacitor insulating film. It is necessary to form the capacitor electrode with a material exhibiting metal conductivity.
[0005]
Recently, as such an electrode material, (Ba, Sr) TiO is used._Three Has the same crystal structure (perovskite structure) as SrRuO_Three The use of is being considered. FIG. 10 shows SrRuO as a capacitor electrode material._ThreeFIG. 6 shows a cross-sectional process diagram of a DRAM memory cell using
[0006]
To explain this, first, as shown in FIG. 8A, an element isolation region 72 is formed on the surface of a p-type Si substrate 71 by STI (Shallow Trench Isolation).
[0007]
Next, as shown in FIG. 5A, a gate insulating film 73, a gate electrode (word line) 74, n⁺ Type drain diffusion layer 75, n⁺After forming the type source diffusion layer 76 and subsequently depositing a first interlayer insulating film 77 to planarize the surface, the first interlayer insulating film (SiO 2)₂A bit hole 78 is formed by opening a contact hole in the film 77.
[0008]
Next, as shown in FIG. 5A, the second interlayer insulating film (SiO₂(Film) 79 is deposited to flatten the surface, and then a contact hole is formed in the first and second interlayer insulating films 77 and 79, and the inside thereof is plug electrode 82 via Ti film 80 and TiN film 81. Embed with
[0009]
Next, as shown in FIG. 8B, the SiN film 83, the third interlayer insulating film (SiO₂(Film) 84 is deposited and the surface is flattened, and then a via hole for the plug electrode 82 is formed in these insulating films 83 and 84.
[0010]
Next, as shown in FIG. 8C, SrRuO which becomes the lower capacitor electrode 85 so as to fill the inside of the via hole._Three After depositing the film on the entire surface by sputtering or CVD, excess SrRuO outside the via hole_Three The film is removed by a CMP (Chemical Mechanical Polishing) method to form the lower capacitor electrode 85. Thereafter, the third interlayer insulating film 84 is selectively removed by etching.
[0011]
Finally, as shown in FIG. 8D, (Ba, Sr) TiO._Three A capacitor insulating film 86 made of is deposited on the entire surface by the CVD method, and then SrRuO which becomes the upper capacitor electrode 87_Three After the film is deposited on the entire surface by the CVD method, this SrRuO_ThreeThe film is processed to form the upper capacitor electrode 87, thereby completing the DRAM memory cell.
[0012]
Here, in order to increase the capacitor capacity and suppress the leakage current, it is desirable that the lower capacitor electrode 85, the capacitor insulating film 86, and the upper capacitor electrode 87 are epitaxially grown.
[0013]
For this purpose, SrRuO which is the lower capacitor electrode 85 is used._Three The film needs to be single crystallized. Reported SrRuO_Three The method for single crystallization of the film will be described as follows.
[0014]
First, as shown in FIG. 9A, an AlTiN film 92 is deposited on a single crystal Si substrate 91 by a sputtering method. Here, the AlTiN film 92 is epitaxially grown on the single crystal Si substrate 91 and becomes a single crystal over the entire surface.
[0015]
Next, as shown in FIG. 9B, a Pt film 93 is deposited on the AlTiN film 92 by sputtering. Similarly, this Pt film 93 also becomes a single crystal over the entire surface.
[0016]
Finally, as shown in FIG. 9C, the SrRuO film is formed on the Pt film 93._Three A film 94 is deposited by sputtering. This SrRuO_Three Similarly, the film 94 becomes a single crystal over the entire surface.
[0017]
In this way, the single crystal SrRuO that is the lower capacitor electrode 85 is formed._Three If the film is formed, the capacitor insulating film 86 (Ba, Sr) TiO is used._Three The film can also be single-crystallized in the capacitor part, and SrRuO which is the upper capacitor electrode 87_Three Since the film also has the same perovskite structure, it can be single-crystallized in the capacitor portion, and a capacitor having good characteristics can be realized.
[0018]
However, in an actual DRAM, a gate electrode (word line) 74 and a bit line 78 for operating a transistor are wired between the Si substrate 71 and the lower capacitor electrode 85, and the lower capacitor electrode 85 is n⁺It must be connected to the type source diffusion layer 76 via a submicron-sized plug electrode 82, and the aspect ratio of the contact hole for embedding the plug electrode 82 increases as the generation of LSI advances.
[0019]
Thus, when the size of the plug electrode 82 is reduced and the aspect ratio is increased, the Si-based material conventionally used as the plug electrode material cannot be used because of its high resistance. Instead, Ru, W, etc. Although it is necessary to use a low-resistance metal, it is very difficult to make a single crystal of this kind of metal.
[0020]
Further, as shown in FIG. 10, a plug electrode 82 whose upper surface is lower than the opening surface of the contact hole is formed, and single crystal SrRuO is formed only on the surface of the plug electrode 82._Three When the / Pt laminated film 88 is formed, SrRuO as the upper capacitor electrode 87 formed thereon is formed._Three It is possible to monocrystallize the film.
[0021]
Single crystal SrRuO_Three / Pt laminated film 88 is formed by applying amorphous SrRuO to the unfocused portion of the contact hole on plug electrode 82._Three / Pt multilayer film is embedded and formed, and this is formed into a single crystal using laser annealing or the like.
[0022]
However, when the size of the plug electrode 82 is about submicron, amorphous SrRuO on the plug electrode 82 is used even if laser annealing or the like is used._Three It is difficult to make a single crystal of the / Pt laminated film, and twins and polycrystals are formed. As a result, SrRuO which is the lower capacitor electrode 85 is formed._Three There is a problem that the film also becomes twinned or polycrystalline. In the figure, 89 indicates a grain boundary.
[0023]
[Problems to be solved by the invention]
As described above, a single crystal (Ba) having a high dielectric constant is used as a capacitor insulating film in order to secure a necessary capacity in a DRAM cell which has been miniaturized._,Sr₎TiO_ThreeSingle crystal SrRuO as film, lower and upper capacitor electrodes_ThreeIt has been proposed to use a membrane.
[0024]
In order to form such a capacitor insulating film and the lower and upper capacitor electrodes, the plug electrode connecting the lower capacitor electrode and the Si substrate had to be a single crystal.
[0025]
However, in a highly miniaturized DRAM cell, it is necessary to use a metal such as Ru, which has a low resistance but is difficult to crystallize, as a material for the plug electrode. There was a problem.
[0026]
As another method, amorphous SrRuO is formed in the unfilled portion of the contact hole in which the plug electrode is partially embedded._ThreeThere has also been proposed a method in which a film is embedded and formed into a single crystal by laser annealing and used as a crystal nucleus.
[0027]
However, in the advanced DRAM cell, the contact hole is also miniaturized, and amorphous SrRuO embedded in the upper part of such a fine contact hole._ThreeThere is a problem that it is difficult to single crystallize the film by laser annealing.
[0028]
The present invention has been made in view of the above circumstances, and an object of the present invention is to connect a perovskite structure on a lower capacitor electrode made of a conductive film having a perovskite structure and connected to a semiconductor substrate through a plug electrode. It is an object of the present invention to provide a semiconductor device having a structure capable of easily realizing a capacitor formed with a capacitor insulating film made of a metal oxide dielectric film having a structure and a method for manufacturing the same.
[0029]
[Means for Solving the Problems]
[Constitution]
  In order to achieve the above object, a semiconductor device according to the present invention is formed on a semiconductor substrate and has a perovskite structure.Single crystal SrRuO _Three filmA lower capacitor electrode, and a perovskite structure formed on the lower capacitor electrodeSingle crystalA capacitor insulating film made of a metal oxide dielectric film, an upper capacitor electrode formed on the capacitor insulating film, the lower capacitor electrode and the semiconductor substrate are connected, and a depression is formed in a portion in contact with the lower capacitor electrode The inside of this dent isSrRuO _Three filmPlug electrode embedded inAnd said SrRuO _Three The plug electrode, wherein at least the outermost surface of the film is a single crystalAnd withThe lower capacitor electrode is formed of the SrRuO embedded in the recess. _Three Using the film as a crystal nucleus, the SrRuO _Three Amorphous SrRuO in contact with the film _Three The film is crystallized by heat treatment, and the size of the recess is amorphous SrRuO embedded in the recess. _Three The size is such that at least the outermost surface of the film can be converted into a single crystal by heat treatmentIt is characterized by that.
[0031]
  In addition, a method for manufacturing a semiconductor device according to the present invention includes a step of forming a plug electrode having a depression on a surface for connecting the semiconductor substrate and a lower capacitor electrode to be formed in a later step on the semiconductor substrate, and the depression. InsideSrRuO whose at least outermost surface is a single crystal _Three filmThe process of embedding with, and amorphous with perovskite structure during crystallizationSrRuO _Three filmThe aboveSrRuO whose at least outermost surface is a single crystal _Three filmForming to contact with the said,SrRuO whose at least outermost surface is a single crystal _Three filmFor the crystal nucleusSrRuO _Three filmHas a perovskite structure as a lower capacitor electrode by crystallizing by heat treatmentSingle crystal SrRuO _Three filmAnd the process of forming thisSingle crystal SrRuO _Three filmHas a perovskite structure on topSingle crystalThe method includes a step of forming a capacitor insulating film made of a metal oxide dielectric film, and a step of forming an upper capacitor electrode on the capacitor insulating film.
[0032]
More specific embodiments of the present invention are as follows.
[0033]
(1)SrRuO whose at least outermost surface is a single crystal _Three filmIs a conductive material having a perovskite structure.
[0034]
(2) The upper capacitor electrode is composed of a conductive film having a perovskite structure.
[0035]
(3) The hole diameter of the recess is 50 nm or less.
[0038]
(4) Lower capacitor electrode is ARuO_Three (A represents at least one element selected from Sr, Ba, Ca, La and Nd), and (Sr, RE) CoO_Three (RE represents at least one element selected from La, Pr, Sm, and Nd), and is made of one material selected from the group consisting of:
[0039]
(5) Capacitor insulation film is (Ba, Sr) TiO_Three , SrTiO_Three , BaTiO_Three , PbTiO_Three , Bi_Four Ti_Three O₁₂, SrBi₂ Ta₂ O₉ , Pb (Zr, Ti) O_Three Or (Pb, La) (Zr, Ti) O_Three It consists of
[0040]
(6) Inside the depressionSrRuO whose at least outermost surface is a single crystal _Three filmThe step of embedding in the amorphous is thicker than half of the hole diameter of the depression so as to fill the inside of the depression.SrRuO _Three filmOn the entire surface and amorphous outside the depressionSrRuO _Three filmAnd the amorphous material remaining inside the depressionSrRuO _Three filmCrystallizing.
[0041]
(9) Platinum film or ABO as amorphous conductive film_Three(A and B are metal elements) A film is formed, and a sputtering method or a CVD method is used as the film formation method.
[0042]
    [Action]
  The present invention (Claims 1 to5) According to the inside of the depression on the surface of the plug electrodeSrRuO whose at least outermost surface is a single crystal _Three filmEven if the plug electrode is a metal film that is difficult to be single-crystallized, such as a Ru film,SrRuO _Three filmHas a perovskite structure by usingSingle crystal SrRuO _Three filmThe (lower capacitor electrode) can be easily formed.
[0043]
  Further, even if the contact hole in which the plug electrode is embedded has a small opening diameter, the present invention (claims)6)SrRuO whose at least outermost surface is a single crystal _Three filmCan be easily formed. The reason is that if the size of the recess on the surface of the plug electrode is 50 nm or less, the amorphous material embedded in the plug electrodeSrRuO _Three filmThis is because a single crystal is surely formed by heat treatment.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0045]
(First embodiment)
FIG. 1 is a cross-sectional view showing a DRAM cell according to a first embodiment of the present invention.
[0046]
In the figure, reference numeral 1 denotes a p-type Si substrate, and an element isolation region 2 having an STI structure is formed on the surface of the p-type Si substrate 1.
[0047]
In the transistor region isolated by the element isolation region 2, a gate insulating film 3, a gate electrode (word line) 4, n⁺Type drain diffusion layer 5 and n⁺A MOS transistor composed of the type source diffusion layer 6 is formed.
[0048]
On the p-type Si substrate 1, a first interlayer insulating film (SiO 2 having a flat surface is formed.₂ Film) 7 is formed, and the bit line 8 is n through the contact hole opened in the first interlayer insulating film 7.⁺It is connected to the type drain diffusion layer 5.
[0049]
On the first interlayer insulating film 7, a second interlayer insulating film (SiO 2 having a flat surface is formed.₂ Film) 9 is formed, and the plug electrode 10 made of single crystal Ru is n through the contact hole opened in the first and second interlayer insulating films 7 and 9.⁺It is connected to the type source diffusion layer 6.
[0050]
A recess is formed at the center of the surface of the plug electrode 10, and the interior of the recess is a single crystal SrRuO._Three It is embedded with a film 11. SrRuO_Three Instead of the film 11, a crystalline substance having a lattice constant close to that may be used.
[0051]
A SiN film 12 is formed on the second interlayer insulating film 9. The SiN film 12 has an opening in a region including the plug electrode 10 and is in contact with the plug electrode 10 through the opening._ThreeA lower capacitor electrode 14 is formed. The lower capacitor electrode 14 is thicker than the SiN film 12.
[0052]
On the lower capacitor electrode 14, a single crystal (Ba, Sr) TiO 2 is formed._Three A capacitor insulating film 15 made of is formed. A single-crystal SrRuO film is formed on the lower capacitor electrode 14 via a capacitor insulating film 15._ThreeAn upper capacitor electrode 16 is formed.
[0053]
Note that the capacitor insulating film 15 on the SiN film 12 other than the vicinity of the lower capacitor electrode 14 is not single crystal but amorphous or polycrystalline. When the temperature (single crystallization temperature) at the time of forming the capacitor insulating film 15 is low, it is amorphous, and even when the single crystallization temperature is low, the subsequent process (for example, at the time of forming the upper capacitor electrode 16) or crystallinity improvement When exposed to a temperature higher than the single crystallization temperature, it becomes polycrystalline. The amorphous or polycrystalline portion has no problem because it does not serve as a capacitor insulating film.
[0054]
According to such a configuration, (Ba, Sr) TiO having a high dielectric constant is used as the capacitor insulating film 15._ThreeSince the film is used and all of the parts constituting the capacitor are single crystal films (perovskite structure), the required capacitor capacity can be easily secured and the increase in leakage current can be effectively suppressed. become.
[0055]
2 and 3 are process sectional views showing a method of manufacturing the DRAM memory cell of FIG.
[0056]
First, as shown in FIG. 2A, an element isolation region 2 by STI is formed on the surface of a p-type Si substrate 1, followed by a gate insulating film 3, a gate electrode (word line) 4, n⁺ Type drain diffusion layer 5, n⁺A type source diffusion layer 6 is formed.
[0057]
Next, as shown in FIG. 5A, after depositing a first interlayer insulating film 7 and planarizing the surface, a contact hole is formed in the first interlayer insulating film 7 to form a bit line 8; Subsequently, after the second interlayer insulating film 9 is deposited and the surface is flattened, contact holes are opened in the first and second interlayer insulating films 7 and 9.
[0058]
Next, as shown in FIG. 2B, the substrate temperature is 200 to 450 ° C., the film forming pressure is 1 to 100 Pa, and Ru (Cp).₂ (Ar carrier) and O₂ (Atmosphere O₂ After depositing a Ru film to be the plug electrode 10 on the entire surface by a CVD method using a concentration of 40% or less), the excess Ru film outside the contact hole is removed by a CMP method or an etch-back method using reactive ion etching By doing so, the plug electrode 10 is embedded in the contact hole.
[0059]
At this time, when the excess Ru film is removed by the CMP method, a recess is formed in the central portion of the plug electrode 10 by reducing the film thickness of the Ru film deposited on the entire surface to about half of the diameter of the contact hole. To do. In the case of reactive ion etching, the film thickness of the Ru film (plug electrode 10) is not particularly limited, and it is sufficient if it is not too thick (up to the aperture diameter). FIG. 11 shows a cross-sectional view of a process of removing an excess Ru film by a CMP method or a reactive ion etching (RIE) method.
[0060]
Next, as shown in FIG. 2C, the substrate temperature is 200 to 400 ° C., the film forming pressure is 1 to 1000 Pa, and Ru (THD)_Three And Sr (THD)₂ And O₂Single crystal SrRuO by CVD using a mixed gas of_Three Amorphous SrRuO to be the film 11_Three A film is deposited on the entire surface, and then the excess SrRuO outside the depression is formed by CMP._Three After removing the film, heat treatment at 600 ° C. or higher is performed, so that the depression at the center of the plug electrode 10 is made of single crystal SrRuO._Three The film 11 is embedded.
[0061]
Next, as shown in FIG. 3D, the SiN film 12, the third interlayer insulating film (SiO₂ Film) 13 is sequentially deposited, and then a contact hole connected to plug electrode 10 is opened in these insulating films 12 and 13, and then amorphous SrRuO serving as a lower capacitor electrode is filled to fill the contact hole._Three A film 14 is deposited on the entire surface by CVD. SrRuO on the third interlayer insulating film 13_Three The film 14 need not be thicker than the SiN film 12.
[0062]
The SiN film 12 is for preventing the capacitor insulating film 15 from coming into direct contact with the plug electrode 10 even if the contact hole formation position is shifted. This prevents an increase in leakage current due to misalignment.
[0063]
Next, as shown in FIG. 3E, excess SrRuO outside the contact hole._ThreeThe film 14 is removed by the CMP method, and SrRuO is formed only inside the contact hole._ThreeThe membrane 14 is selectively left behind.
[0064]
Thereafter, SrRuO inside the contact hole is obtained by heat treatment at 400 to 500 ° C. for 2 to 10 hours._Three By crystallizing the film 14, single crystal SrRuO_Three The lower capacitor electrode 14 made of is completed.
[0065]
Next, as shown in FIG. 3 (f), the third interlayer insulating film 13 is removed by etching, and then amorphous (Ba, Sr) TiO 3 which becomes the single crystal capacitor insulating film 15._ThreeAfter the film is deposited on the entire surface by the CVD method, this is heat-treated and crystallized to form a single crystal (Ba, Sr) TiO 2 in a portion in contact with the lower capacitor electrode 14._ThreeA capacitor insulating film 15 made of is formed.
[0066]
Next, as shown in FIG. 5 (f), amorphous SrRuO serving as the upper capacitor electrode is formed._Three After the film 16 is deposited on the entire surface by the CVD method, this is heat-treated and crystallized to obtain a single crystal SrRuO._ThreeA film 16 is formed.
[0067]
Finally, single crystal SrRuO_ThreeThe film 12 is patterned into an electrode shape to complete the DRAM memory cell shown in FIG.
[0068]
In the present embodiment, when the lower capacitor electrode 14 is formed, excess amorphous SrRuO._Three After removing the film by the CMP method, amorphous SrRuO is formed by heat treatment._ThreeThe film was crystallized, but conversely, amorphous SrRuO was obtained by heat treatment._ThreeAfter crystallizing the film, excess single crystal SrRuO_ThreeThe film may be removed by a CMP method.
[0069]
Hereinafter, advantages of using the Ru film as the plug electrode 10 will be described.
[0070]
To embed and form a Ru film in a contact hole, first, Ru (C₆H_Five)₂, Ru (CH_ThreeC_FiveH_Four)₂Or Ru (C₂H_FiveC_FiveH_Four)₂And O₂Then, the Ru film outside the contact hole is removed by the CMP method after being deposited on the entire surface by the CVD method at a film forming temperature of 300 ° C. or lower. O₂Instead of O_Three, O radical, N₂A substance that becomes an oxidizing atmosphere such as O may be used.
[0071]
If the Ru film is formed under the above conditions, the Ru film can be formed with very good coverage, and the surface morphology of the Ru film is also good. Therefore, by using the Ru film embedding method, it becomes possible to easily realize the plug electrode 10 made of Ru without forming a void in a contact hole having a small opening diameter.
[0072]
Since Ru exhibits metal conductivity even when oxidized like Ir or the like, the material of the lower capacitor electrode 14 is SrRuO._ThreeEven when a metal oxide such as this is used, the problem that the contact resistance between the plug electrode 10 and the lower capacitor electrode 14 increases does not occur.
[0073]
The contact surface between the Si substrate 1 and the plug electrode 10 is O in the film forming atmosphere.₂Therefore, a very thin layer containing Ru, Si, and O is formed. This layer has the advantage of preventing the diffusion of Ru into the Si substrate 1 and lowering the contact resistance between the Si substrate 1 and the plug electrode 10. Moreover, there is no problem even if a barrier metal film such as a TiN film is formed on the contact surface between the Si substrate 1 and the plug electrode 10.
[0074]
Further, as in the present embodiment, the material of the lower capacitor electrode 14 is SrRuO._ThreeWhen Ru is used, the Ru element is included in both the plug electrode 10 and the lower capacitor electrode 14, so that the electrical connection between the plug electrode 10 and the lower capacitor electrode 14 is very good.
[0075]
In the present embodiment, the depression on the surface of the plug electrode 10 is made of single crystal SrRuO._Three Although embedded in the film 14, as shown in FIG. 4, the outermost SrRuO_Three If the film 11 is a single crystal, there may be a plurality of crystal grains in the recess. The figure shows SrRuO with two crystal grains._ThreeThe membrane 11 is shown.
[0076]
The larger the hole diameter of the recess on the surface of the plug electrode 10 is, the SrRuO that becomes the crystal nucleus in the recess._Three Information on the crystal of the film 11 is easily transmitted to the lower capacitor electrode 14, but if it is too large, SrRuO on the outermost surface in the depression_Three Since the film 11 becomes polycrystalline or twinned, it is ensured that the single crystal SrRuO_Three In order to obtain the film 11, it is necessary to set the diameter of the recess in the surface of the plug electrode 10 to 50 nm or less.
[0077]
In this embodiment, the Ru film having a depression on the surface is used as the plug electrode 10. However, since the above-described advantage of the Ru film can be obtained even without a depression on the surface, a Ru film having no depression on the surface is plugged. Even when used as an electrode, a DRAM cell superior to the conventional one can be realized (the same applies to other embodiments).
[0078]
(Second Embodiment)
FIG. 5 is a process sectional view showing a method of manufacturing a DRAM memory cell according to the second embodiment of the present invention. In addition, the same code | symbol as FIGS. 1-3 is attached | subjected to the part corresponding to FIGS.
[0079]
The manufacturing method of the present embodiment is different from that of the first embodiment in a step after the step of FIG.
[0080]
That is, following the step of FIG. 2C, as shown in FIG. 5A, amorphous SrRuO serving as a lower capacitor electrode is formed._Three A film 14 is deposited on the entire surface by sputtering. Then, SrRuO is obtained by heat treatment at 400 to 500 ° C. for 2 to 10 hours._Three The film 14 is crystallized.
[0081]
Next, as shown in FIG. 5B, single-crystal SrRuO_ThreeThe film 14 is patterned to form the lower capacitor electrode 14. Note that crystallization may be performed after patterning.
[0082]
Next, as shown in FIG. 5C, amorphous (Ba, Sr) TiO that becomes the capacitor insulating film 15 is formed._Three After the film is deposited on the entire surface by the CVD method, this is heat-treated to thereby form a single crystal (Ba, Sr) TiO._Three A capacitor insulating film 15 made of is formed.
[0083]
Finally, as shown in FIG. 5C, amorphous SrRuO serving as the upper capacitor electrode 16 is formed._ThreeA film is deposited on the entire surface by CVD, and then this amorphous SrRuO_ThreeAfter the film is crystallized by heat treatment, it is patterned to form a single crystal SrRuO._ThreeThe upper capacitor electrode 16 is formed to complete the DRAM memory.
[0084]
In the present embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the present embodiment, the SiN film 12 and the third interlayer insulating film 13 are not formed, so that the process is compared with the first embodiment. Can be simplified.
[0085]
(Third embodiment)
FIG. 6 is a process sectional view showing a method of manufacturing a DRAM memory cell according to the third embodiment of the present invention.
[0086]
The manufacturing method of this embodiment is different from that of the first embodiment in a post-process than the process of FIG. Also in this embodiment, the SiN film 12 and the third interlayer insulating film 13 are not formed.
That is, following the step of FIG. 2C, as shown in FIG. 6A, amorphous SrRuO serving as a lower capacitor electrode is formed._Three The film 14 has a substrate temperature of 400 to 500 ° C., a film forming pressure of 1 Pa or less, Ru (THD)_Three And Sr (THD)₂ And O₂ It is formed by the CVD method using
[0087]
At this time, since the film formation pressure is a sufficiently low pressure of 1 Pa or less, SrRuO_Three The film 14 is SrRuO._ThreeSince it grows from the film 11, as shown in FIG._Three The film 14 is selectively formed only on the plug electrode 10 and its periphery. Thereafter, amorphous SrRuO is obtained by heat treatment at 400 to 500 ° C. for 2 to 10 hours._Three 14 is crystallized.
[0088]
Next, as shown in FIG. 6B, amorphous (Ba, Sr) TiO that becomes the capacitor insulating film 15 is formed._Three After the film is deposited on the entire surface by the CVD method, this is heat-treated to thereby form a single crystal (Ba, Sr) TiO._Three A capacitor insulating film 15 made of is formed.
[0089]
Finally, as shown in FIG. 5B, amorphous SrRuO serving as the upper capacitor electrode 16 is formed._ThreeA film is deposited on the entire surface by CVD, followed by amorphous SrRuO._ThreeAfter the film is crystallized by heat treatment, it is patterned to form a single crystal SrRuO._ThreeThe upper capacitor electrode 16 is formed to complete the DRAM memory.
[0090]
In the present embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the present embodiment, the SiN film 12 and the third interlayer insulating film 13 are not formed, so that the process is compared with the first embodiment. Can be simplified.
[0091]
Also, as in this embodiment, SrRuO_Three In the case where the lower capacitor electrode 14 is formed by selectively growing a film, the capacitor arrangement can be made fine by arranging the capacitors at a quarter pitch as shown in FIG. become.
[0092]
(Fourth embodiment)
The DRAM cell of this embodiment is structurally different from that of the first embodiment in that the inside of the recess at the center of the surface of the plug electrode 10 is formed in SrRuO._ThreeInstead of embedding with film 11, SrRuO_Three And embedded with a single crystal Pt film having a lattice constant close to that of the film.
[0093]
In addition, the difference in process is that single crystal SrRuO is formed inside the recess in the step of FIG._ThreeInstead of forming the film 11, an amorphous Pt film is deposited on the entire surface by sputtering or CVD, and then the excess amorphous Pt film outside the depression is removed by the CMP method, and then heat treatment at 700 ° C. or higher is performed on the inside of the depression. It is to promote the Pt grain growth of the Pt film and form a single crystal Pt film.
[0094]
In this embodiment, the same effects as those in the first embodiment can be obtained, and the order of the CMP process and the heat treatment process, the number of crystal grains in the depression, and other various modifications can be performed in the same manner as in the first embodiment. It is.
[0095]
In the DRAM cells of the second and third embodiments, SrRuO_ThreeThe same effect can be obtained even if the film 11 is replaced with a single crystal Pt film.
[0096]
(Fifth embodiment)
The DRAM cell of this embodiment is structurally different from that of the first embodiment in that the inside of the recess at the center of the surface of the plug electrode 10 is formed in SrRuO._ThreeInstead of embedding with film 11, SrRuO_Three Single crystal SrTiO having the same perovskite structure_Three It is embedded in a film.
[0097]
In addition, the difference in process is that single crystal SrRuO is formed inside the recess in the step of FIG._ThreeInstead of forming the film 11, the substrate temperature is 300 to 400 ° C., Ti (t-OBu)₂ (THD)₂ And Sr (THD)₂ And O₂ Amorphous SrTiO by CVD using a mixed gas with_Three A film is deposited on the entire surface, followed by excess amorphous SrTiO outside the depression._Three After the film is removed by CMP, the amorphous SrTiO inside the depression is subjected to heat treatment at 600 ° C. or higher._Three It is to crystallize the film.
[0098]
In this embodiment, single crystal SrTiO which is an insulating film as a nucleus of single crystallization_Three A film is used, but single crystal SrTiO_Three Since the film exists only at the center of the plug electrode 10, the lower capacitor electrode 14 and the plug electrode 10 can be electrically connected.
[0099]
The single crystallization nucleus is SrTiO._Three BaTiO is not limited to the film_Three Film and (Ba, Sr) TiO_Three Other insulating films having a perovskite structure such as a film can also be used as crystallization nuclei.
[0100]
Single crystallized SrTiO_Three Since the outermost surface of the film is the most stable surface in terms of energy, the single crystal SrRuO on it_ThreeAs a result, the cell dependence of the capacitor characteristics can be eliminated.
[0101]
In this embodiment, the same effects as those in the first embodiment can be obtained, and the order of the CMP process and the heat treatment process, the number of crystal grains in the depression, and other various modifications can be performed in the same manner as in the first embodiment. It is.
[0102]
In the DRAM cells of the second and third embodiments, SrRuO_ThreeThe film 11 is made of single crystal SrTiO._Three Similar effects can be obtained by replacing the insulating film having a perovskite structure such as a film.
[0103]
The present invention is not limited to the above embodiment. For example, in the above embodiment, (Ba, Sr) TiO 2 is used as the material of the capacitor insulating film._Three In the case of using SrTiO,_Three , BaTiO_Three , PbTiO_Three , Bi_Four Ti_Three O₁₂, SrBi₂ Ta₂ O₉ , Pb (Zr, Ti) O_Three , (Pb, La) (Zr, Ti) O_Three Similar effects can be obtained even when other insulating materials such as the above are used.
[0104]
In the above embodiment, the case of a capacitor of a DRAM memory cell has been described. However, the present invention can also be applied to other capacitors such as a capacitor of an FRAM memory cell.
[0105]
In addition, various modifications can be made without departing from the scope of the present invention.
[0106]
【The invention's effect】
As described above in detail, according to the present invention, a plug electrode having a depression on the surface and embedded in a crystalline substance is used on the lower capacitor electrode made of a conductive film having a perovskite structure. A semiconductor device having a capacitor in which a capacitor insulating film made of a metal oxide dielectric film having a perovskite structure is formed and a method for manufacturing the same can be easily realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a DRAM cell according to a first embodiment of the present invention.
2 is a process cross-sectional view illustrating a method for manufacturing the DRAM memory cell of FIG. 1;
3 is a process cross-sectional view illustrating the method for manufacturing the DRAM memory cell subsequent to FIG. 2; FIG.
4 is a cross-sectional view showing a modification of the DRAM memory cell of FIG. 1;
FIG. 5 is a process sectional view showing a method for manufacturing a DRAM memory cell according to a second embodiment of the present invention;
FIG. 6 is a process sectional view showing a method of manufacturing a DRAM memory cell according to a third embodiment of the present invention.
FIG. 7 is a plan view showing the arrangement of capacitors of the DRAM memory cell;
FIG. 8 shows SrRuO as an electrode material of a conventional capacitor._ThreeSectional view showing a method of manufacturing a DRAM memory cell using
FIG. 9 shows conventional SrRuO._Three Process cross-sectional view showing the method of single crystallization of the film
FIG. 10 shows SrRuO as a conventional upper capacitor electrode._Three Cross-sectional view for explaining the problems of the single crystallization method of the film
FIG. 11 is a cross-sectional view showing a process of removing excess Ru film by CMP or RIE
[Explanation of symbols]
1,71 ... p-type Si substrate
2, 72 ... element isolation region
3, 73 ... Gate insulating film
4, 74 ... Gate electrode (word line)
5,75 ... n⁺ Type drain diffusion layer
6,76 ... n⁺Type source diffusion layer
7, 77 ... first interlayer insulating film
8, 78 ... bit line
9, 79 ... second interlayer insulating film
10, 82 ... plug electrode
11 ... SrRuO_Three film
12, 83 ... SiN film
13 ... Third interlayer insulating film
14, 85 ... SrRuO_Three Film (lower capacitor electrode)
15, 86 ... (Ba, Sr) TiO_ThreeFilm (capacitor insulation film)
16, 87 ... SrRuO_Three Membrane (upper capacitor electrode)
80 ... Ti film
81 ... TiN film
84 ... Third interlayer insulating film

Claims (8)

A lower capacitor electrode formed on a semiconductor substrate and made of a single crystal SrRuO ₃ film having a perovskite structure;
A capacitor insulating film formed on the lower capacitor electrode and made of a single crystal metal oxide dielectric film having a perovskite structure;
An upper capacitor electrode formed on the capacitor insulating film;
And connecting the semiconductor substrate and the lower capacitor electrode has a recess in a portion in contact with the lower capacitor electrode, the interior of the recess is a plug electrodes embedded in SrRuO ₃ film, the SrRuO ₃ film The plug electrode having at least an outermost surface of a single crystal, and
The lower capacitor electrode is used the SrRuO ₃ film buried in said recess crystal nucleus, by heat treatment amorphous SrRuO ₃ film in contact with the SrRuO ₃ film is obtained by crystallization,
The size of the recess is a size capable of forming a single crystal by heat treatment at least the outermost surface of the amorphous SrRuO ₃ film embedded in the recess.   The semiconductor device according to claim 1, wherein the upper capacitor electrode is made of a conductive film having a perovskite structure.   The semiconductor device according to claim 1, wherein an opening diameter of the recess is 50 nm or less.   The semiconductor device according to claim 1, wherein the plug electrode is made of Ru.   The semiconductor device according to claim 1, wherein the upper capacitor electrode is a conductive film having a perovskite structure, and a hole diameter of the recess is 50 nm or less. Forming a plug electrode having a depression on the surface, connecting the semiconductor substrate and a lower capacitor electrode formed in a later step on the semiconductor substrate;
Filling the inside of the depression with a SrRuO ₃ film having at least an outermost surface of a single crystal;
Forming an amorphous SrRuO ₃ film having a perovskite structure at the time of crystallization so as to be in contact with the SrRuO ₃ film whose outermost surface is a single crystal;
A step of forming a single crystal SrRuO ₃ film having a perovskite structure as a lower capacitor electrode by crystallizing the amorphous SrRuO ₃ film by heat treatment using the SrRuO ₃ film having at least the outermost surface as a single crystal. When,
Forming a capacitor insulating film made of a single crystal metal oxide dielectric film having a perovskite structure on the single crystal SrRuO ₃ film;
And a step of forming an upper capacitor electrode on the capacitor insulating film. The step of embedding the inside of the recess with the SrRuO ₃ film having at least the outermost surface of the single crystal is performed by filling the entire surface of the amorphous SrRuO ₃ film thicker than one half of the opening diameter of the recess so as to fill the inside of the recess. 7. A step of depositing the amorphous SrRuO ₃ film outside the depression, a step of removing the amorphous SrRuO ₃ film outside the depression, and a step of crystallizing the amorphous SrRuO ₃ film remaining inside the depression. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The method of manufacturing a semiconductor device according to claim 6, wherein the plug electrode is made of Ru.

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