JP2007067433A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having such a structure that a capacitor can be readily realized, in which a capacitor insulating layer made of a metal oxide dielectric film with perovskite structure is formed, on a lower capacitor electrode which is connected with a semiconductor substrate through a plug electrode and is made of an electric conductive film with perovskite structure. <P>SOLUTION: This semiconductor device is provided with the lower capacitor electrode 14 made of the electric conductive film which is formed on the semiconductor substrate 1 and has a perovskite structure, the capacitor insulating layer 15 made of the metal oxide dielectric film which is formed on the lower capacitor electrode 14 and has the perovskite structure, an upper capacitor electrode 16 formed on the capacitor insulating layer 15, and the plug electrode 10 which connects the lower capacitor electrode 14 with the semiconductor substrate 1 and is made from ruthenium. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a capacitor in which a lower capacitor electrode and a capacitor insulating film have a perovskite structure, and the lower capacitor electrode is connected to a semiconductor substrate via a plug electrode.

  In recent years, along with the high integration of semiconductor integrated circuits, the miniaturization of elements continues to progress, and for example, the cell area of capacitors has become very small. When the cell area is reduced, the capacitance of the capacitor is also reduced. However, there is a demand that the capacitance of the capacitor cannot be reduced so much in terms of sensitivity and soft error.

  As a method for securing the capacitance, a method of forming a capacitor three-dimensionally to increase the cell area as much as possible and a method of using an insulating film having a high dielectric constant for the capacitor insulating film are being studied.

As a typical insulating film having a high dielectric constant, an oxide dielectric film such as a (Ba, Sr) TiO ₃ film is known. When this kind of oxide dielectric film is used as a capacitor insulating film, it is not oxidized or oxidized in order to prevent a low dielectric constant layer from being formed at the interface between the capacitor electrode and the capacitor insulating film. It is necessary to form the capacitor electrode with a material exhibiting metal conductivity.

Recently, the use of SrRuO ₃ having the same crystal structure (perovskite structure) as (Ba, Sr) TiO ₃ has been studied as such an electrode material. FIG. 10 is a process cross-sectional view of a DRAM memory cell using SrRuO ₃ as a capacitor electrode material.

  To explain this, first, as shown in FIG. 8A, an element isolation region 72 is formed by STI (Shallow Trench Isolation) on the surface of a p-type Si substrate 71.

Next, as shown in FIG. 6A, a gate insulating film 73, a gate electrode (word line) 74, an n ⁺ type drain diffusion layer 75, and an n ⁺ type source diffusion layer 76 are formed, and then a first interlayer insulation is formed. After the film 77 is deposited and the surface is flattened, a contact hole is opened in the first interlayer insulating film (SiO ₂ film) 77 to form a bit line 78.

Next, as shown in FIG. 6A, after depositing a second interlayer insulating film (SiO ₂ film) 79 and planarizing the surface, contact holes are opened in the first and second interlayer insulating films 77, 79. The inside of the hole is filled with a plug electrode 82 via a Ti film 80 and a TiN film 81.

Next, as shown in FIG. 8B, after a SiN film 83 and a third interlayer insulating film (SiO ₂ film) 84 are deposited and the surface is flattened, the plug electrodes 82 are formed on these insulating films 83 and 84. A via hole is opened.

Next, as shown in FIG. 8C, an SrRuO ₃ film to be the lower capacitor electrode 85 is deposited on the entire surface by sputtering or CVD so as to fill the inside of the via hole, and then excess SrRuO outside the via hole. _{The three} films are removed by a CMP (Chemical Mechanical Polishing) method to form the lower capacitor electrode 85. Thereafter, the third interlayer insulating film 84 is selectively removed by etching.

Finally, as shown in FIG. 8D, a capacitor insulating film 86 made of (Ba, Sr) TiO ₃ is deposited on the entire surface by the CVD method, and then an SrRuO ₃ film to be the upper capacitor electrode 87 is deposited by the CVD method. After being deposited on the entire surface, this SrRuO ₃ film is processed to form an upper capacitor electrode 87, thereby completing a DRAM memory cell.

  Here, in order to increase the capacitor capacity and suppress the leakage current, it is desirable that the lower capacitor electrode 85, the capacitor insulating film 86, and the upper capacitor electrode 87 are epitaxially grown.

For this purpose, the SrRuO ₃ film that is the lower capacitor electrode 85 needs to be single-crystallized. The reported method for single crystallization of the SrRuO ₃ film is as follows.

  First, as shown in FIG. 9A, an AlTiN film 92 is deposited on a single crystal Si substrate 91 by a sputtering method. Here, the AlTiN film 92 is epitaxially grown on the single crystal Si substrate 91 and becomes a single crystal over the entire surface.

  Next, as shown in FIG. 9B, a Pt film 93 is deposited on the AlTiN film 92 by sputtering. Similarly, this Pt film 93 also becomes a single crystal over the entire surface.

Finally, as shown in FIG. 9C, a SrRuO ₃ film 94 is deposited on the Pt film 93 by sputtering. Similarly, the SrRuO ₃ film 94 becomes a single crystal over the entire surface.

If a single crystal SrRuO ₃ film that is the lower capacitor electrode 85 is formed by such a method, the (Ba, Sr) TiO ₃ film that is the capacitor insulating film 86 can also be single-crystallized in the capacitor portion. Since the SrRuO ₃ film as the capacitor electrode 87 also has the same perovskite structure, it can be single-crystallized in the capacitor portion, and a capacitor having good characteristics can be realized.

However, in an actual DRAM, a gate electrode (word line) 74 and a bit line 78 for operating the transistor are wired between the Si substrate 71 and the lower capacitor electrode 85, and the lower capacitor electrode 85 is n ^+. It must be connected to the type source diffusion layer 76 via a submicron-sized plug electrode 82, and the aspect ratio of the contact hole for embedding the plug electrode 82 increases as the generation of LSI advances.

  Thus, when the size of the plug electrode 82 is reduced and the aspect ratio is increased, the Si-based material conventionally used as the plug electrode material cannot be used because of its high resistance. Instead, Ru, W, etc. Although it is necessary to use a low-resistance metal, it is very difficult to make a single crystal of this kind of metal.

Further, as shown in FIG. 10, if a plug electrode 82 whose upper surface is lower than the opening surface of the contact hole is formed and a single crystal SrRuO ₃ / Pt laminated film 88 is formed only on the surface of the plug electrode 82, It is possible to single crystallize the SrRuO ₃ film as the upper capacitor electrode 87 formed thereon.

The single crystal SrRuO ₃ / Pt laminated film 88 is formed by embedding and forming an amorphous SrRuO ₃ / Pt laminated film in the unfocused portion of the contact hole on the plug electrode 82, and using laser annealing or the like. And a single crystallization step.

However, when the size of the plug electrode 82 is about submicron, it is difficult to single-crystal the amorphous SrRuO ₃ / Pt laminated film on the plug electrode 82 even if laser annealing or the like is used, and twin crystals and polycrystals are formed. As a result, there is a problem that the SrRuO ₃ film as the lower capacitor electrode 85 also becomes twinned or polycrystalline. In the figure, 89 indicates a grain boundary.

As described above, in a DRAM cell which has been miniaturized, in order to secure a necessary capacity, a single crystal (Ba _, Sr ₎ TiO ₃ film having a high dielectric constant as a capacitor insulating film, and a single crystal SrRuO as lower and upper capacitor electrodes. It was proposed to use _three membranes.

  In order to form such a capacitor insulating film and the lower and upper capacitor electrodes, the plug electrode connecting the lower capacitor electrode and the Si substrate had to be a single crystal.

  However, in a highly miniaturized DRAM cell, it is necessary to use a metal such as Ru, which has a low resistance but is difficult to crystallize, as a material for the plug electrode. There was a problem.

As another method, there is a method in which an amorphous SrRuO ₃ film is buried in an unfilled portion of the contact hole in which the plug electrode is partially buried, and then single crystallized by laser annealing is used as a crystal nucleus. It was proposed.

However, in a finely advanced DRAM cell, the contact hole is also miniaturized, and it is difficult to single crystallize the amorphous SrRuO ₃ film buried above the fine contact hole by laser annealing. was there.

  The present invention has been made in view of the above circumstances, and its object is to connect a perovskite structure on a lower capacitor electrode connected to a semiconductor substrate via a plug electrode and made of a conductive film having a perovskite structure. It is an object of the present invention to provide a semiconductor device having a structure capable of easily realizing a capacitor formed with a capacitor insulating film made of a metal oxide dielectric film having a metal oxide.

[Constitution]
In order to achieve the above object, a semiconductor device according to the present invention includes a lower capacitor electrode formed on a semiconductor substrate and made of a conductive film having a perovskite structure, and a metal having a perovskite structure formed on the lower capacitor electrode. A capacitor insulating film made of an oxide dielectric film; an upper capacitor electrode formed on the capacitor insulating film; and a plug electrode made of ruthenium for connecting the lower capacitor electrode and the semiconductor substrate. It is characterized by.

  More specific embodiments of the present invention are as follows.

(1) The crystalline material is a conductive material having a perovskite structure.

(2) The upper capacitor electrode is composed of a conductive film having a perovskite structure.

(3) The crystalline substance is platinum.

(4) The crystalline substance is an insulator having a perovskite structure (more specifically, a metal oxide dielectric film or a metal oxide dielectric film having crystallinity close to the lattice constant of the metal oxide dielectric film) It is.

(5) The lower capacitor electrode includes ARuO ₃ (A represents at least one element selected from Sr, Ba, Ca, La, and Nd), and (Sr, RE) CoO ₃ (RE represents La, Pr, Sm). And at least one element selected from Nd).

(6) a capacitor insulating _{film, (Ba, Sr) TiO 3} , SrTiO 3, BaTiO 3, PbTiO 3, Bi 4 Ti 3 O 12, SrBi 2 Ta 2 O 9, Pb (Zr, Ti) O 3 or ( Pb, La) (Zr, Ti) O ₃ .

  According to the present invention, a semiconductor device having a capacitor in which a capacitor insulating film made of a metal oxide dielectric film having a perovskite structure is formed on a lower capacitor electrode made of a conductive film having a perovskite structure can be easily realized. It becomes like this.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing a DRAM cell according to a first embodiment of the present invention.

  In the figure, reference numeral 1 denotes a p-type Si substrate, and an element isolation region 2 having an STI structure is formed on the surface of the p-type Si substrate 1.

In the transistor region isolated by the element isolation region 2, a MOS transistor including a gate insulating film 3, a gate electrode (word line) 4, an n ⁺ type drain diffusion layer 5 and an n ⁺ type source diffusion layer 6 is formed. ing.

A first interlayer insulating film (SiO ₂ film) 7 having a flat surface is formed on the p-type Si substrate 1, and the bit line 8 is connected to n via a contact hole opened in the first interlayer insulating film 7. Connected to the ⁺ type drain diffusion layer 5.

A second interlayer insulating film (SiO ₂ film) 9 having a flat surface is formed on the first interlayer insulating film 7, and through contact holes opened in the first and second interlayer insulating films 7, 9, A plug electrode 10 made of single crystal Ru is connected to the n ⁺ -type source diffusion layer 6.

A depression is formed at the center of the surface of the plug electrode 10, and the inside of the depression is filled with a single crystal SrRuO ₃ film 11. SrRuO ₃ film 11 may be a crystalline material having a lattice constant close to that in place of.

A SiN film 12 is formed on the second interlayer insulating film 9. The SiN film 12 has an opening in a region including the plug electrode 10, and a lower capacitor electrode 14 made of single crystal SrRuO ₃ is formed in contact with the plug electrode 10 through the opening. The lower capacitor electrode 14 is thicker than the SiN film 12.

A capacitor insulating film 15 made of single crystal (Ba, Sr) TiO ₃ is formed on the lower capacitor electrode 14. An upper capacitor electrode 16 made of single-crystal SrRuO ₃ is formed on the lower capacitor electrode 14 via a capacitor insulating film 15.

  Note that the capacitor insulating film 15 on the SiN film 12 other than the vicinity of the lower capacitor electrode 14 does not become single crystal but becomes amorphous or polycrystalline. When the temperature (single crystallization temperature) at the time of forming the capacitor insulating film 15 is low, it is amorphous. When exposed to a temperature higher than the single crystallization temperature, it becomes polycrystalline. The amorphous or polycrystalline portion has no problem because it does not serve as a capacitor insulating film.

According to such a configuration, a (Ba, Sr) TiO ₃ film having a high dielectric constant is used as the capacitor insulating film 15, and all of the respective films constituting the capacitor are single crystal films (perovskite structure). Therefore, it is possible to easily secure a necessary capacitor capacity and to effectively suppress an increase in leakage current.

  2 and 3 are process sectional views showing a method of manufacturing the DRAM memory cell of FIG.

First, as shown in FIG. 2A, an element isolation region 2 is formed by STI on the surface of a p-type Si substrate 1, followed by a gate insulating film 3, a gate electrode (word line) 4, an n ⁺ -type drain diffusion. Layer 5 and n ⁺ -type source diffusion layer 6 are formed.

  Next, as shown in FIG. 5A, after depositing a first interlayer insulating film 7 and planarizing the surface, a contact hole is formed in the first interlayer insulating film 7 to form a bit line 8; Subsequently, after the second interlayer insulating film 9 is deposited and the surface is flattened, contact holes are opened in the first and second interlayer insulating films 7 and 9.

Next, as shown in FIG. 2B, a substrate temperature of 200 to 450 ° C., a film forming pressure of 1 to 100 Pa, Ru (Cp) ₂ (Ar carrier) and O ₂ (O ₂ concentration in the atmosphere of 40% or less) are used. After depositing the Ru film to be the plug electrode 10 by the conventional CVD method, the excess Ru film outside the contact hole is removed by the CMP method or the etch-back method using reactive ion etching to thereby remove the contact hole. Plug electrode 10 is embedded and formed inside.

  At this time, when the excess Ru film is removed by the CMP method, a recess is formed in the central portion of the plug electrode 10 by reducing the film thickness of the Ru film deposited on the entire surface to about half of the diameter of the contact hole. To do. In the case of reactive ion etching, there is no particular limitation on the film thickness of the Ru film (plug electrode 10), and it is sufficient if it is not too thick (up to the aperture diameter). FIG. 11 shows a cross-sectional view of a process of removing an excess Ru film by a CMP method or a reactive ion etching (RIE) method.

Next, as shown in FIG. 2C, the substrate temperature is 200 to 400 ° C., the film forming pressure is 1 to 1000 Pa, and the CVD method using a mixed gas of Ru (THD) ₃ , Sr (THD) ₂ and O ₂ , An amorphous SrRuO ₃ film to be a single crystal SrRuO ₃ film 11 is deposited on the entire surface, and after removing the excess SrRuO ₃ film outside the depression by CMP, a plug electrode is formed by performing a heat treatment at 600 ° C. or higher. The central depression 10 is filled with a single crystal SrRuO ₃ film 11.

Next, as shown in FIG. 3D, a SiN film 12 and a third interlayer insulating film (SiO ₂ film) 13 are sequentially deposited, and then contact holes connected to the plug electrode 10 are formed in these insulating films 12 and 13. After the opening, an amorphous SrRuO ₃ film 14 to be the lower capacitor electrode is deposited on the entire surface by CVD so as to fill the contact hole. The film thickness of the SrRuO ₃ film 14 on the third interlayer insulating film 13 need not be thicker than that of the SiN film 12.

  The SiN film 12 is for preventing the capacitor insulating film 15 from coming into direct contact with the plug electrode 10 even if the contact hole formation position is shifted. This prevents an increase in leakage current due to misalignment.

Next, as shown in FIG. 3E, excess SrRuO ₃ film 14 outside the contact hole is removed by CMP, and the SrRuO ₃ film 14 is selectively left only inside the contact hole.

Thereafter, the SrRuO ₃ film 14 inside the contact hole is crystallized by heat treatment at 400 to 500 ° C. for 2 to 10 hours, thereby completing the lower capacitor electrode 14 made of single crystal SrRuO ₃ .

Next, as shown in FIG. 3F, the third interlayer insulating film 13 is removed by etching, and then an amorphous (Ba, Sr) TiO ₃ film to be a single crystal capacitor insulating film 15 is formed on the entire surface by CVD. After the deposition, this is heat-treated and crystallized to form a capacitor insulating film 15 made of single-crystal (Ba, Sr) TiO _{3 in a} portion in contact with the lower capacitor electrode 14.

Next, as shown in FIG. 6F, an amorphous SrRuO ₃ film 16 to be the upper capacitor electrode is deposited on the entire surface by the CVD method, and is then crystallized by heat treatment to thereby obtain a single crystal SrRuO ₃ film. 16 is formed.

Finally, by patterning the SrRuO ₃ film 12 of single crystal electrodes form, the DRAM memory cell shown in FIG. 1 is completed.

In this embodiment, when the lower capacitor electrode 14 is formed, the amorphous SrRuO ₃ film is crystallized by the heat treatment after removing the excess amorphous SrRuO ₃ film by the CMP method. After the amorphous SrRuO ₃ film is crystallized, the excess single crystal SrRuO ₃ film may be removed by CMP.

  Hereinafter, advantages of using the Ru film as the plug electrode 10 will be described.

To bury and form a Ru film in the contact hole, first, Ru (C ₆ H ₅ ) ₂ , Ru (CH ₃ C ₅ H ₄ ) ₂ , or Ru (C ₂ H ₅ C ₅ H ₄ ) ₂ and O After depositing on the entire surface by a CVD method at a film forming temperature of 300 ° C. or less using a mixed gas with ₂ , the Ru film outside the contact hole is removed by the CMP method. Instead of O _2, a substance that becomes an oxidizing atmosphere such as O ₃ , O radical, N ₂ O may be used.

  If the Ru film is formed under the above conditions, the Ru film can be formed with very good coverage, and the surface morphology of the Ru film is also good. Therefore, by using the Ru film embedding method, the plug electrode 10 made of Ru can be easily realized without generating a nest in the contact hole having a small opening diameter.

Since Ru is showing a metallic conductivity be oxidized similarly to the Ir, etc., even if a metal oxide of ₃ such SrRuO the material of the lower capacitor electrode 14, between the plug electrodes 10 and the lower capacitor electrode 14 There is no problem of increasing the contact resistance.

Since the contact surface between the Si substrate 1 and the plug electrode 10 uses O _{2 in the} film forming atmosphere, a very thin layer containing Ru, Si, and O is formed. This layer has the advantage of preventing the diffusion of Ru into the Si substrate 1 and lowering the contact resistance between the Si substrate 1 and the plug electrode 10. Moreover, there is no problem even if a barrier metal film such as a TiN film is formed on the contact surface between the Si substrate 1 and the plug electrode 10.

Further, when SrRuO ₃ is used as the material of the lower capacitor electrode 14 as in the present embodiment, since the Ru element is included in both the plug electrode 10 and the lower capacitor electrode 14, the plug electrode 10, the lower capacitor electrode 14, The electrical bondability of the is very good.

In this embodiment, the depression on the surface of the plug electrode 10 is filled with the single crystal SrRuO ₃ film 14. However, as shown in FIG. 4, if the outermost SrRuO ₃ film 11 is a single crystal, There may be a plurality of crystal grains. In the figure, the SrRuO ₃ film 11 having two crystal grains is shown.

In addition, the larger the hole diameter of the depression on the surface of the plug electrode 10 is, the easier it is to transmit the crystal information of the SrRuO ₃ film 11 serving as the crystal nucleus in the depression to the lower capacitor electrode 14. Since the SrRuO ₃ film 11 on the outermost surface becomes polycrystalline or twinned, in order to obtain the single crystal SrRuO ₃ film 11 with certainty, it is necessary to make the hole diameter of the recess on the surface of the plug electrode 10 50 nm or less. There is.

  In the present embodiment, the Ru film having a depression on the surface is used as the plug electrode 10. However, the above-described advantage of the Ru film can be obtained even if there is no depression on the surface. Therefore, the Ru film having no depression on the surface is plugged. Even when used as an electrode, a DRAM cell superior to the conventional one can be realized (the same applies to other embodiments).

(Second Embodiment)
FIG. 5 is a process sectional view showing a method of manufacturing a DRAM memory cell according to the second embodiment of the present invention. In addition, the same code | symbol as FIGS. 1-3 is attached | subjected to the part corresponding to FIGS. 1-3, and detailed description is abbreviate | omitted (it is the same also about other embodiment).

  The manufacturing method of the present embodiment is different from that of the first embodiment in a step after the step of FIG.

That is, following the step of FIG. 2C, as shown in FIG. 5A, an amorphous SrRuO ₃ film 14 to be the lower capacitor electrode is deposited on the entire surface by sputtering. Thereafter, the SrRuO ₃ film 14 is crystallized by heat treatment at 400 to 500 ° C. for 2 to 10 hours.

Next, as shown in FIG. 5B, the single-crystal SrRuO ₃ film 14 is patterned to form the lower capacitor electrode 14. Note that crystallization may be performed after patterning.

Next, as shown in FIG. 5C, an amorphous (Ba, Sr) TiO ₃ film to be the capacitor insulating film 15 is deposited on the entire surface by the CVD method, and then heat-treated to form a single crystal (Ba, A capacitor insulating film 15 made of Sr) TiO ₃ is formed.

Finally, as shown in FIG. 6C, an amorphous SrRuO ₃ film to be the upper capacitor electrode 16 is deposited on the entire surface by the CVD method, and then this amorphous SrRuO ₃ film is crystallized by heat treatment. By patterning this, the upper capacitor electrode 16 made of single crystal SrRuO ₃ is formed, and the DRAM memory is completed.

  In the present embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the present embodiment, the SiN film 12 and the third interlayer insulating film 13 are not formed, so that the process is compared with the first embodiment. Can be simplified.

(Third embodiment)
FIG. 6 is a process sectional view showing a method of manufacturing a DRAM memory cell according to the third embodiment of the present invention.

The manufacturing method of this embodiment is different from that of the first embodiment in a post-process than the process of FIG. Also in this embodiment, the SiN film 12 and the third interlayer insulating film 13 are not formed. That is, following the step of FIG. 2C, as shown in FIG. 6A, amorphous SrRuO _{3 serving} as a lower capacitor electrode is formed. The film 14 is formed by a CVD method using Ru (THD) ₃ , Sr (THD) ₂ and O ₂ at a substrate temperature of 400 to 500 ° C., a film forming pressure of 1 Pa or less.

At this time, since the deposition pressure is a sufficiently low pressure of 1 Pa or less, the SrRuO ₃ film 14 grows from the SrRuO ₃ film 11, so that the SrRuO ₃ film 14 is plug electrode as shown in FIG. 10 and only on its periphery. Thereafter, amorphous SrRuO ₃ 14 is crystallized by heat treatment at 400 to 500 ° C. for 2 to 10 hours.

Next, as shown in FIG. 6B, after an amorphous (Ba, Sr) TiO ₃ film to be the capacitor insulating film 15 is deposited on the entire surface by the CVD method, this is heat-treated to thereby form a single crystal (Ba, A capacitor insulating film 15 made of Sr) TiO ₃ is formed.

Finally, as shown in FIG. 4B, an amorphous SrRuO ₃ film to be the upper capacitor electrode 16 is deposited on the entire surface by the CVD method, and then the amorphous SrRuO ₃ film is crystallized by heat treatment. Then, the upper capacitor electrode 16 made of single-crystal SrRuO ₃ is formed, thereby completing the DRAM memory.

  In the present embodiment, the same effect as that of the first embodiment can be obtained. Further, according to the present embodiment, the SiN film 12 and the third interlayer insulating film 13 are not formed, so that the process is compared with the first embodiment. Can be simplified.

Further, in the case where the lower capacitor electrode 14 is formed by selectively growing the SrRuO ₃ film as in the present embodiment, the capacitor is arranged at a ¼ pitch as shown in FIG. The capacitor arrangement can be made fine.

(Fourth embodiment)
The DRAM cell of the present embodiment is structurally different from that of the first embodiment in that a single crystal having a lattice constant close to that of SrRuO ₃ is used instead of embedding the inside of the recess at the center of the surface of the plug electrode 10 with the SrRuO ₃ film 11. This is because it is embedded with a Pt film.

Further, the process is different in that an amorphous Pt film is deposited on the entire surface by sputtering or CVD instead of forming the single crystal SrRuO ₃ film 11 inside the recess in the step of FIG. After removing the excess amorphous Pt film outside the depression by the CMP method, the Pt grain growth of the Pt film inside the depression is promoted by a heat treatment at 700 ° C. or more to form a single crystal Pt film.

  In this embodiment, the same effects as in the first embodiment can be obtained, and the order of the CMP process and the heat treatment process, the number of crystal grains in the recess, and other various modifications are possible as in the first embodiment. It is.

In the DRAM cells of the second and third embodiments, the same effect can be obtained even if the SrRuO ₃ film 11 is replaced with a single crystal Pt film.

(Fifth embodiment)
The DRAM cell of this embodiment is structurally different from that of the first embodiment in that a single crystal having the same perovskite structure as that of SrRuO ₃ is used instead of embedding a recess at the center of the surface of the plug electrode 10 with the SrRuO ₃ film 11. This is because it is embedded with a SrTiO ₃ film.

Moreover, the different points in the process, instead of forming a SrRuO ₃ film 11 of single crystal inside recess in the step of FIG. 2 (c), the substrate temperature 300~400 ℃, Ti (t-OBu ) 2 (THD) _An amorphous SrTiO ₃ film is deposited on the entire surface by a CVD method using a mixed gas of ₂ , Sr (THD) ₂ and O _2, and then the excess amorphous SrTiO ₃ film outside the depression is removed by the CMP method, and then 600 It is to crystallize the amorphous SrTiO ₃ film inside the depression by a heat treatment at a temperature of 0 ° C. or higher.

In the present embodiment, a single crystal SrTiO ₃ film, which is an insulating film, is used as the nucleus for single crystallization. However, since the single crystal SrTiO ₃ film exists only in the central portion of the plug electrode 10, The plug electrode 10 can be electrically connected.

Further, the single crystallization nucleus is not limited to the SrTiO ₃ film, and an insulating film having another perovskite structure such as a BaTiO ₃ film or a (Ba, Sr) TiO ₃ film can also be used as the crystallization nucleus.

Further, since the outermost surface of the single crystallized SrTiO ₃ film is the most stable surface energy, orientation is aligned to the substrate orientation of the lower capacitor electrode 14 made of single-crystal SrRuO ₃ thereon, as a result As a result, the cell dependence of the capacitor characteristics can be eliminated.

  In this embodiment, the same effects as in the first embodiment can be obtained, and the order of the CMP process and the heat treatment process, the number of crystal grains in the recess, and other various modifications are possible as in the first embodiment. It is.

In the DRAM cells of the second and third embodiments, the same effect can be obtained even if the SrRuO ₃ film 11 is replaced with an insulating film having a perovskite structure such as a single crystal SrTiO ₃ film.

In addition, this invention is not limited to the said embodiment. For example, in the above embodiment, materials as (Ba, Sr) of the capacitor insulating film has been described using a _{TiO 3, SrTiO 3, BaTiO 3} , PbTiO 3, Bi 4 Ti 3 O 12, SrBi 2 Ta 2 O ₉ , the same effect can be obtained by using other insulating materials such as Pb (Zr, Ti) O ₃ and (Pb, La) (Zr, Ti) O ₃ .

  In the above embodiments, the case of a capacitor of a DRAM memory cell has been described. However, the present invention can also be applied to other capacitors such as a capacitor of an FRAM memory cell.

  In addition, various modifications can be made without departing from the scope of the present invention.

Sectional drawing which shows the DRAM cell which concerns on the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing method of the DRAM memory cell of FIG. Process sectional drawing which shows the manufacturing method of the DRAM memory cell following FIG. Sectional drawing which shows the modification of the DRAM memory cell of FIG. Sectional drawing which shows the manufacturing method of the DRAM memory cell based on the 2nd Embodiment of this invention Process sectional drawing which shows the manufacturing method of the DRAM memory cell based on the 3rd Embodiment of this invention Plan view showing the arrangement of capacitors of the DRAM memory cell Sectional views illustrating a method of manufacturing the DRAM memory cell using a SrRuO ₃ as an electrode material of a conventional capacitor Sectional views illustrating a conventional SrRuO ₃ film methods monocrystallization Sectional view for explaining a problem of the method of the single crystal of the SrRuO ₃ film as a conventional upper capacitor electrode Sectional drawing which shows the process of removing excess Ru film | membrane by CMP method or RIE method

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,71 ... p-type Si substrate, 2,72 ... Element isolation region, 3,73 ... Gate insulating film, 4,74 ... Gate electrode (word line), 5,75 ... N ^<+> type | mold drain diffusion layer, 6,76 ... n ⁺ -type source diffusion layer, 7,77 ... first interlayer insulating film, 8,78 ... bit lines, 9,79 ... second interlayer insulating film, 10,82 ... plug electrode, 11 ... SrRuO ₃ film, 12, 83 ... SiN film, 13 ... third interlayer insulating film, 14,85 ... SrRuO ₃ film (lower capacitor electrode), 15,86 ... (Ba, Sr ) TiO 3 film (capacitor insulating film), 16,87 ... SrRuO ₃ Film (upper capacitor electrode), 80 ... Ti film, 81 ... TiN film, 84 ... third interlayer insulating film.

Claims (2)

A lower capacitor electrode formed on a semiconductor substrate and made of a conductive film having a perovskite structure;
A capacitor insulating film formed on the lower capacitor electrode and made of a metal oxide dielectric film having a perovskite structure;
An upper capacitor electrode formed on the capacitor insulating film;
A semiconductor device comprising: the lower capacitor electrode and the semiconductor substrate; and a plug electrode made of ruthenium. The semiconductor device according to claim 1, wherein the conductive film is a SrRuO ₃ film.

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