JP4073464B2 - リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル - Google Patents
リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル Download PDFInfo
- Publication number
- JP4073464B2 JP4073464B2 JP2006343089A JP2006343089A JP4073464B2 JP 4073464 B2 JP4073464 B2 JP 4073464B2 JP 2006343089 A JP2006343089 A JP 2006343089A JP 2006343089 A JP2006343089 A JP 2006343089A JP 4073464 B2 JP4073464 B2 JP 4073464B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- checkpoint
- processor
- read buffer
- computer system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000015654 memory Effects 0.000 title claims abstract description 218
- 239000000872 buffer Substances 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 claims description 41
- 230000004044 response Effects 0.000 claims description 3
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000012545 processing Methods 0.000 abstract description 60
- 230000007246 mechanism Effects 0.000 abstract description 11
- 230000008569 process Effects 0.000 description 12
- 238000011084 recovery Methods 0.000 description 11
- 238000011010 flushing procedure Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 9
- 230000000873 masking effect Effects 0.000 description 8
- 230000008901 benefit Effects 0.000 description 7
- 239000003999 initiator Substances 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 238000004590 computer program Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 208000000044 Amnesia Diseases 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 231100000863 loss of memory Toxicity 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
- G06F11/1407—Checkpointing the instruction stream
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Debugging And Monitoring (AREA)
Description
Claims (5)
- チェツクポイント・メモリ(213)と基本メモリ(212)を有するコンピュータ・システム200の稼動中のチェックポイント状態を維持する方法であって、該チェツクポイント・メモリが、後入れ先出しリード・バッファ・メモリ(216)を含み、該基本メモリと該後入れ先出しリード・バッファ・メモリが同じポートに接続され、更に該コンピュータ・システム(200)が、各プロッセサが関連したプロッセサ・キャッシュ・メモリ(42)を有する少なくとも1つのプロセッサ(218)を含む、該方法において、以下のステップをそなえることを特徴とする、
該プロッセサ・キャッシュ・メモリに記憶されたデータを該基本メモリにコピーして該基本メモリにおけるチェックポイントを確立し(250)、該後入れ先出しリード・バッファ・メモリに記憶されたデータを廃棄するステップ(252)であって、該チェックポイントが該コンピュータシステム200の稼働中のチェックポイント状態を表す該ステップと、
該基本メモリからデータを読出すステップ(254)、
該後入れ先出しリード・バッファ・メモリ内に該読出したデータを記憶することにより該読出されたデータを捕獲するステップ(256)、
一定の期間が経過するか又は障害が発生するまで該読出すステップと捕獲するステップを繰り返すステップ(258)、および
該プロッセサ・キャッシュ・メモリに記憶されたデータを該基本メモリにコピーして該基本メモリにおけるチェックポイントを確立し、一定の期間が経過した時に、該後入れ先出しリード・バッファ・メモリに記憶されたデータを廃棄するステップ、
を備えることを特徴とする該方法。 - 前記コンピュータ・システムにおける前記障害の検出に応答して、前記後入れ先出しリード・バッファ・メモリに記憶された前記読出されたデータを前記基本メモリにコピーすることにより、障害が生じたより前に確立されたチェックポイントに前記基本メモリを戻すステップ(266)と、正常動作を再開するステップとを更に含む請求項1に記載の方法。
- 前記基本メモリと同じポートに接続され、さらに前記後入れ先出しリード・バッファ・メモリに接続されたシャドウ・メモリ(222)を更に備え、
該シャドウ・メモリの内容が前記基本メモリの内容を複写する様に、前記基本メモリに書き込まれた全てのデータを、最初に後入れ先出しリード・バッファ・メモリに記憶させないで、該シャドウ・メモリに記憶することにより、直接捕獲し、
前記コンピュータ・システムにおける障害の検出に応答して、該基本メモリが動作可能か否かをテストし(260)、
該基本メモリが動作可能で無い場合は、該後入れ先出しバッファ・メモリの内容を該シャドウ・メモリにコピーし、該障害が生じたより前に該基本メモリに対して確立されたチェックポイントに該シャドウ・メモリを戻し(262)、
該障害のある基本メモリの役割を該シャドウ・メモリに割り当て(264)、
該障害のある基本メモリの役割を実行する該シャドウ・メモリにより該コンピュータ・システムの動作を再開する
ことを特徴とする請求項2に記載の方法。 - 前記コンピュータ・システムが、複数のプロッセサを含み、各プロッセサが関連したプロッセサ・キャッシュ・メモリ(42)を有し、
前記コピーするステップは、同期した状態でプロッセサが関連したプロッセサ・キャッシュ・メモリをコピーする該プロセッサを含む、請求項3に記載の方法。 - 前記プロッセサ・キャッシュ・メモリをコピーするプロセッサの同期は、全てのプロッセサが、プロッセサに関連したプロッセサ・キャッシャ・、メモリのコピーが完了するまでプロッセサが正常稼働へ復帰するのを妨げることにより達成される請求項4に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/564,024 US5745672A (en) | 1995-11-29 | 1995-11-29 | Main memory system and checkpointing protocol for a fault-tolerant computer system using a read buffer |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52206097A Division JP2001515615A (ja) | 1995-11-29 | 1996-11-27 | リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007128540A JP2007128540A (ja) | 2007-05-24 |
JP4073464B2 true JP4073464B2 (ja) | 2008-04-09 |
Family
ID=24252868
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52206097A Withdrawn JP2001515615A (ja) | 1995-11-29 | 1996-11-27 | リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル |
JP2006343089A Expired - Fee Related JP4073464B2 (ja) | 1995-11-29 | 2006-12-20 | リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52206097A Withdrawn JP2001515615A (ja) | 1995-11-29 | 1996-11-27 | リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル |
Country Status (6)
Country | Link |
---|---|
US (1) | US5745672A (ja) |
EP (1) | EP0900420B1 (ja) |
JP (2) | JP2001515615A (ja) |
AT (1) | ATE203338T1 (ja) |
DE (1) | DE69614003T2 (ja) |
WO (1) | WO1997022045A2 (ja) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3086779B2 (ja) * | 1995-06-19 | 2000-09-11 | 株式会社東芝 | メモリ状態復元装置 |
US5737514A (en) * | 1995-11-29 | 1998-04-07 | Texas Micro, Inc. | Remote checkpoint memory system and protocol for fault-tolerant computer system |
TW379298B (en) * | 1996-09-30 | 2000-01-11 | Toshiba Corp | Memory updating history saving device and memory updating history saving method |
FR2773234B1 (fr) * | 1997-12-31 | 2003-07-25 | Sgs Thomson Microelectronics | Memoire a double acces pour processeur de signal numerique |
US6256753B1 (en) * | 1998-06-30 | 2001-07-03 | Sun Microsystems, Inc. | Bus error handling in a computer system |
US6230282B1 (en) * | 1998-07-03 | 2001-05-08 | Hewlett-Packard Company | Checkpoint computer system utilizing a FIFO buffer to re-synchronize the memory systems on the detection of an error |
US6338147B1 (en) * | 1998-10-29 | 2002-01-08 | International Business Machines Corporation | Program products for performing checkpoint/restart of a parallel program |
US6401216B1 (en) | 1998-10-29 | 2002-06-04 | International Business Machines Corporation | System of performing checkpoint/restart of a parallel program |
US6393583B1 (en) | 1998-10-29 | 2002-05-21 | International Business Machines Corporation | Method of performing checkpoint/restart of a parallel program |
US6622263B1 (en) * | 1999-06-30 | 2003-09-16 | Jack Justin Stiffler | Method and apparatus for achieving system-directed checkpointing without specialized hardware assistance |
US6810489B1 (en) * | 2000-09-06 | 2004-10-26 | Hewlett-Packard Development Company, L.P. | Checkpoint computer system utilizing a FIFO buffer to re-synchronize and recover the system on the detection of an error |
US7085955B2 (en) * | 2001-09-14 | 2006-08-01 | Hewlett-Packard Development Company, L.P. | Checkpointing with a write back controller |
US7058849B2 (en) | 2002-07-02 | 2006-06-06 | Micron Technology, Inc. | Use of non-volatile memory to perform rollback function |
US8336044B2 (en) * | 2002-10-09 | 2012-12-18 | Rpx Corporation | Method and system for deploying a software image |
US7024581B1 (en) | 2002-10-09 | 2006-04-04 | Xpoint Technologies, Inc. | Data processing recovery system and method spanning multiple operating system |
US7290166B2 (en) * | 2004-07-28 | 2007-10-30 | Intel Corporation | Rollback of data |
US7421617B2 (en) | 2004-08-30 | 2008-09-02 | Symantec Corporation | Systems and methods for optimizing restoration of stored data |
JP4165499B2 (ja) * | 2004-12-13 | 2008-10-15 | 日本電気株式会社 | コンピュータシステム及びそれを用いたフォールトトレラントシステム並びにその動作制御方法 |
USRE45632E1 (en) * | 2005-01-03 | 2015-07-28 | O'shantel Software L.L.C. | Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support |
US7840768B2 (en) * | 2005-12-13 | 2010-11-23 | Reliable Technologies, Inc. | Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support |
US7478276B2 (en) * | 2005-02-10 | 2009-01-13 | International Business Machines Corporation | Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor |
US7590885B2 (en) * | 2005-04-26 | 2009-09-15 | Hewlett-Packard Development Company, L.P. | Method and system of copying memory from a source processor to a target processor by duplicating memory writes |
US7409589B2 (en) * | 2005-05-27 | 2008-08-05 | International Business Machines Corporation | Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor |
US8396937B1 (en) * | 2007-04-30 | 2013-03-12 | Oracle America, Inc. | Efficient hardware scheme to support cross-cluster transactional memory |
US20100005218A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Enhanced cascade interconnected memory system |
US20100005220A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US20100005214A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Enhancing bus efficiency in a memory system |
US20100005212A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Providing a variable frame format protocol in a cascade interconnected memory system |
US20100005206A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | Automatic read data flow control in a cascade interconnect memory system |
US20100005219A1 (en) * | 2008-07-01 | 2010-01-07 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US7717752B2 (en) * | 2008-07-01 | 2010-05-18 | International Business Machines Corporation | 276-pin buffered memory module with enhanced memory system interconnect and features |
US20100106904A1 (en) * | 2008-10-23 | 2010-04-29 | Dell Products L.P. | Shadow raid cache memory |
US8127185B2 (en) * | 2009-01-23 | 2012-02-28 | Micron Technology, Inc. | Memory devices and methods for managing error regions |
US8671311B2 (en) | 2011-02-15 | 2014-03-11 | International Business Machines Corporation | Multiprocessor switch with selective pairing |
US8635492B2 (en) * | 2011-02-15 | 2014-01-21 | International Business Machines Corporation | State recovery and lockstep execution restart in a system with multiprocessor pairing |
US8930752B2 (en) | 2011-02-15 | 2015-01-06 | International Business Machines Corporation | Scheduler for multiprocessor system switch with selective pairing |
US9357649B2 (en) | 2012-05-08 | 2016-05-31 | Inernational Business Machines Corporation | 276-pin buffered memory card with enhanced memory system interconnect |
US9069701B2 (en) | 2012-12-11 | 2015-06-30 | International Business Machines Corporation | Virtual machine failover |
US9519315B2 (en) | 2013-03-12 | 2016-12-13 | International Business Machines Corporation | 276-pin buffered memory card with enhanced memory system interconnect |
Family Cites Families (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3588829A (en) * | 1968-11-14 | 1971-06-28 | Ibm | Integrated memory system with block transfer to a buffer store |
US4413327A (en) * | 1970-06-09 | 1983-11-01 | The United States Of America As Represented By The Secretary Of The Navy | Radiation circumvention technique |
US3761881A (en) * | 1971-06-30 | 1973-09-25 | Ibm | Translation storage scheme for virtual memory system |
US3736566A (en) * | 1971-08-18 | 1973-05-29 | Ibm | Central processing unit with hardware controlled checkpoint and retry facilities |
US3803560A (en) * | 1973-01-03 | 1974-04-09 | Honeywell Inf Systems | Technique for detecting memory failures and to provide for automatically for reconfiguration of the memory modules of a memory system |
US3889237A (en) * | 1973-11-16 | 1975-06-10 | Sperry Rand Corp | Common storage controller for dual processor system |
US3979726A (en) * | 1974-04-10 | 1976-09-07 | Honeywell Information Systems, Inc. | Apparatus for selectively clearing a cache store in a processor having segmentation and paging |
GB1509193A (en) * | 1974-04-17 | 1978-05-04 | Nat Res Dev | Computer systems |
US4020466A (en) * | 1974-07-05 | 1977-04-26 | Ibm Corporation | Memory hierarchy system with journaling and copy back |
US4044337A (en) * | 1975-12-23 | 1977-08-23 | International Business Machines Corporation | Instruction retry mechanism for a data processing system |
US4228496A (en) * | 1976-09-07 | 1980-10-14 | Tandem Computers Incorporated | Multiprocessor system |
US4373179A (en) * | 1978-06-26 | 1983-02-08 | Fujitsu Limited | Dynamic address translation system |
JPS5913783B2 (ja) * | 1978-09-18 | 1984-03-31 | 富士通株式会社 | 2重化フアイル方式 |
JPS55115121A (en) * | 1979-02-28 | 1980-09-04 | Nec Corp | Input and output control unit possible for duplicated recording |
JPS605024B2 (ja) * | 1979-09-04 | 1985-02-07 | ファナック株式会社 | 情報処理方式 |
US4403284A (en) * | 1980-11-24 | 1983-09-06 | Texas Instruments Incorporated | Microprocessor which detects leading 1 bit of instruction to obtain microcode entry point address |
US4426682A (en) * | 1981-05-22 | 1984-01-17 | Harris Corporation | Fast cache flush mechanism |
JPS5831651A (ja) * | 1981-08-20 | 1983-02-24 | Nec Corp | 電子交換機の再開処理方式 |
US4566106A (en) * | 1982-01-29 | 1986-01-21 | Pitney Bowes Inc. | Electronic postage meter having redundant memory |
US4459658A (en) * | 1982-02-26 | 1984-07-10 | Bell Telephone Laboratories Incorporated | Technique for enabling operation of a computer system with a consistent state of a linked list data structure after a main memory failure |
US4484273A (en) * | 1982-09-03 | 1984-11-20 | Sequoia Systems, Inc. | Modular computer system |
WO1984002409A1 (en) * | 1982-12-09 | 1984-06-21 | Sequoia Systems Inc | Memory backup system |
US4819154A (en) * | 1982-12-09 | 1989-04-04 | Sequoia Systems, Inc. | Memory back up system with one cache memory and two physically separated main memories |
FR2553541B1 (fr) * | 1983-10-17 | 1992-02-28 | Inst Nat Rech Inf Automat | Dispositif et procede pour le stockage rapide et stable d'informations |
EP0254247A3 (de) * | 1984-04-26 | 1988-08-10 | BBC Brown Boveri AG | Einrichtung zur Rettung des Rechnerzustandes |
US4751639A (en) * | 1985-06-24 | 1988-06-14 | Ncr Corporation | Virtual command rollback in a fault tolerant data processing system |
EP0228559A1 (de) * | 1985-12-17 | 1987-07-15 | BBC Brown Boveri AG | Fehlertolerante Mehrrechneranordnung |
US4740969A (en) * | 1986-06-27 | 1988-04-26 | Hewlett-Packard Company | Method and apparatus for recovering from hardware faults |
SE454730B (sv) * | 1986-09-19 | 1988-05-24 | Asea Ab | Forfarande och datorutrustning for stotfri omkoppling av funktionen fran aktiva enheter till beredskapsenheter i en centralenhet |
US4958273A (en) * | 1987-08-26 | 1990-09-18 | International Business Machines Corporation | Multiprocessor system architecture with high availability |
US4965719A (en) * | 1988-02-16 | 1990-10-23 | International Business Machines Corporation | Method for lock management, page coherency, and asynchronous writing of changed pages to shared external store in a distributed computing system |
EP0348628A3 (en) * | 1988-06-28 | 1991-01-02 | International Business Machines Corporation | Cache storage system |
US4924466A (en) * | 1988-06-30 | 1990-05-08 | International Business Machines Corp. | Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system |
US4964126A (en) * | 1988-09-30 | 1990-10-16 | Massachusetts Institute Of Technology | Fault tolerant signal processing machine and method |
US5325517A (en) * | 1989-05-17 | 1994-06-28 | International Business Machines Corporation | Fault tolerant data processing system |
US5247618A (en) * | 1989-06-30 | 1993-09-21 | Digital Equipment Corporation | Transferring data in a digital data processing system |
US5239637A (en) * | 1989-06-30 | 1993-08-24 | Digital Equipment Corporation | Digital data management system for maintaining consistency of data in a shadow set |
US5271013A (en) * | 1990-05-09 | 1993-12-14 | Unisys Corporation | Fault tolerant computer system |
US5327532A (en) * | 1990-05-16 | 1994-07-05 | International Business Machines Corporation | Coordinated sync point management of protected resources |
EP0457308B1 (en) * | 1990-05-18 | 1997-01-22 | Fujitsu Limited | Data processing system having an input/output path disconnecting mechanism and method for controlling the data processing system |
US5157663A (en) * | 1990-09-24 | 1992-10-20 | Novell, Inc. | Fault tolerant computer system |
US5214652A (en) * | 1991-03-26 | 1993-05-25 | International Business Machines Corporation | Alternate processor continuation of task of failed processor |
US5269017A (en) * | 1991-08-29 | 1993-12-07 | International Business Machines Corporation | Type 1, 2 and 3 retry and checkpointing |
US5313647A (en) * | 1991-09-20 | 1994-05-17 | Kendall Square Research Corporation | Digital data processor with improved checkpointing and forking |
US5325519A (en) * | 1991-10-18 | 1994-06-28 | Texas Microsystems, Inc. | Fault tolerant computer with archival rollback capabilities |
WO1993009494A1 (en) * | 1991-10-28 | 1993-05-13 | Digital Equipment Corporation | Fault-tolerant computer processing using a shadow virtual processor |
US5488719A (en) * | 1991-12-30 | 1996-01-30 | Xerox Corporation | System for categorizing character strings using acceptability and category information contained in ending substrings |
US5408649A (en) * | 1993-04-30 | 1995-04-18 | Quotron Systems, Inc. | Distributed data access system including a plurality of database access processors with one-for-N redundancy |
US5504861A (en) * | 1994-02-22 | 1996-04-02 | International Business Machines Corporation | Remote data duplexing |
JPH10506483A (ja) * | 1994-06-10 | 1998-06-23 | テキサス・マイクロ・インコーポレーテッド | フォールト・トレラントなコンピュータ・システムのためのメイン・メモリ・システム及びチェックポイント用プロトコル |
-
1995
- 1995-11-29 US US08/564,024 patent/US5745672A/en not_active Expired - Lifetime
-
1996
- 1996-11-27 WO PCT/US1996/018949 patent/WO1997022045A2/en active IP Right Grant
- 1996-11-27 JP JP52206097A patent/JP2001515615A/ja not_active Withdrawn
- 1996-11-27 DE DE69614003T patent/DE69614003T2/de not_active Expired - Fee Related
- 1996-11-27 EP EP96941494A patent/EP0900420B1/en not_active Expired - Lifetime
- 1996-11-27 AT AT96941494T patent/ATE203338T1/de not_active IP Right Cessation
-
2006
- 2006-12-20 JP JP2006343089A patent/JP4073464B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2007128540A (ja) | 2007-05-24 |
DE69614003D1 (de) | 2001-08-23 |
EP0900420A2 (en) | 1999-03-10 |
WO1997022045A2 (en) | 1997-06-19 |
WO1997022045A3 (en) | 1997-08-21 |
US5745672A (en) | 1998-04-28 |
ATE203338T1 (de) | 2001-08-15 |
DE69614003T2 (de) | 2002-03-21 |
EP0900420B1 (en) | 2001-07-18 |
JP2001515615A (ja) | 2001-09-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4073464B2 (ja) | リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル | |
US5751939A (en) | Main memory system and checkpointing protocol for fault-tolerant computer system using an exclusive-or memory | |
US5958070A (en) | Remote checkpoint memory system and protocol for fault-tolerant computer system | |
US5864657A (en) | Main memory system and checkpointing protocol for fault-tolerant computer system | |
US7840768B2 (en) | Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support | |
US6622263B1 (en) | Method and apparatus for achieving system-directed checkpointing without specialized hardware assistance | |
EP0764302B1 (en) | Main memory system and checkpointing protocol for fault-tolerant computer system | |
TWI236620B (en) | On-die mechanism for high-reliability processor | |
US10776267B2 (en) | Mirrored byte addressable storage | |
US20060150010A1 (en) | Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support | |
EP0889409B1 (en) | Mirrored write-back cache module warmswap | |
JPS638835A (ja) | 障害回復方法 | |
Zhou et al. | Fast cluster failover using virtual memory-mapped communication | |
US6675316B1 (en) | Method and system for recovery of the state of a failed CPU/cache/memory node in a distributed shared memory system | |
JP3030658B2 (ja) | 電源故障対策を備えたコンピュータシステム及びその動作方法 | |
Fiala et al. | Mini-ckpts: Surviving os failures in persistent memory | |
JPH10326220A (ja) | ファイルシステムおよびファイル管理方法 | |
Masubuchi et al. | Fault recovery mechanism for multiprocessor servers | |
Rosenblum et al. | Implementing efficient fault containment for multiprocessors: confining faults in a shared-memory multiprocessor environment | |
JPH0981464A (ja) | 計算機システムのメモリ障害回復方法および回復システム | |
USRE45632E1 (en) | Memory-controller-embedded apparatus and procedure for achieving system-directed checkpointing without operating-system kernel support | |
JP2000501216A (ja) | リード・バッファを用いたフォールト・トレラント・コンピュータ・システム用主メモリ・システムおよびチェックポインティング・プロトコル | |
JPH10240620A (ja) | コンピュータシステムおよび同システムにおけるチェックポイントイメージ保存方法 | |
JPH05108388A (ja) | プロセス復旧方式 | |
JP4494263B2 (ja) | サービスシステムの冗長化方式 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20070213 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070410 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070622 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20070921 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20070927 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071205 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20071226 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20080122 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110201 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |