JP4069721B2 - Abnormality detection device for battery pack - Google Patents

Abnormality detection device for battery pack Download PDF

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Publication number
JP4069721B2
JP4069721B2 JP2002298817A JP2002298817A JP4069721B2 JP 4069721 B2 JP4069721 B2 JP 4069721B2 JP 2002298817 A JP2002298817 A JP 2002298817A JP 2002298817 A JP2002298817 A JP 2002298817A JP 4069721 B2 JP4069721 B2 JP 4069721B2
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Prior art keywords
assembled battery
internal resistance
battery
threshold value
overcharge
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JP2004134287A (en
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哲也 新国
豊昭 中川
誠 岩島
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Nissan Motor Co Ltd
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Nissan Motor Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/396Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • G01R31/389Measuring internal impedance, internal conductance or related variables

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electric Status Of Batteries (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は組電池の異常状態を検出する装置に関する。
【0002】
【従来の技術】
複数の単電池(以下、セルと呼ぶ)が直列に接続された組電池において、セル電圧が過放電しきい値以下になった場合にそのセルが過放電状態にあると判定し、セル電圧が過充電しきい値以上になった場合にそのセルが過充電状態にあると判定する組電池の異常検出装置が知られている(例えば、特許文献1参照)。
【0003】
この出願の発明に関連する先行技術文献としては次のものがある。
【特許文献1】
特開平05−258778号公報(第2−3頁、図1)
【0004】
【発明が解決しようとする課題】
しかしながら、従来の組電池の異常検出装置では、過放電しきい値と過充電しきい値をそれぞれ固定値としているので、セルの内部抵抗が増大するとセル電圧の変化が急峻になり、セル電圧がしきい値を超えて異常状態を検出してから充放電を禁止したのでは制御が間に合わなくなるおそれがある。
【0005】
本発明は、組電池の異常を早期に確実に検出するようにした組電池の異常検出装置を提供するものである。
【0006】
【課題を解決するための手段】
本発明は、組電池の内部抵抗を推定し、内部抵抗推定値が大きいほど過充電しきい値を低くし、内部抵抗推定値が大きいほど過放電しきい値を高くする
【0007】
【発明の効果】
本発明によれば、組電池の異常を早期に確実に検出することができる。
【0008】
【発明の実施の形態】
セル(単電池)をn個直列に接続した組電池に対して本願発明を適用した一実施の形態を説明する。なお、本願発明は、セルを複数個直列に接続した組電池に限定されず、複数のセルを並列に接続したセル並列回路を複数組直列に接続した組電池に対しても適用することができる。
【0009】
また、本願発明は、電池の温度が低くなるほど電池内部の化学反応が緩やかになって電池の内部抵抗が増大する種類のすべての電池に対して適用することができる。
【0010】
《発明の第1の実施の形態》
図1は第1の実施の形態の構成を示す。組電池1はn個のセル11,12,13,・・,1nが直列に接続されている。この組電池1の各セル11〜1nの両端C0-C1、C1-C2、C2-C3、・・、Cn-1-Cnには、電流バイパス回路21〜2n、過充電検出回路31〜3nおよび過放電検出回路41〜4nがそれぞれ並列に接続される。
【0011】
電流バイパス回路21〜2nは、セル両端の電圧が所定の電圧を超えたときに、それまでセルに流れていた充電電流をバイパスし、セルの充電を停止する回路である。この電流バイパス回路21〜2nには、抵抗器とツェナーダイオードとを直列に接続した回路や、抵抗器とトランジスターとを直列にした回路など、種々の回路を用いることができる。
【0012】
図2は、過充電検出回路31〜3nと過放電検出回路41〜4nの詳細を示す。なお、これらの回路は各セル11〜1nに対してすべて共通である。過充電検出回路31〜3nは、コンパレーターC1、インバーターIV1、トランジスター(FET)Q1および抵抗器R1〜R3から構成される。まず、しきい値切り換え信号SIGがローレベルの状態でトランジスターQ1がオフしている場合を考えると、コンパレーターC1は、制御電源電圧Vccを抵抗器R1と抵抗器(R2+R3)とで分圧したしきい値電圧Vc1とセル電圧Vcとを比較する。
【数1】
Vc1=(R2+R3)/(R1+R2+R3)・Vcc
セル電圧Vcがしきい値Vc1を超えるとコンパレーターC1の出力がローレベルになり、インバーターIN1でハイレベルに反転されて過充電検出信号としてOR素子51〜5nへ出力される。
【0013】
次に、しきい値切り換え信号SIGがハイレベルに変化してトランジスターQ1がオンし、抵抗器R3の両端が短絡されると、コンパレーターC1は、制御電源電圧Vccを抵抗器R1とR2とで分圧したしきい値電圧Vc2とセル電圧Vcとを比較する。
【数2】
Vc2=R2/(R1+R2)・Vcc
セル電圧Vcがしきい値Vc2を超えるとコンパレーターC1の出力がローレベルになり、インバーターIN1でハイレベルに反転されて過充電検出信号としてOR素子51〜5nへ出力される。
【0014】
このように、しきい値切り換え信号SIGにより過充電検出用しきい値をVc1とVc2の間で切り換えることができる。しきい値切り換え信号SIGがローレベルのときは過充電検出用しきい値Vc1が選択され、しきい値切り換え信号SIGがハイレベルのときは過充電検出用しきい値Vc2が選択される。ここで、上述したように過充電しきい値Vc2はしきい値Vc1より低い。
【数3】
Vc2<Vc1
したがって、ローレベルのしきい値切り換え信号SIGで高い過充電しきい値Vc1が選択され、ハイレベルのしきい値切り換え信号SIGで低い過充電しきい値Vc2が選択される。
【0015】
過放電検出回路41〜4nは、コンパレーターC2、インバーターIV2、トランジスター(FET)Q2および抵抗器R4〜R6から構成される。まず、しきい値切り換え信号SIGがローレベルの状態でトランジスターQ2がオフしている場合を考えると、コンパレーターC2は、制御電源電圧Vccを抵抗器(R4+R5)と抵抗器R6とで分圧したしきい値電圧Vd1とセル電圧Vcとを比較する。
【数4】
Vd1=R6/(R4+R5+R6)・Vcc
セル電圧Vcがしきい値Vd1より低くなるとコンパレーターC2の出力がハイレベルに反転し、過放電検出信号としてOR素子51〜5nへ出力される。
【0016】
次に、しきい値切り換え信号SIGがハイレベルに変化すると、インバーターIV2の出力がローレベルになってトランジスターQ2がオンし、抵抗器R4の両端が短絡される。コンパレーターC2は、制御電源電圧Vccを抵抗器R5と抵抗器R6とで分圧したしきい値Vd2とセル電圧Vcとを比較する。
【数5】
Vd2=R6/(R5+R6)・Vcc
セル電圧Vcがしきい値Vd2より低くなるとコンパレーターC2の出力がハイレベルに反転し、過放電検出信号としてOR素子51〜5nへ出力される。
【0017】
このように、しきい値切り換え信号SIGにより過放電検出用しきい値をVd1とVd2の間で切り換えることができる。しきい値切り換え信号SIGがローレベルのときは過放電検出用しきい値Vd1が選択され、しきい値切り換え信号SIGがハイレベルのときは過放電検出用しきい値Vd2が選択される。ここで、上述したように過放電しきい値Vd2はしきい値Vd1より高い。
【数6】
Vd2>Vd1
したがって、ローレベルのしきい値切り換え信号SIGで低い過放電しきい値Vc1が選択され、ハイレベルのしきい値切り換え信号SIGで高い過放電しきい値Vc2が選択される。
【0018】
図1に戻って説明を続けると、OR素子51〜5nは、いずれかのセル11〜1nの過充電検出信号または過放電検出信号を入力し、OR素子6へ出力する。充放電制御回路7は、OR素子6からいずれかのセル11〜1nの過充電検出信号が入力されると組電池1の充電を停止し、OR素子6からいずれかのセル11〜1nの過放電検出信号が入力される組電池1の放電を停止する。
【0019】
充放電制御回路7は、しきい値切り換え信号SIGにより過充電検出回路31〜3nのしきい値Vc1とVc2を切り換えるとともに、過放電検出回路41〜4nのしきい値Vd1とVd2を切り換える。ローレベルのしきい値切り換え信号SIGで過充電検出しきい値Vc1と過放電検出しきい値Vd1を選択し、ハイレベルのしきい値切り換え信号SIGで過充電検出しきい値Vc2と過放電検出しきい値Vd2を選択する。
【0020】
図3は、組電池の内部抵抗が小さい場合の充電時の電圧変化と、内部抵抗が大きい場合の充電時の電圧変化を示す。一般に、電池は温度が低くなるにしたがって電池内部の化学反応が緩やかになるため、電池の内部抵抗が大きくなる。電池の温度が高い状態で充電を行う場合には、図3に示す内部抵抗小の特性曲線にしたがって電池電圧(セル電圧)Vcが上昇する。電池電圧Vcが過充電しきい値Vc1に達すると、過充電検出回路31〜3nから過充電検出信号が充放電制御回路7へ出力される。充放電制御回路7は、過充電検出信号を受信すると直ちに充電停止処理を実行する。
【0021】
ここで、電池電圧Vcが過充電しきい値Vc1に達してから実際に充電が停止されるまでには、「制御遅れ時間」が存在する。そのため、図3に示すように、電池電圧Vcが過充電しきい値Vc1に達した後も、制御遅れ時間の間、そのまま電池電圧Vcが上昇を続けることになる。しかし、電池温度が高い状態で充電を行った場合は電池電圧Vcが緩やかに上昇するから、制御遅れ時間の間、電池電圧Vcが上昇し続けても充電停止制御が実行される前に電池電圧Vcが電池劣化開始電圧に達することはない。
【0022】
一方、電池温度が低い状態で充電を行った場合は、電池の内部抵抗が大きいから電池電圧Vcの変化が急峻になり、図3に示す内部抵抗大の特性曲線にしたがって電池電圧Vcが上昇する。電池電圧Vcが過充電しきい値Vc1に達すると、過充電検出回路31〜3nから過充電検出信号が充放電制御回路7へ出力され、充放電制御回路7が直ちに充電停止処理を実行する。ところが、電池温度が低い状態で充電を行った場合は電池電圧Vcが急激に上昇するから、制御遅れ時間の間、電池電圧Vcが上昇し続けて、充電停止制御が実行される前に電池劣化開始電圧に達してしまう。つまり、充電停止制御が間に合わず、電池の劣化が生じることになる。
【0023】
そこで、この第1の実施の形態では、組電池1の内部抵抗の増大を推定し、内部抵抗の増大が推定された場合には過充電しきい値Vc1を低いしきい値Vc2に切り換える。これにより、内部抵抗の増大により充電時に電池電圧Vcが急激に上昇しても、過充電しきい値Vc1よりも低いしきい値Vc2を超えた時点で過充電検出回路31〜3nから過充電検出信号が出力され、充放電制御回路7により充電停止制御が実行される。その結果、制御遅れ時間の間、電池電圧Vcが上昇し続けても、充電停止制御が実行される前に電池電圧Vcが電池劣化開始電圧に達することはなく、過充電による電池の劣化を避けることができる。
【0024】
ここで、内部抵抗増大時の過充電しきい値Vc2には、組電池1の通常の使用条件下で予想される最大の内部抵抗発生時に、制御遅れ時間後の電池電圧Vcが電池劣化開始電圧を超えない値を設定する。
【0025】
図4は、組電池の内部抵抗が小さい場合の放電時の電圧変化と、内部抵抗が大きい場合の放電時の電圧変化を示す。上述したように、一般に、電池は温度が低くなるにしたがって電池内部の化学反応が緩やかになるため、電池の内部抵抗が大きくなる。電池の温度が高い状態で放電を行う場合には、図4に示す内部抵抗小の特性曲線にしたがって電池電圧(セル電圧)Vcが低下する。電池電圧Vcが過放電しきい値Vd1に達すると、過放電検出回路41〜4nから過放電検出信号が充放電制御回路7へ出力される。充放電制御回路7は、過放電検出信号を受信すると直ちに放電停止処理を実行する。
【0026】
ここで、電池電圧Vcが過放電しきい値Vd1に達してから実際に放電が停止されるまでには、「制御遅れ時間」が存在する。そのため、図4に示すように、電池電圧Vcが過放電しきい値Vd1に達した後も、制御遅れ時間の間、そのまま電池電圧Vcが低下を続けることになる。しかし、電池温度が高い状態で充電を行った場合は電池電圧Vcが緩やかに低下するから、制御遅れ時間の間、電池電圧Vcが低下し続けても放電停止制御が実行される前に電池電圧Vcが電池劣化開始電圧に達することはない。
【0027】
一方、電池温度が低い状態で放電を行った場合は、電池の内部抵抗が大きいから電池電圧Vcの変化が急峻になり、図4に示す内部抵抗大の特性曲線にしたがって電池電圧Vcが低下する。電池電圧Vcが過放電しきい値Vd1に達すると、過放電検出回路41〜4nから過放電検出信号が充放電制御回路7へ出力され、充放電制御回路7が直ちに放電停止処理を実行する。ところが、電池温度が低い状態で放電を行った場合は電池電圧Vcが急激に低下するから、制御遅れ時間の間、電池電圧Vcが低下し続けて、放電停止制御が実行される前に電池劣化開始電圧に達してしまう。つまり、放電停止制御が間に合わず、電池の劣化が生じることになる。
【0028】
そこで、この第1の実施の形態では、組電池1の内部抵抗の増大を推定し、内部抵抗の増大が推定された場合には過放電しきい値Vd1を高いしきい値Vd2へ切り換える。これにより、内部抵抗の増大により放電時に電池電圧Vcが急激に低下しても、過放電しきい値Vd1よりも高いしきい値Vd2を下回った時点で過放電検出回路41〜4nから過放電検出信号が出力され、充放電制御回路7により直ちに放電停止制御が実行される。その結果、制御遅れ時間の間、電池電圧Vcが低下し続けても、放電停止制御が実行される前に電池電圧Vcが電池劣化開始電圧を下回ることがなく、過放電による電池の劣化を避けることができる。
【0029】
ここで、内部抵抗増大時の過放電しきい値Vd2には、組電池1の通常の使用条件下で予想される最大の内部抵抗発生時に、制御遅れ時間後の電池電圧Vcが電池劣化開始電圧を下回らない値を設定する。
【0030】
次に、この第1の実施の形態の組電池1の内部抵抗の推定方法について説明する。組電池1の充電中に、組電池1の充電容量が目標充電容量に達する前にいずれかのセル11〜1nで過充電状態が検出された場合には、過充電状態が検出されたセルの電圧Vcの変化が他のセルの電圧変化よりも急峻であり、そのセルの内部抵抗は他のセルよりも大きいと推定される。したがって、このような場合には、しきい値切り換え信号SIGをハイレベルにして高い過充電しきい値Vc1を低いしきい値Vc2に切り換える。
【0031】
このように第1の実施の形態では、組電池1の充電中に、組電池1の充電容量が目標充電容量に達する前にいずれかのセル11〜1nで過充電状態が検出された場合は、組電池1のいずれかのセルの内部抵抗が大きくなっていると推定し、この推定により過充電しきい値を高い値Vc1から低い値Vc2へ変更するようにした。これにより、次回の過充放電検出サイクルでは低い過充電しきい値Vc2が用いられることになり、特に前回の検出サイクルで過充電状態が検出されたセルの電圧Vcが電池劣化開始電圧に達してセルの劣化が生じるのを避けることができ、組電池の異常を早期に確実に検出することができる。
【0032】
また、組電池1の放電中に、組電池1の放電容量が目標放電容量に達する前にいずれかのセル11〜1nで過放電状態が検出された場合には、過放電状態が検出されたセルの電圧Vcの変化が他のセルの電圧変化よりも急峻であり、そのセルの内部抵抗は他のセルよりも大きいと推定される。したがって、このような場合には、しきい値切り換え信号SIGをハイレベルにして低い過放電しきい値Vd1を高いしきい値Vd2に切り換える。
【0033】
このように第1の実施の形態では、組電池1の放電中に、組電池1の放電容量が目標放電容量に達する前にいずれかのセル11〜1nで過放電状態が検出された場合は、組電池1のいずれかのセルの内部抵抗が大きくなっていると推定し、この推定により過放電しきい値を低い値Vd1から高い値Vd2へ変更するようにした。これにより、次回の過充放電検出サイクルでは高い過放電しきい値Vd2が用いられることになり、特に前回の検出サイクルで過放電状態が検出されたセルの電圧Vcが電池劣化開始電圧に達してセルの劣化が生じるのを避けることができ、組電池の異常を早期に確実に検出することができる。
【0034】
上述した第1の実施の形態では、組電池1の充放電中に、組電池1の充放電容量が目標充放電容量に達する前にいずれかのセル11〜1nで過充電状態または過放電状態が検出された場合には、過充電状態または過放電状態が検出されたセルの内部抵抗は他のセルよりも大きいと推定する例を示したが、内部抵抗の推定方法はこの第1の実施の形態に限定されない。例えば、充放電時の組電池に流れる電流とセルの電圧をサンプリングし、サンプリング結果の電流と電圧を二次元平面上で直線回帰し、この回帰直線の傾きから電池の内部抵抗を推定する方法などを利用することができる。
【0035】
《発明の第2の実施の形態》
上述した第1の実施の形態では、充放電制御回路7により組電池1の内部抵抗を推定する例を示したが、内部抵抗推定手段にハードウエアデバイスを用いる第2の実施の形態を説明する。
【0036】
図5は第2の実施の形態の構成を示す。なお、図1に示す第1の実施の形態の構成と同様な機器に対しては同一の符号を付して相違点を中心に説明する。温度センサー8は組電池1の温度を検出し、組電池1の温度が予め設定したしきい値以下に低下したらハイレベルのしきい値切り換え信号SIGを過充電検出回路31〜3nと過放電検出回路41〜4nへ出力する。
【0037】
上述したように、一般に電池は温度が低くなるにしたがって電池内部の化学反応が緩やかになるため、電池の内部抵抗が大きくなる。そこで、この第2の実施の形態では、組電池1の温度がしきい値以下に低下したら組電池1の内部抵抗が増大したと判断し、しきい値切り換え信号SIGをハイレベルに切り換える。これにより、過充電しきい値が高い値Vc1から低い値Vc2へ切り換わるとともに、過放電しきい値が低い値Vd1から高い値Vd2へ切り換わる。
【0038】
このように、組電池1の温度がしきい値以下に低下したら過充電しきい値を高い値Vc1から低い値Vc2へ切り換えるとともに、過放電しきい値を低い値Vd1から高い値Vd2へ切り換えるようにした。つまり、第2の実施の形態では組電池1の温度を検出し、温度検出値に基づいて組電池1の内部抵抗を推定し、内部抵抗推定値に応じて過充電しきい値と過放電しきい値を変更するようにした。これにより、組電池1の異常を早期に確実に検出することができ、組電池1の温度低下時に内部抵抗が増大して充放電時の電圧変化が急峻になっても、セル電圧Vcが電池劣化開始電圧に達してセルの劣化が生じるのを避けることができる。
【0039】
なお、組電池温度のしきい値と過充放電しきい値Vc2、Vd2には、組電池1の通常の使用条件下で予想される最低温度のときに、上述した制御遅れ時間後の電池電圧Vcが電池劣化開始電圧に達しない値を設定する。
【0040】
《発明の第3の実施の形態》
内部抵抗推定手段に他のハードウエアデバイスを用いる第3の実施の形態を説明する。図6は第3の実施の形態の構成を示す。なお、図1に示す第1の実施の形態の構成と同様な機器に対しては同一の符号を付して相違点を中心に説明する。充放電時間積算回路9は組電池1の充放電時間を積算し、組電池1の充放電時間の積算値が予め設定したしきい値に達したらハイレベルのしきい値切り換え信号SIGを過充電検出回路31〜3nと過放電検出回路41〜4nへ出力する。
【0041】
一般に、電池は劣化が進むにつれて内部抵抗が増大し、電圧変化が急峻になる。そこで、この第3の実施の形態では、組電池1の充放電時間の積算値がしきい値に達したら組電池1の内部抵抗が増大したと判断し、しきい値切り換え信号SIGをハイレベルに切り換える。これにより、過充電しきい値が高い値Vc1から低い値Vc2へ切り換わるとともに、過放電しきい値が低い値Vd1から高い値Vd2へ切り換わる。
【0042】
このように、組電池1の充放電時間の積算値がしきい値に達したら過充電しきい値を高い値Vc1から低い値Vc2へ切り換えるとともに、過放電しきい値を低い値Vd1から高い値Vd2へ切り換えるようにした。つまり、第3の実施の形態では組電池1の充放電時間を積算し、この充放電時間積算値に基づいて組電池1の内部抵抗を推定し、内部抵抗推定値に応じて過充電しきい値と過放電しきい値を変更するようにした。これにより、組電池1の異常を早期に確実に検出することができ、組電池1の長い間の使用により組電池1が徐々に劣化して内部抵抗が増大し、充放電時の電圧変化が急峻になっても、セル電圧Vcが電池劣化開始電圧に達してセルの劣化が生じるのを避けることができる。
【0043】
なお、組電池充放電時間積算値のしきい値と過充放電しきい値Vc2、Vd2には、通常の使用条件下で使用したときに、上述した制御遅れ時間後の電池電圧Vcが電池劣化開始電圧に達しない値を設定する。
【0044】
《発明の第4の実施の形態》
内部抵抗推定手段に他のハードウエアデバイスを用いる第4の実施の形態を説明する。図7は第4の実施の形態の構成を示す。なお、図1に示す第1の実施の形態の構成と同様な機器に対しては同一の符号を付して相違点を中心に説明する。タイマー回路10は、組電池1の電源投入時点からの稼動時間を計時し、稼動時間が予め設定した所定時間に達したらハイレベルのしきい値切り換え信号SIGを過充電検出回路31〜3nと過放電検出回路41〜4nへ出力する。
【0045】
一般に、電池は、電源投入時点、つまり稼動開始時点では温度が低く、稼動時間が長くなるにしたがって温度が上昇する。つまり、電源投入直後は温度が低いので内部抵抗が高く、電圧変化が急峻になる。そこで、この第4の実施の形態では、電源投入時点から所定の稼動時間の間は組電池1の内部抵抗が高いと判断し、その間はしきい値切り換え信号SIGをハイレベルにする。これにより、電源投入時点から所定の稼動時間の間は、過充電しきい値が高い値Vc1から低い値Vc2へ切り換わるとともに、過放電しきい値が低い値Vd1から高い値Vd2へ切り換わる。
【0046】
このように、組電池1の電源投入時点から所定の稼動時間の間は、過充電しきい値を高い値Vc1から低い値Vc2へ切り換えるとともに、過放電しきい値を低い値Vd1から高い値Vd2へ切り換えるようにした。つまり、この第4の実施の形態では組電池1の電源投入時点からの稼動時間を計時し、組電池1の電源投入からの稼動時間に基づいて組電池1の内部抵抗を推定し、内部抵抗推定値に応じて過充電しきい値と過放電しきい値を変更するようにした。これにより、組電池1の異常を早期に確実に検出することができ、電源投入直後の組電池1の内部抵抗が高くて電圧変化が急峻になっても、セル電圧Vcが電池劣化開始電圧に達してセルの劣化が生じるのを避けることができる。
【0047】
なお、上記所定の稼動時間と過充放電しきい値Vc2、Vd2には、通常の使用条件下で使用したときに、上述した制御遅れ時間後の電池電圧Vcが電池劣化開始電圧に達しない値を設定する。
【0048】
特許請求の範囲の構成要素と一実施の形態の構成要素との対応関係は次の通りである。すなわち、過充電検出回路31〜3nが過充電検出手段を、過放電検出回路41〜4nが過放電検出手段を、過充電検出回路31〜3nおよび過放電検出回路41〜4nが過充放電検出手段を、充放電制御回路7、温度センサー8、充放電時間積算回路9、タイマー回路10がそれぞれ内部抵抗推定手段およびしきい値変更手段をそれぞれ構成する。なお、本発明の特徴的な機能を損なわない限り、各構成要素は上記構成に限定されるものではない。
【0049】
なお、上述した一実施の形態では、組電池の充放電中に目標充放電容量に達する前に過充電検出信号または過放電検出信号が出力されたときは、組電池のいずれかのセルの内部抵抗が大きくなっていると推定する例、または組電池の温度、充放電時間積算値および電源投入時点からの稼動時間に基づいて組電池の内部抵抗を推定する例を示したが、組電池の内部抵抗を推定する方法は上述した一実施の形態の方法に限定されるものではない。
【0050】
また、上述した一実施の形態では、内部抵抗推定値に応じて過充電しきい値および過放電しきい値をそれぞれ2段階に変更する例を示したが、過充電しきい値および過放電しきい値の変更段数は2段階に限定されず、3段階以上としてもよい。あるいは、内部抵抗推定値に応じて過充電しきい値および過放電しきい値を連続的に変更してもよい。
【0051】
上述した一実施の形態では組電池1の内部抵抗推定値に応じて過充電しきい値と過放電しきい値とを同時に変更する例を示した。これにより、しきい値切り換え信号SIGを送る信号線を1本化することができ、装置を簡素化することができる。もちろん、過充電しきい値と過放電しきい値とを同時に変更せず、それぞれ別個にしきい値切り換え信号線を設けて別々のタイミングで切り換えるようにしてもよい。
【0052】
さらに、上述した第2から第4の実施の形態では、組電池1の内部抵抗推定手段にそれぞれ温度センサー8、充放電時間積算回路9およびタイマー回路10のハードウエアデバイスを用いる例を示した。このようなハードウエアデバイスにより内部抵抗推定手段を構成することによって、過充電検出回路31〜3nおよび過放電検出回路41〜4nもハードウエアデバイスであるから、ハードウエアデバイスのみで組電池の異常検出装置を構成することができ、マイクロコンピューターやA/Dコンバーターを用いずに装置を簡素化することができる。
【図面の簡単な説明】
【図1】 第1の実施の形態の構成を示す図である。
【図2】 過充電検出回路と過放電検出回路の詳細を示す図である。
【図3】 組電池の内部抵抗が小さい場合の充電時の電圧変化と、内部抵抗が大きい場合の充電時の電圧変化を示す図である。
【図4】 組電池の内部抵抗が小さい場合の放電時の電圧変化と、内部抵抗が大きい場合の放電時の電圧変化を示す図である。
【図5】 第2の実施の形態の構成を示す図である。
【図6】 第3の実施の形態の構成を示す図である。
【図7】 第4の実施の形態の構成を示す図である。
【符号の説明】
1 組電池
6、51〜5n OR素子
7 充放電制御回路
8 温度センサー
9 充放電時間積算回路
10 タイマー回路
11、12、13、・・、1n セル(単電池)
31〜3n 過充電検出回路
41〜4n 過放電検出回路
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for detecting an abnormal state of a battery pack.
[0002]
[Prior art]
In a battery pack in which a plurality of single cells (hereinafter referred to as cells) are connected in series, when the cell voltage falls below the overdischarge threshold, it is determined that the cell is in an overdischarge state, and the cell voltage is A battery pack abnormality detection apparatus that determines that a cell is in an overcharged state when an overcharge threshold value is reached is known (see, for example, Patent Document 1).
[0003]
Prior art documents related to the invention of this application include the following.
[Patent Document 1]
JP 05-258778 A (page 2-3, FIG. 1)
[0004]
[Problems to be solved by the invention]
However, in the conventional battery pack abnormality detection device, the overdischarge threshold value and the overcharge threshold value are fixed values. Therefore, when the internal resistance of the cell increases, the cell voltage changes sharply, and the cell voltage If charging / discharging is prohibited after detecting an abnormal state exceeding the threshold, the control may not be in time.
[0005]
The present invention provides an assembled battery abnormality detection device that reliably detects an abnormality of an assembled battery at an early stage.
[0006]
[Means for Solving the Problems]
The present invention estimates the internal resistance of the assembled battery and estimates the internal resistance. The larger the value, the lower the overcharge threshold, and the larger the estimated internal resistance, the higher the overdischarge threshold. .
[0007]
【The invention's effect】
According to the present invention, the abnormality of the assembled battery can be reliably detected at an early stage.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment in which the present invention is applied to an assembled battery in which n cells (unit cells) are connected in series will be described. The present invention is not limited to an assembled battery in which a plurality of cells are connected in series, and can also be applied to an assembled battery in which a plurality of cell parallel circuits in which a plurality of cells are connected in parallel are connected in series. .
[0009]
Further, the present invention can be applied to all types of batteries in which the chemical reaction inside the battery becomes milder and the internal resistance of the battery increases as the temperature of the battery decreases.
[0010]
<< First Embodiment of the Invention >>
FIG. 1 shows the configuration of the first embodiment. In the assembled battery 1, n cells 11, 12, 13,..., 1n are connected in series. Both ends C0-C1, C1-C2, C2-C3,..., Cn-1-Cn of each cell 11-1n of the assembled battery 1 include current bypass circuits 21-2n, overcharge detection circuits 31-3n, and Overdischarge detection circuits 41 to 4n are connected in parallel.
[0011]
The current bypass circuits 21 to 2n are circuits that, when the voltage across the cell exceeds a predetermined voltage, bypass the charging current that has been flowing through the cell and stop charging the cell. Various circuits such as a circuit in which a resistor and a Zener diode are connected in series and a circuit in which a resistor and a transistor are connected in series can be used for the current bypass circuits 21 to 2n.
[0012]
FIG. 2 shows details of the overcharge detection circuits 31 to 3n and the overdischarge detection circuits 41 to 4n. These circuits are all common to the cells 11 to 1n. The overcharge detection circuits 31 to 3n include a comparator C1, an inverter IV1, a transistor (FET) Q1, and resistors R1 to R3. First, considering the case where the transistor Q1 is turned off while the threshold switching signal SIG is at a low level, the comparator C1 divides the control power supply voltage Vcc by the resistor R1 and the resistor (R2 + R3). The threshold voltage Vc1 is compared with the cell voltage Vc.
[Expression 1]
Vc1 = (R2 + R3) / (R1 + R2 + R3) · Vcc
When the cell voltage Vc exceeds the threshold value Vc1, the output of the comparator C1 becomes low level, is inverted to high level by the inverter IN1, and is output to the OR elements 51 to 5n as overcharge detection signals.
[0013]
Next, when the threshold value switching signal SIG changes to high level to turn on the transistor Q1, and both ends of the resistor R3 are short-circuited, the comparator C1 sets the control power supply voltage Vcc between the resistors R1 and R2. The divided threshold voltage Vc2 is compared with the cell voltage Vc.
[Expression 2]
Vc2 = R2 / (R1 + R2) · Vcc
When the cell voltage Vc exceeds the threshold value Vc2, the output of the comparator C1 becomes low level, is inverted to high level by the inverter IN1, and is output to the OR elements 51 to 5n as overcharge detection signals.
[0014]
As described above, the threshold for overcharge detection can be switched between Vc1 and Vc2 by the threshold switching signal SIG. When the threshold value switching signal SIG is at a low level, the overcharge detection threshold value Vc1 is selected, and when the threshold value switching signal SIG is at a high level, the overcharge detection threshold value Vc2 is selected. Here, as described above, the overcharge threshold value Vc2 is lower than the threshold value Vc1.
[Equation 3]
Vc2 <Vc1
Therefore, the high overcharge threshold value Vc1 is selected by the low level threshold value switching signal SIG, and the low overcharge threshold value Vc2 is selected by the high level threshold value switching signal SIG.
[0015]
The overdischarge detection circuits 41 to 4n include a comparator C2, an inverter IV2, a transistor (FET) Q2, and resistors R4 to R6. First, considering the case where the transistor Q2 is turned off while the threshold switching signal SIG is at a low level, the comparator C2 divides the control power supply voltage Vcc by the resistor (R4 + R5) and the resistor R6. The threshold voltage Vd1 is compared with the cell voltage Vc.
[Expression 4]
Vd1 = R6 / (R4 + R5 + R6) .Vcc
When the cell voltage Vc becomes lower than the threshold value Vd1, the output of the comparator C2 is inverted to a high level and is output to the OR elements 51 to 5n as an overdischarge detection signal.
[0016]
Next, when the threshold value switching signal SIG changes to high level, the output of the inverter IV2 becomes low level, the transistor Q2 is turned on, and both ends of the resistor R4 are short-circuited. The comparator C2 compares the threshold voltage Vd2 obtained by dividing the control power supply voltage Vcc by the resistors R5 and R6 with the cell voltage Vc.
[Equation 5]
Vd2 = R6 / (R5 + R6) · Vcc
When the cell voltage Vc becomes lower than the threshold value Vd2, the output of the comparator C2 is inverted to a high level and is output to the OR elements 51 to 5n as an overdischarge detection signal.
[0017]
Thus, the overdischarge detection threshold value can be switched between Vd1 and Vd2 by the threshold value switching signal SIG. When the threshold switching signal SIG is at a low level, the overdischarge detection threshold Vd1 is selected, and when the threshold switching signal SIG is at a high level, the overdischarge detection threshold Vd2 is selected. Here, as described above, the overdischarge threshold value Vd2 is higher than the threshold value Vd1.
[Formula 6]
Vd2> Vd1
Therefore, the low overdischarge threshold value Vc1 is selected by the low level threshold value switching signal SIG, and the high overdischarge threshold value Vc2 is selected by the high level threshold value switching signal SIG.
[0018]
Returning to FIG. 1 and continuing the description, the OR elements 51 to 5 n receive the overcharge detection signal or the overdischarge detection signal of any of the cells 11 to 1 n and output it to the OR element 6. The charge / discharge control circuit 7 stops charging the assembled battery 1 when the overcharge detection signal of any of the cells 11 to 1n is input from the OR element 6, and the overcharge detection of any of the cells 11 to 1n from the OR element 6. Discharge of the assembled battery 1 to which the discharge detection signal is input is stopped.
[0019]
The charge / discharge control circuit 7 switches the threshold values Vc1 and Vc2 of the overcharge detection circuits 31 to 3n and the threshold values Vd1 and Vd2 of the overdischarge detection circuits 41 to 4n by the threshold value switching signal SIG. The overcharge detection threshold value Vc1 and the overdischarge detection threshold value Vd1 are selected by the low level threshold value switching signal SIG, and the overcharge detection threshold value Vc2 and the overdischarge detection value are selected by the high level threshold value switching signal SIG. The threshold value Vd2 is selected.
[0020]
FIG. 3 shows voltage changes during charging when the internal resistance of the assembled battery is small, and voltage changes during charging when the internal resistance is large. In general, as the temperature of the battery decreases, the chemical reaction inside the battery becomes gradual, so that the internal resistance of the battery increases. When charging is performed in a state where the battery temperature is high, the battery voltage (cell voltage) Vc increases according to the characteristic curve with a small internal resistance shown in FIG. When the battery voltage Vc reaches the overcharge threshold Vc1, overcharge detection signals are output from the overcharge detection circuits 31 to 3n to the charge / discharge control circuit 7. The charge / discharge control circuit 7 executes the charge stop process immediately after receiving the overcharge detection signal.
[0021]
Here, there is a “control delay time” from when the battery voltage Vc reaches the overcharge threshold value Vc1 until when the charging is actually stopped. Therefore, as shown in FIG. 3, even after the battery voltage Vc reaches the overcharge threshold value Vc1, the battery voltage Vc continues to rise during the control delay time. However, when charging is performed in a state where the battery temperature is high, the battery voltage Vc gradually increases. Therefore, even if the battery voltage Vc continues to increase during the control delay time, the battery voltage before the charge stop control is executed. Vc does not reach the battery deterioration start voltage.
[0022]
On the other hand, when charging is performed in a state where the battery temperature is low, since the internal resistance of the battery is large, the change of the battery voltage Vc becomes steep, and the battery voltage Vc increases according to the characteristic curve of the large internal resistance shown in FIG. . When the battery voltage Vc reaches the overcharge threshold value Vc1, an overcharge detection signal is output from the overcharge detection circuits 31 to 3n to the charge / discharge control circuit 7, and the charge / discharge control circuit 7 immediately executes a charge stop process. However, when charging is performed in a state where the battery temperature is low, the battery voltage Vc rapidly increases. Therefore, the battery voltage Vc continues to increase during the control delay time, and the battery deteriorates before the charge stop control is executed. The starting voltage is reached. That is, the charge stop control is not in time, and the battery is deteriorated.
[0023]
Therefore, in the first embodiment, an increase in the internal resistance of the assembled battery 1 is estimated, and when the increase in the internal resistance is estimated, the overcharge threshold value Vc1 is switched to a low threshold value Vc2. As a result, even if the battery voltage Vc suddenly increases during charging due to an increase in internal resistance, overcharge detection is performed from the overcharge detection circuits 31 to 3n when the threshold value Vc2 lower than the overcharge threshold value Vc1 is exceeded. A signal is output, and the charge / discharge control circuit 7 performs charge stop control. As a result, even if the battery voltage Vc continues to rise during the control delay time, the battery voltage Vc does not reach the battery deterioration start voltage before the charge stop control is executed, and the battery deterioration due to overcharging is avoided. be able to.
[0024]
Here, the overcharge threshold value Vc2 when the internal resistance is increased includes the battery voltage Vc after the control delay time when the maximum internal resistance expected under normal use conditions of the battery pack 1 is generated. Set a value that does not exceed.
[0025]
FIG. 4 shows voltage changes during discharge when the internal resistance of the battery pack is small, and voltage changes during discharge when the internal resistance is large. As described above, generally, as the temperature of the battery decreases, the chemical reaction inside the battery becomes moderate, and the internal resistance of the battery increases. When discharging in a state where the battery temperature is high, the battery voltage (cell voltage) Vc decreases according to the characteristic curve with small internal resistance shown in FIG. When battery voltage Vc reaches overdischarge threshold Vd1, overdischarge detection signals are output from overdischarge detection circuits 41 to 4n to charge / discharge control circuit 7. The charge / discharge control circuit 7 executes the discharge stop process immediately after receiving the overdischarge detection signal.
[0026]
Here, there is a “control delay time” from when the battery voltage Vc reaches the overdischarge threshold Vd1 until when the discharge is actually stopped. Therefore, as shown in FIG. 4, even after the battery voltage Vc reaches the overdischarge threshold Vd1, the battery voltage Vc continues to decrease during the control delay time. However, when charging is performed in a state where the battery temperature is high, the battery voltage Vc gradually decreases. Therefore, even if the battery voltage Vc continues to decrease during the control delay time, the battery voltage before the discharge stop control is executed. Vc does not reach the battery deterioration start voltage.
[0027]
On the other hand, when discharging is performed in a state where the battery temperature is low, since the internal resistance of the battery is large, the change of the battery voltage Vc becomes steep, and the battery voltage Vc decreases according to the characteristic curve of the large internal resistance shown in FIG. . When the battery voltage Vc reaches the overdischarge threshold Vd1, overdischarge detection signals are output from the overdischarge detection circuits 41 to 4n to the charge / discharge control circuit 7, and the charge / discharge control circuit 7 immediately executes a discharge stop process. However, when discharging is performed in a state where the battery temperature is low, the battery voltage Vc rapidly decreases. Therefore, the battery voltage Vc continues to decrease during the control delay time, and the battery deteriorates before the discharge stop control is executed. The starting voltage is reached. That is, the discharge stop control is not in time, and the battery is deteriorated.
[0028]
Therefore, in the first embodiment, an increase in the internal resistance of the assembled battery 1 is estimated, and when the increase in the internal resistance is estimated, the overdischarge threshold value Vd1 is switched to the high threshold value Vd2. As a result, even if the battery voltage Vc suddenly drops during discharge due to an increase in internal resistance, overdischarge detection is performed from the overdischarge detection circuits 41 to 4n when it falls below a threshold value Vd2 higher than the overdischarge threshold value Vd1. A signal is output, and the discharge stop control is immediately executed by the charge / discharge control circuit 7. As a result, even if the battery voltage Vc continues to decrease during the control delay time, the battery voltage Vc does not fall below the battery deterioration start voltage before the discharge stop control is executed, and the battery deterioration due to overdischarge is avoided. be able to.
[0029]
Here, the overdischarge threshold value Vd2 when the internal resistance is increased is the battery deterioration start voltage after the control delay time when the maximum internal resistance expected under normal use conditions of the battery pack 1 is generated. Set a value not lower than.
[0030]
Next, a method for estimating the internal resistance of the assembled battery 1 according to the first embodiment will be described. When the overcharged state is detected in any of the cells 11 to 1n before the charge capacity of the assembled battery 1 reaches the target charge capacity during charging of the assembled battery 1, the cell of the overcharged state is detected. The change in voltage Vc is steeper than the voltage change in other cells, and the internal resistance of the cell is estimated to be larger than that in other cells. Therefore, in such a case, the threshold switching signal SIG is set to the high level to switch the high overcharge threshold Vc1 to the low threshold Vc2.
[0031]
As described above, in the first embodiment, when the assembled battery 1 is being charged, if the overcharged state is detected in any of the cells 11 to 1n before the charging capacity of the assembled battery 1 reaches the target charging capacity. The internal resistance of any cell of the assembled battery 1 is estimated to be large, and the overcharge threshold is changed from the high value Vc1 to the low value Vc2 by this estimation. As a result, the low overcharge threshold Vc2 is used in the next overcharge / discharge detection cycle, and in particular, the voltage Vc of the cell in which the overcharge state is detected in the previous detection cycle reaches the battery deterioration start voltage. It is possible to avoid the deterioration of the cell, and it is possible to reliably detect the abnormality of the assembled battery at an early stage.
[0032]
Moreover, when the overdischarge state is detected in any of the cells 11 to 1n before the discharge capacity of the assembled battery 1 reaches the target discharge capacity during the discharge of the assembled battery 1, the overdischarge state is detected. The change in the voltage Vc of the cell is steeper than the voltage change of the other cells, and the internal resistance of the cell is estimated to be larger than that of the other cells. Therefore, in such a case, the threshold value switching signal SIG is set to the high level to switch the low overdischarge threshold value Vd1 to the high threshold value Vd2.
[0033]
As described above, in the first embodiment, during the discharge of the assembled battery 1, when the overdischarge state is detected in any of the cells 11 to 1n before the discharge capacity of the assembled battery 1 reaches the target discharge capacity. The internal resistance of any cell of the assembled battery 1 is estimated to be large, and the overdischarge threshold is changed from the low value Vd1 to the high value Vd2 by this estimation. As a result, the high overdischarge threshold value Vd2 is used in the next overcharge / discharge detection cycle, and in particular, the voltage Vc of the cell in which the overdischarge state is detected in the previous detection cycle reaches the battery deterioration start voltage. It is possible to avoid the deterioration of the cell, and it is possible to reliably detect the abnormality of the assembled battery at an early stage.
[0034]
In the first embodiment described above, during charging / discharging of the assembled battery 1, before the charging / discharging capacity of the assembled battery 1 reaches the target charging / discharging capacity, any of the cells 11-1n is overcharged or overdischarged. In the example, it is estimated that the internal resistance of a cell in which an overcharged state or an overdischarged state is detected is larger than that of other cells. It is not limited to the form. For example, a method of sampling the current flowing through the assembled battery during charging and discharging and the cell voltage, performing a linear regression on the current and voltage of the sampling result on a two-dimensional plane, and estimating the internal resistance of the battery from the slope of this regression line, etc. Can be used.
[0035]
<< Second Embodiment of the Invention >>
In the first embodiment described above, the example in which the internal resistance of the assembled battery 1 is estimated by the charge / discharge control circuit 7 has been described, but the second embodiment in which a hardware device is used as the internal resistance estimation means will be described. .
[0036]
FIG. 5 shows the configuration of the second embodiment. In addition, the same code | symbol is attached | subjected to the apparatus similar to the structure of 1st Embodiment shown in FIG. 1, and it demonstrates centering around difference. The temperature sensor 8 detects the temperature of the assembled battery 1, and when the temperature of the assembled battery 1 drops below a preset threshold, a high level threshold switching signal SIG is detected with the overcharge detection circuits 31 to 3n and overdischarge detection. Output to circuits 41 to 4n.
[0037]
As described above, generally, as the temperature of the battery decreases, the chemical reaction inside the battery becomes milder, so that the internal resistance of the battery increases. Therefore, in the second embodiment, when the temperature of the assembled battery 1 falls below the threshold value, it is determined that the internal resistance of the assembled battery 1 has increased, and the threshold value switching signal SIG is switched to the high level. As a result, the overcharge threshold value is switched from the high value Vc1 to the low value Vc2, and the overdischarge threshold value is switched from the low value Vd1 to the high value Vd2.
[0038]
As described above, when the temperature of the assembled battery 1 falls below the threshold value, the overcharge threshold value is switched from the high value Vc1 to the low value Vc2, and the overdischarge threshold value is switched from the low value Vd1 to the high value Vd2. I made it. That is, in the second embodiment, the temperature of the assembled battery 1 is detected, the internal resistance of the assembled battery 1 is estimated based on the temperature detection value, and the overcharge threshold and overdischarge are performed according to the estimated internal resistance value. The threshold value was changed. As a result, the abnormality of the assembled battery 1 can be reliably detected at an early stage, and even if the internal resistance increases when the temperature of the assembled battery 1 decreases and the voltage change at the time of charge / discharge becomes steep, the cell voltage Vc is It is possible to avoid the deterioration of the cell due to reaching the deterioration start voltage.
[0039]
The battery temperature threshold value and the overcharge / discharge threshold values Vc2 and Vd2 include the battery voltage after the above-described control delay time at the lowest temperature expected under normal use conditions of the battery pack 1. A value at which Vc does not reach the battery deterioration start voltage is set.
[0040]
<< Third Embodiment of the Invention >>
A third embodiment in which another hardware device is used as the internal resistance estimation means will be described. FIG. 6 shows the configuration of the third embodiment. In addition, the same code | symbol is attached | subjected to the apparatus similar to the structure of 1st Embodiment shown in FIG. 1, and it demonstrates centering around difference. The charging / discharging time integration circuit 9 integrates the charging / discharging time of the assembled battery 1 and overcharges the high-level threshold switching signal SIG when the integrated value of the charging / discharging time of the assembled battery 1 reaches a preset threshold value. It outputs to the detection circuits 31 to 3n and the overdischarge detection circuits 41 to 4n.
[0041]
In general, as the battery deteriorates, the internal resistance increases and the voltage change becomes steep. Therefore, in the third embodiment, when the integrated value of the charge / discharge time of the assembled battery 1 reaches the threshold value, it is determined that the internal resistance of the assembled battery 1 has increased, and the threshold value switching signal SIG is set to the high level. Switch to. As a result, the overcharge threshold value is switched from the high value Vc1 to the low value Vc2, and the overdischarge threshold value is switched from the low value Vd1 to the high value Vd2.
[0042]
As described above, when the integrated value of the charge / discharge time of the assembled battery 1 reaches the threshold value, the overcharge threshold value is switched from the high value Vc1 to the low value Vc2, and the overdischarge threshold value is changed from the low value Vd1 to the high value. Switching to Vd2. That is, in the third embodiment, the charging / discharging time of the assembled battery 1 is integrated, the internal resistance of the assembled battery 1 is estimated based on this charging / discharging time integrated value, and the overcharge threshold is determined according to the estimated internal resistance value. The value and overdischarge threshold were changed. Thereby, the abnormality of the assembled battery 1 can be reliably detected at an early stage, and the assembled battery 1 is gradually deteriorated due to long-term use of the assembled battery 1 to increase the internal resistance. Even if it becomes steep, it can be avoided that the cell voltage Vc reaches the battery deterioration start voltage and the cell is deteriorated.
[0043]
It should be noted that the battery voltage Vc after the control delay time described above is used for the battery pack charge / discharge time integrated value threshold value and the overcharge / discharge threshold value Vc2, Vd2 when the battery is used under normal use conditions. Set a value that does not reach the start voltage.
[0044]
<< Fourth Embodiment of the Invention >>
A fourth embodiment in which another hardware device is used as the internal resistance estimation means will be described. FIG. 7 shows the configuration of the fourth embodiment. In addition, the same code | symbol is attached | subjected to the apparatus similar to the structure of 1st Embodiment shown in FIG. 1, and it demonstrates centering around difference. The timer circuit 10 counts the operating time from the time when the battery pack 1 is turned on, and when the operating time reaches a predetermined time set in advance, a high-level threshold switching signal SIG is sent to the overcharge detection circuits 31 to 3n. It outputs to the discharge detection circuits 41-4n.
[0045]
In general, the temperature of a battery is low at the time of power-on, that is, at the start of operation, and the temperature rises as the operation time increases. That is, immediately after the power is turned on, the temperature is low, so the internal resistance is high, and the voltage change becomes steep. Therefore, in the fourth embodiment, it is determined that the internal resistance of the assembled battery 1 is high during a predetermined operation time from the time of power-on, and the threshold value switching signal SIG is set to a high level during that period. As a result, the overcharge threshold value is switched from the high value Vc1 to the low value Vc2 and the overdischarge threshold value is switched from the low value Vd1 to the high value Vd2 during a predetermined operation time from the time when the power is turned on.
[0046]
As described above, during the predetermined operation time from the time when the battery pack 1 is turned on, the overcharge threshold value is switched from the high value Vc1 to the low value Vc2, and the overdischarge threshold value is changed from the low value Vd1 to the high value Vd2. Switched to. That is, in the fourth embodiment, the operation time from the time when the battery pack 1 is turned on is counted, and the internal resistance of the battery pack 1 is estimated based on the operation time after the battery pack 1 is turned on. The overcharge threshold and overdischarge threshold were changed according to the estimated value. As a result, the abnormality of the assembled battery 1 can be reliably detected at an early stage, and even if the internal resistance of the assembled battery 1 immediately after power-on is high and the voltage change becomes steep, the cell voltage Vc becomes the battery deterioration start voltage. And cell degradation can be avoided.
[0047]
The predetermined operating time and overcharge / discharge threshold values Vc2 and Vd2 are values at which the battery voltage Vc after the control delay time described above does not reach the battery deterioration start voltage when used under normal use conditions. Set.
[0048]
The correspondence between the constituent elements of the claims and the constituent elements of the embodiment is as follows. That is, the overcharge detection circuits 31 to 3n are overcharge detection means, the overdischarge detection circuits 41 to 4n are overdischarge detection means, the overcharge detection circuits 31 to 3n and the overdischarge detection circuits 41 to 4n are overcharge detection. The charging / discharging control circuit 7, the temperature sensor 8, the charging / discharging time integrating circuit 9, and the timer circuit 10 constitute an internal resistance estimating means and a threshold changing means, respectively. In addition, as long as the characteristic function of this invention is not impaired, each component is not limited to the said structure.
[0049]
In the above-described embodiment, when the overcharge detection signal or the overdischarge detection signal is output before the target charge / discharge capacity is reached during the charge / discharge of the assembled battery, the inside of any cell of the assembled battery An example of estimating that the resistance has increased, or an example of estimating the internal resistance of the assembled battery based on the temperature of the assembled battery, the accumulated charge / discharge time, and the operation time from the time of power-on was shown. The method for estimating the internal resistance is not limited to the method of the above-described embodiment.
[0050]
In the above-described embodiment, an example in which the overcharge threshold value and the overdischarge threshold value are changed in two stages according to the estimated internal resistance value is shown. The number of threshold change stages is not limited to two, and may be three or more. Or you may change an overcharge threshold value and an overdischarge threshold value continuously according to an internal resistance estimated value.
[0051]
In the above-described embodiment, an example in which the overcharge threshold value and the overdischarge threshold value are simultaneously changed according to the estimated internal resistance value of the assembled battery 1 has been described. Thereby, the signal line which sends threshold switching signal SIG can be unified, and a device can be simplified. Of course, the overcharge threshold value and the overdischarge threshold value may not be changed at the same time, and a threshold value switching signal line may be provided separately for switching at different timings.
[0052]
Furthermore, in the second to fourth embodiments described above, examples in which the hardware devices of the temperature sensor 8, the charge / discharge time integration circuit 9, and the timer circuit 10 are used as the internal resistance estimation means of the assembled battery 1 are shown. By configuring the internal resistance estimation means with such a hardware device, the overcharge detection circuits 31 to 3n and the overdischarge detection circuits 41 to 4n are also hardware devices. The apparatus can be configured, and the apparatus can be simplified without using a microcomputer or an A / D converter.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a first exemplary embodiment.
FIG. 2 is a diagram showing details of an overcharge detection circuit and an overdischarge detection circuit.
FIG. 3 is a diagram illustrating a voltage change during charging when the internal resistance of the assembled battery is small and a voltage change during charging when the internal resistance is large.
FIG. 4 is a diagram showing a voltage change during discharging when the internal resistance of the assembled battery is small and a voltage change during discharging when the internal resistance is large.
FIG. 5 is a diagram showing a configuration of a second exemplary embodiment.
FIG. 6 is a diagram showing a configuration of a third exemplary embodiment.
FIG. 7 is a diagram showing a configuration of a fourth exemplary embodiment.
[Explanation of symbols]
1 battery pack
6,51-5n OR element
7 Charge / discharge control circuit
8 Temperature sensor
9 Charge / discharge time integration circuit
10 Timer circuit
11, 12, 13, ... 1n cell (single cell)
31-3n Overcharge detection circuit
41 to 4n overdischarge detection circuit

Claims (8)

単電池(以下、セルという)を複数個直列に接続した組電池、または複数のセルを並列に接続したセル並列回路を複数組直列に接続した組電池の過充電状態を検出する組電池の異常検出装置であって、
前記セルまたは前記セル並列回路の両端電圧が過充電しきい値を超えたときに過充電検出信号を出力する過充電検出手段と、
前記組電池の内部抵抗を推定する内部抵抗推定手段と、
前記組電池の内部抵抗推定値が大きいほど前記過充電しきい値を低くする過充電しきい値変更手段とを備えることを特徴とする組電池の異常検出装置。
Abnormal battery pack that detects the overcharge status of battery packs that are connected in series with multiple single cells (hereinafter referred to as cells), or battery packs that are connected in parallel with multiple cell parallel circuits with multiple cells connected in parallel A detection device,
Overcharge detection means for outputting an overcharge detection signal when a voltage across the cell or the cell parallel circuit exceeds an overcharge threshold;
Internal resistance estimating means for estimating the internal resistance of the assembled battery;
An overcharge threshold value changing means for lowering the overcharge threshold value as the estimated internal resistance value of the assembled battery becomes larger .
単電池(以下、セルという)を複数個直列に接続した組電池、または複数のセルを並列に接続したセル並列回路を複数組直列に接続した組電池の過放電状態を検出する組電池の異常検出装置であって、
前記セルまたは前記セル並列回路の両端電圧が過放電しきい値を下回ったときに過放電検出信号を出力する過放電検出手段と、
前記組電池の内部抵抗を推定する内部抵抗推定手段と、
前記組電池の内部抵抗推定値が大きいほど前記過放電しきい値を高くする過放電しきい値変更手段とを備えることを特徴とする組電池の異常検出装置。
Abnormality of a battery pack that detects an overdischarge status of a battery pack in which a plurality of single cells (hereinafter referred to as cells) are connected in series, or a battery pack in which a plurality of cells connected in parallel are connected in series. A detection device,
Overdischarge detection means for outputting an overdischarge detection signal when a voltage across the cell or the cell parallel circuit falls below an overdischarge threshold;
Internal resistance estimating means for estimating the internal resistance of the assembled battery;
An assembled battery abnormality detection device comprising: overdischarge threshold value changing means for increasing the overdischarge threshold value as the estimated internal resistance value of the assembled battery increases .
単電池(以下、セルという)を複数個直列に接続した組電池、または複数のセルを並列に接続したセル並列回路を複数組直列に接続した組電池の過充電状態または過放電状態を検出する組電池の異常検出装置であって、
前記セルまたは前記セル並列回路の両端電圧が過充電しきい値を超えたときに過充電検出信号を出力し、前記セルまたは前記セル並列回路の両端電圧が過放電しきい値を下回ったときに過放電検出信号を出力する過充放電検出手段と、
前記組電池の内部抵抗を推定する内部抵抗推定手段と、
前記組電池の内部抵抗推定値が大きいほど前記過充電しきい値を低くし、前記過放電しきい値を高くする過充放電しきい値変更手段とを備えることを特徴とする組電池の異常検出装置。
Detects an overcharged state or an overdischarged state of an assembled battery in which a plurality of single cells (hereinafter referred to as cells) are connected in series, or an assembled battery in which a plurality of cell parallel circuits in which a plurality of cells are connected in parallel are connected in series. An assembled battery abnormality detection device,
When the voltage across the cell or the cell parallel circuit exceeds an overcharge threshold, an overcharge detection signal is output, and when the voltage across the cell or the cell parallel circuit falls below the overdischarge threshold Overcharge / discharge detection means for outputting an overdischarge detection signal;
Internal resistance estimating means for estimating the internal resistance of the assembled battery;
An abnormality of the assembled battery , comprising: an overcharge / discharge threshold value changing means for lowering the overcharge threshold value and increasing the overdischarge threshold value as the estimated internal resistance of the assembled battery increases. Detection device.
請求項3に記載の組電池の異常検出装置において、
前記過充放電しきい値変更手段は、前記組電池の内部抵抗推定値に応じて前記過充電しきい値と前記過放電しきい値とを同時に変更することを特徴とする組電池の異常検出装置。
In the assembled battery abnormality detection device according to claim 3,
The overcharge / discharge threshold value changing means simultaneously changes the overcharge threshold value and the overdischarge threshold value according to an estimated internal resistance value of the assembled battery, and detects an abnormality in the assembled battery. apparatus.
請求項1〜4のいずれかの項に記載の組電池の異常検出装置において、
前記内部抵抗推定手段は、前記組電池の充放電中に目標充放電容量に達する前に前記過充電検出信号または前記過放電検出信号が出力されたときは、前記組電池のいずれかのセルまたはセル並列回路の内部抵抗が大きくなっていると推定することを特徴とする組電池の異常検出装置。
In the abnormality detection apparatus of the assembled battery as described in any one of Claims 1-4,
When the overcharge detection signal or the overdischarge detection signal is output before reaching the target charge / discharge capacity during charging / discharging of the assembled battery, the internal resistance estimating means outputs any cell of the assembled battery or An assembled battery abnormality detection device characterized by estimating that the internal resistance of a cell parallel circuit is increased .
請求項1〜4のいずれかの項に記載の組電池の異常検出装置において、
前記組電池の温度を検出する電池温度検出手段を備え、
前記内部抵抗推定手段は、前記組電池の温度検出値がしきい値以下に低下したら前記組電池の内部抵抗が増大したと推定することを特徴とする組電池の異常検出装置。
In the abnormality detection apparatus of the assembled battery as described in any one of Claims 1-4,
Battery temperature detecting means for detecting the temperature of the assembled battery;
The assembled battery abnormality detecting device, wherein the internal resistance estimating means estimates that the internal resistance of the assembled battery has increased when a temperature detection value of the assembled battery falls below a threshold value .
請求項1〜4のいずれかの項に記載の組電池の異常検出装置において、
前記組電池の充放電時間を積算する充放電時間積算手段を備え、
前記内部抵抗推定手段は、前記組電池の充放電時間積算値がしきい値に達したら前記組 電池の内部抵抗が増大したと推定することを特徴とする組電池の異常検出装置。
In the abnormality detection apparatus of the assembled battery as described in any one of Claims 1-4,
Charge / discharge time integration means for integrating the charge / discharge time of the assembled battery,
The assembled battery abnormality detecting device, wherein the internal resistance estimating means estimates that the internal resistance of the assembled battery has increased when the integrated charge / discharge time of the assembled battery reaches a threshold value .
請求項1〜4のいずれかの項に記載の組電池の異常検出装置において、
前記組電池の電源投入時点からの稼動時間を計時する稼動時間計時手段を備え、
前記内部抵抗推定手段は、前記組電池の電源投入時点からの稼動時間が所定の稼働時間になるまでの間は前記組電池の内部抵抗が高いと推定することを特徴とする組電池の異常検出装置。
In the abnormality detection apparatus of the assembled battery as described in any one of Claims 1-4,
An operation time measuring means for measuring the operation time from the time of turning on the battery pack,
The internal resistance estimating means estimates that the internal resistance of the assembled battery is high until the operation time from the time when the battery is turned on reaches a predetermined operation time. apparatus.
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JP2009055755A (en) 2007-08-29 2009-03-12 Ricoh Co Ltd Semiconductor device for protecting secondary battery
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JP5321392B2 (en) * 2009-09-29 2013-10-23 株式会社デンソー Voltage monitoring device
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