JP3733953B2 - Abnormality detection device for battery pack - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an apparatus for detecting an abnormality in a battery pack composed of a plurality of cells.
[0002]
[Prior art]
A device that has a detection terminal connected to each of both terminals of a cell constituting an assembled battery and detects overcharge or overdischarge of the cell based on a voltage between the both detection terminals is known (Patent Document) 1). Such a device may have a function of performing a failure diagnosis of the device itself for detecting cell overcharge or overdischarge.
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-157367 [0004]
[Problems to be solved by the invention]
However, the conventional device requires a trigger signal line for inputting a trigger for switching the abnormality detection device to the diagnosis mode in order to diagnose whether or not the device itself that detects the abnormality of the cell has failed. Therefore, when a signal line for outputting a cell abnormality detection result is taken into account, there is a problem that it is impossible to unify the signal lines.
[0005]
The present invention provides an assembled battery abnormality detection device that outputs a detection result by an abnormality detection means for detecting an abnormality of a cell and a diagnosis result by a failure diagnosis means for diagnosing a failure of the abnormality detection means using a single signal line. provide.
[0006]
[Means for Solving the Problems]
The battery pack abnormality detection apparatus according to the present invention includes abnormality detection means for detecting an abnormality of each cell and failure diagnosis means for diagnosing a failure of the abnormality detection means. The abnormality detection means outputs a first signal when it is determined that all the cells are normal, and outputs a second signal different from the first signal when detecting an abnormality of at least one cell, The failure diagnosis means outputs a second signal when diagnosing that the abnormality detection means is normal, and outputs a first signal when a failure of the abnormality detection means is detected. The signal output from the abnormality detection means and the signal output from the failure diagnosis means are time-divided and output alternately by a single signal line.
[0007]
【The invention's effect】
According to the battery pack abnormality detection device of the present invention, it is possible to output the cell abnormality detection result and the failure diagnosis result of the abnormality detection means for detecting the cell abnormality through a single signal line.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a configuration of an embodiment of an assembled battery abnormality detection device according to the present invention. The battery pack abnormality detection device 100 in one embodiment includes overcharge detection circuits a1 to an, overdischarge detection circuits b1 to bn, OR circuits 2, c1 to cn, AND circuits 3, d1 to dn, Switches 4, e 1 to en, a clock circuit 10, a signal transmission photocoupler 20 (hereinafter simply referred to as a photocoupler 20), and an NPN transistor 30. The photocoupler 20 includes a light emitting diode 21 and a phototransistor 30.
[0009]
The assembled battery 1 is configured by connecting n cells s1 to sn that can be charged and discharged in series. Overcharge detection circuits a1 to an, overdischarge detection circuits b1 to bn, OR circuits c1 to cn, AND circuits d1 to dn, and switches e1 to en are provided for each cell.
[0010]
The overcharge detection circuits a1 to an detect that the terminal voltages of the corresponding cells s1 to sn are higher than the first predetermined voltage and are overcharged. Moreover, the overcharge detection circuits a1 to an have a self-diagnosis function for diagnosing whether or not the overcharge detection function has failed. Switching between the overcharge detection function and the self-diagnosis function is performed based on a clock signal input from the clock circuit 10. In this embodiment, when the input clock signal is at the Hi level, the overcharge detection circuit itself performs self-diagnosis. In this case, the overcharge detection circuits a1 to an output a Hi level signal if the self-diagnosis result is normal, and output a Low level signal if the result is abnormal. It should be noted that the state where the signal is at the Hi level is a state where a current flows, and the state where the signal is at a Low level is a state where no current flows.
[0011]
On the other hand, when the clock signal input from the clock circuit 10 is at the low level, the overcharge detection of the corresponding cells s1 to sn is performed. In this case, when the overcharge detection circuits a1 to an determine that the corresponding cells s1 to sn are normal rather than the overcharge state, the overcharge detection circuits a1 to an output a low level signal. Is output.
[0012]
The overdischarge detection circuits b1 to bn detect that the terminal voltages of the corresponding cells s1 to sn have fallen from the second predetermined voltage to cause overdischarge. Further, the overdischarge detection circuits b1 to bn have a self-diagnosis function for diagnosing whether or not the overdischarge detection function has failed. Switching between the overdischarge detection function and the self-diagnosis function is performed based on a clock signal input from the clock circuit 10. In this embodiment, the self-diagnosis of the overdischarge detection circuit itself is performed when the input clock signal is at the Hi level. In this case, the overdischarge detection circuits b1 to bn output a Hi level signal if the self-diagnosis result is normal, and output a Low level signal if the result is abnormal.
[0013]
On the other hand, when the clock signal input from the clock circuit 10 is at the low level, the overdischarge detection of the corresponding cells s1 to sn is performed. In this case, the overdischarge detection circuits b1 to bn output a low level signal when it is determined that the corresponding cells s1 to sn are normal rather than the overdischarge state, and a high level signal when it is determined that the cells are in the overdischarge state. Is output. The detection results of the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn are input to the OR circuits d1 to dn and the AND circuits e1 to en.
[0014]
The switches e1 to en switch between outputs from the OR circuits c1 to cn and outputs from the AND circuits d1 to dn. The output is switched based on a clock signal input from the clock circuit 10. When performing self-diagnosis of the overcharge detection circuits a1 to an and overdischarge detection circuits b1 to bn, that is, when the clock signal is at the Hi level, the outputs from the AND circuits d1 to dn are selected. On the other hand, when the overcharge detection of the cells by the overcharge detection circuits a1 to an and the overdischarge detection of the cells by the overdischarge detection circuits b1 to bn are performed, that is, when the clock signal is at the low level, the OR circuits c1 to cn. The output from is selected. The output selected by switching the switches e1 to en is input to the OR circuit 2 and the AND circuit 3.
[0015]
One of the logical sum operation results performed by the OR circuit 2 and the logical product operation results performed by the AND circuit 3 is selected by the switch 4 and output. The output is switched based on a clock signal input from the clock circuit 10. That is, when the clock signal is at Hi level, the output from the AND circuit 3 is selected, and when the clock signal is at Low level, the output from the OR circuit 2 is selected.
[0016]
The operation described above will be summarized. When the clock signal is at the Hi level, all the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn perform failure diagnosis of their own detection circuits. The self-diagnosis results of the overcharge detection circuits a1 to an and the self-diagnosis results of the overdischarge detection circuits b1 to bn are obtained by performing AND operation on the AND circuits d1 to dn and then inputting the operation results to the AND circuit 3. An AND operation is performed. When the self-diagnosis result is normal, the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn output Hi level signals, so the self diagnosis results of all the detection circuits a1 to an and b1 to bn Is normal, the output of the AND circuit 3 becomes Hi level. On the other hand, when the self-diagnosis result of at least one of the detection circuits a1 to an and b1 to bn indicates abnormality, the output of the AND circuit 3 is at a low level.
[0017]
When the clock signal is at a low level, the overcharge detection circuits a1 to an detect overcharge of the corresponding cells s1 to sn, and the overdischarge detection circuits b1 to bn detect overdischarge of the corresponding cells s1 to sn. Do. The results of overcharge detection and overdischarge detection are subjected to OR operation in the OR circuits c1 to cn, and then the operation result is input to the OR circuit 2 to perform OR operation. When the cells s1 to sn are normal, a low level signal is output from the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn. If it is not in a discharging state, the output of the OR circuit 2 is at a low level. On the other hand, if at least one of the cells s1 to sn is in an overcharged state or an overdischarged state, the output of the OR circuit 2 becomes Hi level. FIG. 2 shows a diagram in which the signal levels output via the switch 4 are summarized based on the level of the clock signal, the states of the cells s1 to sn, and the self-diagnosis result.
[0018]
The output of the OR circuit 2 or the output of the AND circuit 3 selected by the switch 4 is input to the base terminal of the NPN transistor 30. The emitter terminal of the NPN transistor 30 is connected to the negative terminal of the assembled battery 1, and the collector terminal is connected to the positive terminal of the assembled battery 1 via the light emitting diode 21 of the photocoupler 20. Thereby, the NPN transistor 30 is turned on when the signal input to the base terminal is at the Hi level and turned off when the signal is at the Low level.
[0019]
When the NPN transistor 30 is turned on, a current flows through the light emitting diode 21, so that the phototransistor 22 of the photocoupler 20 is turned on. The collector terminal of the phototransistor 22 is connected to the power source of the voltage Vdd via the resistor R0, and the emitter terminal is grounded. Therefore, when the phototransistor 22 is turned on, the collector-emitter voltage Vt of the phototransistor 22 becomes equal to the ground potential. On the other hand, when the transistor 30 is off, the phototransistor 22 is also off, so the collector-emitter voltage Vt of the phototransistor 22 is equal to the voltage Vdd. Note that the resistance value of the resistor R0 is sufficiently smaller than the resistance value of the primary side of the photocoupler, that is, the secondary side (the phototransistor 22) when the light emitting diode 21 is not energized.
[0020]
The battery pack abnormality detection apparatus 100 according to one embodiment detects abnormalities (overcharge state or overdischarge state) of cells s1 to sn and overcharge by detecting the collector-emitter voltage Vt of the phototransistor 22. Abnormalities of the detection circuits a1 to an and the overdischarge detection circuits b1 to bn themselves are detected. This principle will be described with reference to FIGS.
[0021]
FIG. 3A shows the level change (time change) of the clock signal output from the clock circuit 10. FIG. 3B is a diagram showing changes in the output voltage Vt when the cells s1 to sn and the detection circuits a1 to an and b1 to bn are all normal, and the level change of the clock signal shown in FIG. It corresponds to. As described above, when the clock signal is at the Hi level (circuit self-diagnosis), the output of the AND circuit 3 is at the Hi level, so that the transistor 30 and the phototransistor 22 are turned on, so that the output voltage Vt is 0 ( Ground level). When the clock signal is at the low level (cell abnormality detection), the output of the OR circuit 2 is at the low level, so that the transistor 30 and the phototransistor 22 are turned off and the output voltage Vt is Vdd.
[0022]
FIG. 3C shows a change in the output voltage Vt when the detection circuits a1 to an and b1 to bn are all normal, but any of the cells s1 to sn is in an overcharged state or an overdischarged state. It is. The change in the output voltage Vt shown in FIG. 3C also corresponds to the change in the level of the clock signal shown in FIG. When the clock signal is at Hi level, that is, when the self-diagnosis of the detection circuits a1 to an and b1 to bn is performed, the output voltage Vt is at the same Low level as in FIG. When the clock signal is at a low level, if any of the cells s1 to sn is in an overcharged state or an overdischarged state, the output signal from the OR circuit 2 is at a high level, so that the transistor 30 and the phototransistor 22 are turned on. . Therefore, the output voltage Vt is 0 (ground level). That is, as shown in FIG. 3C, the output voltage Vt is at a low level regardless of the level of the clock signal.
[0023]
FIG. 3D is a diagram illustrating a change in the output voltage Vt when all the cells s1 to sn are normal but a failure has occurred in any of the detection circuits a1 to an and b1 to bn. . The change in the output voltage Vt shown in FIG. 3D also corresponds to the change in the level of the clock signal shown in FIG. When the clock signal is at the low level, that is, when the abnormality detection of the cells s1 to sn is performed, the output voltage Vt is at the same Hi level as in FIG. When any one of the detection circuits a1 to an and b1 to bn determines that there is an abnormality as a result of self-diagnosis when the clock signal is at the Hi level, the signal output from the AND circuit 3 is at the Low level. 20 and the phototransistor 22 are both turned off, and the output voltage Vt becomes Vdd. That is, as shown in FIG. 3D, the output voltage Vt becomes the Hi level regardless of the level of the clock signal.
[0024]
FIG. 3 (e) shows an output voltage when one of the cells s1 to sn is in an overcharged state or an overdischarged state, and a failure has occurred in any one of the detection circuits a1 to an and b1 to bn. It is a figure which shows the change of Vt. The change in the output voltage Vt shown in FIG. 3 (e) also corresponds to the level change in the clock signal shown in FIG. 3 (a). In this case, the cells s1 to sn and the detection circuits a1 to an and b1 to bn shown in FIG. 3B exhibit characteristics opposite to the characteristics of the output voltage Vt. That is, when the clock signal is at the Hi level, any one of the detection circuits a1 to an, b1 to bn determines that there is an abnormality as a result of self-diagnosis, and the signal output from the AND circuit 3 is at the Low level. Therefore, both the transistor 20 and the phototransistor 22 are turned off, and the output voltage Vt becomes Vdd (Hi level). When the clock signal is at the low level, any of the cells s1 to sn is in an overcharged state or an overdischarged state, so that the output signal from the OR circuit 2 is at the high level. Both are turned on, and the output voltage Vt becomes 0 (Low level).
[0025]
In the assembled battery abnormality detection device 100 according to the embodiment, the length of the period in which the clock signal is at the Hi level and the period in which the clock signal is at the Low level are changed. Thereby, it is possible to discriminate using the integration circuit without using the decoder for analyzing the four signal patterns shown in FIGS. 3 (a) to 3 (e). In this embodiment, since the period when the clock signal is at the Hi level is shorter than the period when the clock signal is at the Low level, the value obtained by integrating the current flowing through the phototransistor 22 is as shown in FIGS. 3 (d), 3 (b), and 3 (E) and becomes smaller in the order of FIG. That is, four signal patterns can be identified by using an integration circuit that integrates the current flowing through the phototransistor 22 without detecting the magnitude of the output voltage Vt according to the level of the clock signal. Therefore, the charge / discharge which receives the signal output from the abnormality detection apparatus 100 of the assembled battery in one embodiment and determines the presence / absence of the abnormality of the cells s1 to sn and the abnormality of the detection circuits a1 to an and b1 to bn itself. The circuit configuration of the control circuit (not shown) can be simplified.
[0026]
Further, since the period when the clock signal is at the Hi level is made shorter than the period when the clock signal is at the Low level, the current consumption flowing through the abnormality detection device can be reduced. That is, when the cells s1 to sn and the detection circuits a1 to an and b1 to bn are all normal, the light emitting diode 21 is turned on during the self-diagnosis of the detection circuits a1 to an and b1 to bn, that is, the clock. This is when the signal is at the Hi level. Therefore, the current consumed by the entire apparatus can be reduced by making the period during which the clock signal is at the Hi level shorter than the period during which the clock signal is at the Low level.
[0027]
According to the assembled battery abnormality detection device 100 in one embodiment, the abnormality (overcharge state or overdischarge state) detection signal of the cells s1 to sn and the detection circuits a1 to an and b1 to bn for detecting the abnormality of the cells. It is possible to output its own fault diagnosis signal through a single signal line. Specifically, the signal level indicating that all the cells are normal and the signal level indicating that all the detection circuits are normal are set to different levels, and both signals are set to one signal line. Since the cells s1 to sn and the detection circuits a1 to an and b1 to bn are both normal, the output signal is pulsed and output by one signal line. Can do. That is, the abnormality detection signals of the cells s1 to sn and the failure diagnosis signals of the detection circuits a1 to an and b1 to bn that detect the abnormality of the cells are time-divided and output alternately with one signal line. Both signals can be output efficiently, and a cell abnormality and a failure of the cell abnormality detection circuit itself can be detected with a simple configuration.
[0028]
The clock circuit 10 provided in the battery pack abnormality detection device 100 according to the embodiment outputs a signal indicating the abnormality detection result of the cell and a signal indicating the failure diagnosis result of the detection circuits a1 to an and b1 to bn. Since time division is performed based on the clock signal (internal clock) to be performed, an external signal line (trigger signal line) for switching the output signal becomes unnecessary.
[0029]
In addition, since the length of the output period of the signal indicating the abnormality detection result of the cell and the length of the output period of the signal indicating the failure diagnosis result are changed, both the cells s1 to sn and the detection circuits a1 to an and b1 to bn It is also possible to detect that an abnormality has occurred. That is, the change in the output voltage Vt when abnormality occurs in both the cells s1 to sn and the detection circuits a1 to an and b1 to bn is between Hi level and Low level as shown in FIG. Since the states appear alternately, it is difficult to distinguish the output voltage Vt from the normal signal level (FIG. 3A) where the Hi level and the Low level alternately appear. However, in the assembled battery abnormality detection device 100 according to the embodiment, the length of the period for detecting the abnormality of the cell and the length of the period for performing the failure diagnosis of the detection circuits a1 to an and b1 to bn are changed. It can also be easily detected that an abnormality has occurred in both the cells s1 to sn and the detection circuits a1 to an and b1 to bn.
[0030]
In the battery pack abnormality detection apparatus 100 according to the embodiment, when both the cells s1 to sn and the detection circuits a1 to an and b1 to bn are normal, the cell abnormality is detected and the detection circuit is failed. Since the amount of current consumed in the abnormality detection apparatus 100 is different, the signal output period when the current consumption increases is shorter than the signal output period when the current consumption is smaller. Thereby, the electric current consumed by the whole abnormality detection apparatus can be reduced.
[0031]
The present invention is not limited to the embodiment described above. For example, failure detection of the detection circuits a1 to an and b1 to bn is performed when the clock signal is at the Hi level, and abnormality detection of the cells s1 to sn is performed when the clock signal is at the Low level. The Hi / Low of the clock signal is The reverse is also possible. In addition, the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn are all provided with their own circuit fault diagnosis function. However, the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn are separately provided. A failure diagnosis circuit for performing the failure diagnosis may be provided.
[0032]
Moreover, in order to detect the overcharge state and the overdischarge state of the cells s1 to sn, the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn are provided. The state may be detected using one abnormality detection circuit. In this case, the abnormality detection circuit may prepare a voltage determination threshold value used when detecting the overcharge state of the cell and a voltage determination threshold value used when detecting the overdischarge state.
[0033]
The correspondence between the constituent elements of the claims and the constituent elements of the embodiment is as follows. That is, the overcharge detection circuits a1 to an and the overdischarge detection circuits b1 to bn constitute an abnormality detection unit and a failure diagnosis unit, respectively. In addition, as long as the characteristic function of this invention is not impaired, each component is not limited to the said structure.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of an assembled battery abnormality detection device according to the present invention. FIG. 2 shows a signal level output via a switch 4 as a clock signal level, a cell state, and a self-diagnosis result. FIG. 3A is a diagram showing the state of the clock signal, and FIGS. 3B to 3E are diagrams showing changes in the output voltage Vt. DESCRIPTION OF SYMBOLS
DESCRIPTION OF SYMBOLS 1 ... Battery assembly, 2 ... OR circuit, 3 ... AND circuit, 4 ... Switch, 10 ... Clock circuit, 20 ... Photocoupler, 21 ... Light emitting diode, 22 ... Phototransistor, 30 ... NPN transistor, s1-sn ... cell, a1-an: overcharge detection circuit, b1-bn: overdischarge detection circuit, c1-cn: OR circuit, d1-dn: AND circuit, e1-en: switch

Claims (4)

In the battery pack abnormality detection device composed of a plurality of rechargeable cells,
An anomaly detecting means for detecting an anomaly in each cell;
A failure diagnosis means for diagnosing a failure of the abnormality detection means,
The abnormality detection means outputs a first signal when it is determined that all cells are normal, and outputs a second signal different from the first signal when an abnormality of at least one cell is detected. And
The failure diagnosis means outputs the second signal when diagnosing that the abnormality detection means is normal, and outputs the first signal when a failure of the abnormality detection means is detected,
An assembled battery abnormality detection device, wherein a signal output from the abnormality detection means and a signal output from the failure diagnosis means are alternately output in a time-sharing manner using a single signal line. In the assembled battery abnormality detection device according to claim 1,
An assembled battery abnormality detection device, wherein the signal output from the abnormality detection means and the signal output from the failure diagnosis means are time-divided based on an internal clock. In the assembled battery abnormality detection device according to claim 1 or 2,
An abnormality detection device for an assembled battery, wherein an output period of a signal output from the abnormality detection unit and an output period of a signal output from the failure diagnosis unit have different lengths. In the assembled battery abnormality detection device according to any one of claims 1 to 3,
The second signal is output when the first signal is output when all the cells are determined to be normal by the abnormality detection means, and when the abnormality detection means is determined to be normal by the failure diagnosis means . When the current consumption in the assembled battery abnormality detection device is different from when the signal is output, the signal output period with the larger current consumption is made shorter than the signal output period with the smaller current consumption. A battery pack abnormality detection device.

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