JP4066570B2 - EPROM with error correction function and failure diagnosis method and apparatus thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an EPROM having a 3-bit majority voting type error correction function, and in particular, an EPROM suitable for diagnosing a failure of a 3-bit voting circuit used for error correction in the EPROM, a failure diagnosis method, and Relates to the device.
[0002]
[Prior art]
In general, in EPROM, bit data is not written from a logical value indicating a data writing state during use due to variations in data retention time of each memory cell (EPROM cell) or the influence of noise. An erase error (a phenomenon called bit loss or charge loss) that changes to a logical value indicating the state may occur. In addition, although the probability of occurrence is low compared to the erasure error, an erroneous write error occurs in which the bit data changes from a logical value indicating the data non-written state to a logical value indicating the data written state. Sometimes.
[0003]
For this reason, an EPROM with an error correction function of the 3-bit majority method as shown in FIG. 3 has been proposed.
That is, as shown in FIG. 3, the 3-bit majority method EPROM with error correction function includes three EPROM cells M1, M2, and M3 for storing the same 1-bit data. On the data input lines to the EPROM cells M1 to M3, there are provided latch circuits L1, L2, and L3 made of D flip-flops, for example, and the same 1-bit data is supplied to the latch circuits L1 to L3. By latching, 1-bit data having the same logical value can be simultaneously stored in the EPROM cells M1 to M3 via the latch circuits L1 to L3.
[0004]
Outputs (1-bit data) DM1, DM2, and DM3 from the EPROM cells M1 to M3 are input to the 3-bit majority circuit T through the selectors S1, S2, and S3, respectively, and are input to the 3-bit majority circuit T. By taking the majority of these outputs DM1 to DM3, 1-bit data having the same logical value as two or more of the outputs DM1 to DM3 from the respective EPROM cells M1 to M3 is output from the 3-bit majority circuit T. Have been to.
[0005]
In other words, in the conventional 3-bit majority method EPROM with an error correction function, when data is written to the EPROM with the read / write signal R / W at the write level, the same data is written to the three EEPROM cells M1 to M3. When writing 1-bit data and reading data from the EPROM with the read / write signal R / W set to the read level, the 3-bit majority circuit T determines the majority of the outputs DM1 to DM3 from the three EPROM cells M1 to M3. By adopting the above, even when an erasure error or an erroneous write error occurs in one of the three EPROM cells M1 to M3, normal data can be read through the 3-bit majority circuit T. It is.
[0006]
In this example, the 3-bit majority circuit T receives outputs D1 and D3 from the selectors S1 and S3, outputs D1 and D2 from the selectors S1 and S2, and outputs D2 and D3 from the selectors S2 and S3. Three 2-input NOR gates NOR1, NOR2, NOR3 received respectively, and one 3-input NOR gate NOR0 receiving the outputs from the 2-input NOR gates NOR1-NOR3 are provided, and each EPROM cell M1-M3 is provided from the 3-input NOR gate NOR0. 1-bit data having the same logical value as that of two or more of outputs DM1 to DM3.
[0007]
Therefore, for example, the logical value of 1-bit data held in each of the three EPROM cells M1 to M3 is changed from the normal value “1,1,1” to “O, 1,1”, “1,0”. , 1 ”,“ 1, 1, 0 ”, no two-input NOR gates NOR1 to NOR3 have both two inputs“ 0 ”. All the inputs are kept at “0”, and the output DATA from the 3-input NOR gate NOR0 becomes normal 1-bit data DATA (“1”).
[0008]
Conversely, the logical value of the 1-bit data held in the three EPROM cells M1 to M3 is changed from the normal value “0, 0, 0” to “1, 0, 0”, “0, 1, Even if it becomes either “0” or “0, 0, 1”, there are still two input NOR gates NOR1 to NOR3 in which both two inputs are “0”. Since “1” is output to the 3-input NOR gate NOR0, the output DATA from the 3-input NOR gate NOR0 is normal 1-bit data (“0”).
[0009]
Therefore, according to the conventional EPROM with error correction function shown in FIG. 3, if two of the three EPROM cells M1 to M3 are normal, the correct 1-bit data is output from the 3-bit majority circuit T. Will be able to.
In the conventional EPROM with error correction function shown in FIG. 3, 1-bit data to be written to each of the EPROM cells M1 to M3 corresponds to each of the EPROM cells M1 to M3 when writing data to each of the EPROM cells M1 to M3. Are latched by the three latch circuits L1 to L3, and at the time of data reading, the outputs DM1 to DM3 from the EPROM cells M1 to M3 are respectively sent to the 3-bit majority circuit T via the selectors S1 to S3. This is to make it possible to diagnose a failure of the 3-bit majority circuit T at the time of shipment of the EPROM.
[0010]
That is, in the conventional EPROM with error correction function, even if an erase error or an erroneous write error occurs in one of the three EPROM cells M1 to M3, the remaining two are normal. 1-bit data can be output, but this is the case where the 3-bit majority circuit T operates normally. If a failure such as disconnection or short-circuit occurs in the 3-bit majority circuit T, Even if normal 1-bit data is output from the 3-bit majority circuit T immediately after the data is written, an erase error or an erroneous write error occurs in one of the three EPROM cells M1 to M3. Then, normal 1-bit data may not be output.
[0011]
Therefore, conventionally, by providing three latch circuits L1 to L3 and three selectors S1 to S3 corresponding to the EPROM cells M1 to M3, respectively, the selectors S1 to S3 are used for the 3-bit majority circuit T. Switching between whether to input the outputs DM1 to DM3 from the EPROM cells M1 to M3 or to input the outputs DL1 to DL3 from the latch circuits L1 to L3 corresponding to the EPROM cells M1 to M3. When the selectors S1 to S3 select the outputs DL1 to DL3 from the latch circuits L1 to L3, the outputs DL1 to DL3 from the latch circuits L1 to L3 can be arbitrarily switched from the outside. Then, the three data D1 to D3 input to the 3-bit majority circuit T are individually set to desired values (“1” or “0”), and the 3-bit With each other to be able to verify the operation of the majority circuit T.
[0012]
In other words, the 3-bit majority circuit T has two data values, even if one data value is different from the remaining two data values among the three one-bit data inputted from the outside. Since it is necessary to be able to output the same data value, conventionally, by configuring the EPROM with error correction function as described above, the failure of the 3-bit majority circuit T can be detected by the following procedures (1) to (3). The diagnosis is made possible.
[0013]
(1) From the normal selection state in which the selectors S1 to S3 select the outputs DM1 to DM3 of the EPROM cells M1 to M3 and input them to the 3-bit majority decision circuit T, the outputs DL1 to DL1 from the latch circuits L1 to L3 DL3 is selected and switched to the selected state at the time of failure diagnosis input to the 3-bit majority circuit T.
[0014]
(2) “1, 1, 1”, “O, 1, 1”, “1, 0, 1”, “3, 1 bit data lines” to the latch circuits L1 to L3, By inputting each data DIN of “1, 1, 0” in order, each of the data DIN is sequentially latched by the latch circuits L1 to L3. At that time, all the output DATA from the 3-bit majority circuit T are “1”. Thus, the failure diagnosis of the 3-bit majority circuit T when the write data to the EPROM is “1” is performed.
[0015]
(3) “0, 0, 0”, “1, 0, 0”, “0, 1, 0”, “0, 0, 1” data is input to the data input lines to the latch circuits L1 to L3. By sequentially inputting DIN, each of the data DIN is sequentially latched by each of the latch circuits L1 to L3, and at this time, it is determined whether or not all the outputs from the 3-bit majority circuit T are “0”. A failure diagnosis of the 3-bit majority circuit T when the write data to the EPROM is “0” is performed.
[0016]
[Problems to be solved by the invention]
However, in the above conventional failure diagnosis method, it is determined whether the 3-bit majority circuit T operates normally when the write data to the EPROM with error correction function is “0” or “1”. Therefore, it is necessary to selectively input 1-bit data of “0” and “1” to the three data input lines to the 3-bit majority circuit T.
[0017]
Therefore, in order to use the conventional failure diagnosis method, as shown in FIG. 3, in the EPROM with error correction function, three latch circuits L1 to L3 and three EPROM cells M1 to M3 and Three selectors S1 to S3 must be provided respectively.
[0018]
Therefore, the conventional EPROM with an error correction function has a problem that the number of elements provided for failure diagnosis of the 3-bit majority circuit T increases and the circuit scale (circuit area) increases.
The present invention has been made in view of these problems, and in an EPROM with an error correction function of a 3-bit majority decision system, the number of elements provided in the EPROM is reduced in order to diagnose a failure of the 3-bit majority decision circuit, and an EPROM circuit is provided. The object is to make the area smaller than before.
[0019]
[Means for solving the problems and effects of the invention]
In order to achieve this object, the invention according to claim 1 is characterized in that three EPROM cells to which 1-bit data having the same logical value is written and the same logical value as two or more of outputs from each of these EPROM cells. The invention relates to a failure diagnosis method for diagnosing a failure of a 3-bit majority circuit in an EPROM with an error correction function of a 3-bit majority method having a 3-bit majority circuit that outputs 1-bit data as a value.
[0020]
In the failure diagnosis method according to claim 1, after the same data is written to the three EPROM cells constituting the error correcting EPROM, the three outputs from each EPROM cell are directly input to the 3-bit majority circuit. 1-bit data output from the 3-bit majority circuit is read, and one of the three outputs from each EPROM cell is one-bit data having a logical value different from the data written in each EPROM cell. The three types of 1-bit data output from the 3-bit majority circuit are read out when the 1-bit data and the outputs from the other two EPROM cells are input to the 3-bit majority circuit.
[0021]
Then, when all of the read four types of 1-bit data coincide with the data written in each EPROM cell, it is determined that the 3-bit majority circuit is normal, and among the four types of 1-bit data, If at least one of these is different from the data written in each EPROM cell, it is determined that the 3-bit majority circuit is out of order.
[0022]
That is, according to the fault diagnosis method of the present invention, the EPROM is configured instead of changing the three types of data input to the 3-bit majority circuit to the input data from the outside using a latch circuit or the like as in the prior art. Four types of data (specifically, when the write data to each EPROM cell is “1”) by combining the output from three EPROM cells and one 1-bit data input from the outside. Are four types of data consisting of “1, 1, 1”, “O, 1, 1”, “1, 0, 1”, “1, 1, 0”, and the write data to each EPROM cell If it is “0”, it becomes four types of data consisting of “0, 0, 0”, “1, 0, 0”, “0, 1, 0”, “0, 0, 1”). Input to the 3-bit majority circuit, and at each data input, output data from the 3-bit majority circuit Data is by determining whether all the same as the 1-bit data written in the EPROM cell, determines normal or not is 3 bits majority circuit.
[0023]
Therefore, in realizing the fault diagnosis method of the present invention, it corresponds to each EPROM cell as a latch circuit for latching 1-bit data for writing and fault diagnosis like the conventional EPROM with error correction function. There is no need to provide the three latch circuits, and it is only necessary to provide one latch circuit as a latch circuit for latching 1-bit data for writing and failure diagnosis.
[0024]
Therefore, according to the failure diagnosis method of the present invention, in the EPROM with an error correction function of the 3-bit majority method, in order to diagnose the failure of the 3-bit majority circuit, the circuit area of the EPROM with the error correction function is reduced as before. There is no need to increase the size of the EPROM with the error correction function.
[0025]
In the failure diagnosis method of the present invention, when diagnosing a failure of the 3-bit majority circuit, the outputs of the three EPROM cells constituting the EPROM are used. Therefore, before executing the failure diagnosis, the same EPROM cell is used. It is necessary to write 1-bit data, and for failure diagnosis, only failure diagnosis for 1-bit data (“0” or “1”) written in each EPROM cell can be performed.
[0026]
That is, according to the failure diagnosis method of the present invention, when the 1-bit data written in each EPROM cell is “1”, the 3 bits when the 1-bit data written in each EPROM cell is “0”. If the majority circuit cannot be determined to be faulty and conversely, if 1-bit data written to each EPROM cell is “0”, 1-bit data written to each EPROM cell is “1” The failure determination of the 3-bit majority circuit cannot be performed.
[0027]
Therefore, by using the failure diagnosis method of the present invention, the operation of the 3-bit majority circuit is verified when the write data to each EPROM cell is “1” and “0”, respectively. In this case, it is necessary to change the write data to the EPROM cell to either “1” or “0” in order, and to perform failure diagnosis at the time of writing each data.
[0028]
However, the EPROM only needs to be able to accurately read the data written at the time of shipment, and the 3-bit majority circuit writes to each EPROM cell when one of the three EPROM cells fails. Since it is only necessary to output 1-bit data having the same logical value as the data, actually, after writing the desired 1-bit data to be stored in the EPROM, the failure corresponding to the logical value of the written 1-bit data Just make a decision.
[0029]
Therefore, according to the method of the present invention, at the time of failure diagnosis, it is only necessary to store desired 1-bit data in each EPROM cell and then latch the 1-bit data different from that at the time of data writing in the latch circuit. Since there is no need to individually change the 1-bit data latched by the three latch circuits as in the prior art, the failure determination procedure can be simplified as compared with the conventional failure diagnosis method. It is possible to simplify the configuration of the failure diagnosis device for realizing the failure diagnosis method.
[0030]
Next, the invention according to claim 2 relates to an EPROM with an error correction function of a 3-bit majority vote system that enables failure diagnosis of a 3-bit majority vote circuit by the failure diagnosis method according to claim 1. In addition to one EPROM cell and a three-bit majority circuit, one latch circuit that latches 1-bit data input from the outside and inputs it as write data to each EPROM cell, and 3 from each EPROM cell Each of the data output lines to the bit voting circuit is provided with three selectors for selecting either the output from each EPROM cell or the output from the latch circuit and inputting it to the 3-bit voting circuit. Features.
[0031]
In the EPROM with an error correction function according to claim 2, if 1-bit data for writing is inputted from the outside, the latch circuit latches the data, and a write signal is inputted to each EPROM cell. The same 1-bit data can be written in the EPROM cell. Further, when reading data, by inputting a read signal to each EPROM, the data is output from each EPROM to the 3-bit majority circuit, and then the 1-bit data output from the 3-bit majority circuit is read. Good.
[0032]
The EPROM with error correction function of the present invention is provided with one latch circuit for latching 1-bit data inputted from the outside, and the data output line from each EPROM cell to the 3-bit majority circuit is provided in the data output line. In addition, according to the failure diagnosis method according to claim 1, there is provided a selector for selecting either the output from each EPROM cell or the output from the latch circuit and inputting it to the 3-bit majority circuit. For example, the failure diagnosis of the 3-bit majority circuit can be performed by the following procedures (1) to (3).
[0033]
(1) The desired 1-bit data for data writing is latched by a latch circuit and a write signal is input to each EPROM cell, whereby the same 1-bit data is written to each EPROM cell, and then to each EPROM. By inputting a read signal, 1-bit data is output from each EPROM.
[0034]
(2) Next, 1-bit data for failure diagnosis (data having a logical value different from 1-bit data for data writing) is latched in a latch circuit, and three selectors are connected to each EPROM cell. Is switched from the normal selection state in which the output is selected and input to the 3-bit majority circuit to the latch selection state in which one of the three selectors selects the output from the latch circuit, and in the latch selection state, The selector for selecting the output from the latch circuit is changed in order.
[0035]
As a result, the data input pattern to the 3-bit majority circuit is “1, 1, 1”, “O, 1, 1”, “1” when the write data to each EPROM cell is “1”. , 0, 1 ”,“ 1, 1, 0 ”, and when the write data to each EPROM cell is“ 0 ”,“ 0, 0, 0 ”,“ 1,0, 0 ” ”,“ 0, 1, 0 ”,“ 0, 0, 1 ”.
[0036]
(3) Then, every time the data input pattern to the 3-bit majority circuit is set to one of the four patterns by switching the selection state of each selector, the output from the 3-bit majority circuit is read and read. When all the outputs from the 3-bit majority circuit (four types of outputs) match the 1-bit data written in each EPROM cell, it is determined that the 3-bit majority circuit is normal, and the 3-bit majority If at least one of the outputs (four types of outputs) from the circuit is different from the 1-bit data written to each EPROM cell, it is determined that the 3-bit majority circuit is out of order.
[0037]
On the other hand, the invention described in claim 3 is a device for diagnosing a failure of the 3-bit majority circuit constituting the EPROM with error correction function described in claim 2 using the failure diagnosis method according to claim 1 (failure diagnosis device) ).
In this failure diagnosis apparatus, first, the data writing means causes the latch circuit to latch desired 1-bit data, and writes the 1-bit data latched by the latch circuit to each EPROM cell.
[0038]
When the data writing means writes the same 1-bit data into each EPROM, the diagnosis data input means inputs 1-bit data for failure diagnosis having a logical value different from that at the time of data writing to the latch circuit. And latch the data.
When the diagnostic data input means causes the failure diagnosis 1-bit data to be latched by the latch circuit, the selector driving means selects the three selectors, and all of the three selectors select the output from each EPROM cell. From the normal selection state, one of the three selectors selects the output from the latch circuit, and the other two switches to the latch selection state for selecting the output from the corresponding EPROM cell, and the latch output selection In the state, the data input pattern to the 3-bit majority circuit is changed to “1, 1, 1”, “O, 1, 1”, “1” by sequentially changing the selector that selects the output from the latch circuit. , 0, 1 ”,“ 1, 1, 0 ”, or“ 0, 0, 0 ”,“ 1, 0, 0 ”,“ 0, 1, 0 ”,“ 0, 0, 1 ” Change in order of 4 patterns
[0039]
Then, every time the selector selection unit sets the selection state of the three selectors to one of the four states, the failure determination unit reads four types of 1-bit data output from the 3-bit majority circuit and reads If all four types of 1-bit data match the data written in the EPROM cell by the data writing means, it is determined that the 3-bit majority circuit is normal, and the read four types of 1 If at least one of the bit data is different from the data written by the data writing means in each EPROM cell, it is determined that the 3-bit majority circuit is faulty.
[0040]
Therefore, according to the failure diagnosing device according to claim 3, the above-mentioned procedure according to the failure diagnosing method according to claim 1 is used to detect a failure of the 3-bit majority circuit constituting the error correcting function EPROM according to claim 2. 1) to 3), and the failure diagnosis method according to claim 1 can be realized.
[0041]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments (examples) of the present invention will be described below with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of an EPROM 10 with an error correction function according to an embodiment to which the present invention is applied and a failure diagnosis apparatus 20 connected thereto.
[0042]
As shown in FIG. 1, the EPROM 10 with error correction function of the present embodiment is similar to the conventional EPROM with error correction function shown in FIG. 3, and has three EPROM cells M1, M2 for storing the same 1-bit data. , M3, a 3-bit majority circuit T, and three selectors S1, S2, S3 provided on the data output lines from the respective EPROM cells M1 to M3 to the 3-bit majority circuit T, respectively. 3 differs from the conventional EPROM with an error correction function shown in FIG. 3 in that one latch circuit L0 including a D flip-flop is provided on the data input line to each of the EPROM cells M1 to M3.
[0043]
The output from the latch circuit L0 is not only the data input terminals of the EPROM cells M1 to M3 but also the data of the EPROM cells M1 to M3 among the two data input terminals provided in the selectors S1 to S3. It is connected to another data input terminal different from the data input terminal connected to the output terminal.
[0044]
Therefore, each of the selectors S1 to S3 inputs the outputs DM1 to DM3 from the corresponding EPROM cells M1 to M3 to the 3-bit majority circuit T, or outputs the output DL0 from the latch circuit L0 to the 3-bit majority circuit. Whether to input to T can be selectively switched according to a selection signal SELECT input from the outside.
[0045]
The 3-bit majority circuit T includes two 2-input NOR gates NOR1, NOR2, NOR3 and one 3-input NOR gate NOR0 as in the conventional EPROM with error correction function shown in FIG. The NOR gate NOR0 outputs 1-bit data having the same logical value as two or more of the data D1 to D3 input via the selectors S1 to S3.
[0046]
Therefore, in the EPROM 10 with the error correction function of the present embodiment, desired 1-bit data (logical value: “0” or “1”) is latched in the latch circuit L0 when data is written to each of the EPROM cells M1 to M3. Then, a write command for input data may be input to each of the EPROM cells M1 to M3 (the read / write signal R / W is set to the write level). That is, in this way, 1-bit data having the same logical value can be written into each of the EPROM cells M1 to M3 via the latch circuit L0.
[0047]
Conversely, at the time of data reading, the selectors S1 to S3 are switched to the side selecting the outputs DM1 to DM3 of the EPROM cells M1 to M3, respectively, and data output commands are input to the EPROM cells M1 to M3 (read / read). The write signal R / W may be set to the read level). In other words, in this way, the outputs D1 to D3 from the selectors S1 to S3 become outputs DM1 to DM3 from the EPROM cells M1 to M3, which are input to the 3-bit majority circuit T and input to the 3-bit majority. The output DATA from the circuit T is 1-bit data having the same logical value as two or more of these three input data.
[0048]
Therefore, similarly to the conventional EPROM with error correction function shown in FIG. 3, even if an erase error or an erroneous write error occurs in one of the three EPROM cells M1 to M3, the 3-bit majority circuit T is provided. Accordingly, normal data can be read out.
[0049]
Next, the failure diagnosis apparatus 20 writes desired 1-bit data into each of the EPROM cells M1 to M3 before shipping the EPROM 10 with an error correction function of this embodiment (or an electronic apparatus in which this is incorporated). This is for diagnosing a failure of the majority circuit T, and is constituted by a microcomputer centered on a CPU.
[0050]
Then, the failure diagnosis apparatus 20 performs the data storage / inspection process shown in FIG. 2 to write 1-bit data into the EPROM cells M1 to M3 and to diagnose the failure of the 3-bit majority circuit T. Do. Hereinafter, this process will be described.
[0051]
As shown in FIG. 2, in the data storage / inspection process, first, input data (1-bit data) DIN to the latch circuit L0 should be written to the EPROM cells M1 to M3 in S100 (S represents a step). A desired logical value (“0” or “1”) is set, and this is output as write data to the latch circuit L0, and at the same time, the read / write signal R / R output to each of the EPROM cells M1 to M3. By setting W to the write level, an input data write command is output to each of the EPROM cells M1 to M3.
[0052]
Then, on the EPROM 10 side with the error correction function, the latch circuit L0 latches the write data (DIN) in synchronization with the internal clock CLK output from the failure diagnosis apparatus 20, and each of the EPROM cells M1 to M3 has a latch circuit. Thus, the write data latched by the latch circuit L0 is input. Accordingly, 1-bit data (write data) having a desired logical value output to the latch circuit L0 in S100 is stored in each of the EPROM cells M1 to M3.
[0053]
As described above, when 1-bit data having a desired logical value is written in each of the EPROM cells M1 to M3 in S100, the read / write signal R / W to be output to each of the EPROM cells M1 to M3 in S110. Is set to a read level to set each of the EPROM cells M1 to M3 to a state in which the written data is output, and then the input data (1-bit data) DIN to the latch circuit L0 is set to the EPROM cells M1 to M3. Inverted to a logical value (“1” or “0”) different from the data written to, and outputs this as diagnostic data to the latch circuit L0, thereby causing the latch circuit L0 to latch the diagnostic data.
[0054]
In subsequent S120, all the selectors S1 to S3 are set to the normal selection state in which the outputs DM1 to DM3 from the EPROM cells M1 to M3 are selected, and the EPROM cells M1 to M3 are connected to the 3-bit majority circuit T. After the outputs DM1 to DM3 are input, the output DATA from the 3-bit majority circuit T is read in S130 and stored as basic data DO0 for failure diagnosis.
[0055]
Next, in S140, among the three selectors S1 to S3, the selectors S2 and S3 select the outputs DM2 and DM3 from the EPROM cells M2 and M3, and only the selector S1 selects the output DL0 from the latch circuit L0. Then, the selection state of the selector S1 is switched. As a result, the output DL0 from the latch circuit L0 is input to the 3-bit majority circuit T instead of the output DM1 from the EPROM cell M1 that is input at the time of normal data reading, and the output from the other EPROM cells M2 and M3 is received. The outputs DM2 and DM3 are input as they are as in normal data reading. In the subsequent S150, the output DATA from the 3-bit majority circuit T is read and stored as basic data DO1 for failure diagnosis.
[0056]
In S160, the selectors S1 and S3 among the three selectors S1 to S3 select the outputs DM1 and DM3 from the EPROM cells M1 and M3, and only the selector S2 selects the output DL0 from the latch circuit L0. As described above, the selection states of the selector S1 and the selector S2 are switched. As a result, the output DL0 from the latch circuit L0 is input to the 3-bit majority circuit T in place of the output DM2 from the EPROM cell M2 that is input at the time of normal data reading, and the output from the other EPROM cells M1 and M3. The outputs DM1 and DM3 are input as they are as in normal data reading. In the subsequent S170, the output DATA from the 3-bit majority circuit T is read and stored as basic data DO2 for failure diagnosis.
[0057]
Furthermore, in the subsequent S180, among the three selectors S1 to S3, the selectors S1 and S2 select the outputs DM1 and DM2 from the EPROM cells M1 and M2, and only the selector S3 selects the output DL0 from the latch circuit L0. In this manner, the selection states of the selector S2 and the selector S3 are switched. As a result, the output DL0 from the latch circuit L0 is input to the 3-bit majority circuit T instead of the output DM3 from the EPROM cell M3 that is input at the time of normal data reading, and the output from the other EPROM cells M1 and M2 is received. The outputs DM1 and DM2 are input as they are as in normal data reading. In S190, the output DATA from the 3-bit majority circuit T is read and stored as basic data DO3 for failure diagnosis.
[0058]
That is, in S120 to S190, when the 1-bit data written in the EPROM cells M1 to M3 in S100 is “1”, the data input pattern to the 3-bit majority circuit T is “1, 1, 1 ”,“ O, 1, 1 ”,“ 1, 0, 1 ”,“ 1, 1, 0 ”are changed to 4 patterns, and conversely, 1 bit written to each EPROM cell M1 to M3 in S100 When the data is “0”, the data input pattern to the 3-bit majority circuit T is “0, 0, 0”, “1, 0, 0”, “0, 1, 0”, “0, The output data from the 3-bit majority circuit T is read for each of these four types of data input patterns.
[0059]
In this way, when four types of basic data DO0-DO3 output from the 3-bit majority circuit T when data is input in the data input patterns are obtained, the process proceeds to S210, and each of these basic data DO0 is obtained. It is determined whether or not all of DO3 coincide with the 1-bit data (data for writing) written in each of the EPROM cells M1 to M3 in S100.
[0060]
And when each basic data DO0-DO3 is in agreement with the data for writing, each basic data DO0-DO3 is all normal, and since the 3 bit majority circuit T is functioning normally, Subsequently, the process proceeds to S220, informing that the memory (specifically, the EPROM 10 with an error correction function connected to the failure diagnosis apparatus 20) is normal, and ends the process.
[0061]
On the other hand, even if one of the basic data DO0 to DO3 has a logical value different from that of the writing data, if it is determined in S210 that at least one of the basic data DO0 to DO3 is abnormal, the process proceeds to S230. .
In S230, an abnormal location in the 3-bit majority circuit T is specified from the type of basic data having a logical value different from that of the write data, and the specified information can be read later by the administrator. After storing in a predetermined storage medium and notifying that the memory is abnormal in the subsequent S240, the process ends.
[0062]
As described above, the failure diagnosis apparatus 20 first stores predetermined 1-bit data in each of the EPROM cells M1 to M3, and then, three 1-bit data output from each of the EPROM cells M1 to M3, Using the output from each of the EPROM cells M1 to M3 latched in the latch circuit L0 and 1-bit data whose logic is inverted, the data input pattern to the 3-bit majority circuit T is switched to the above four patterns. By determining whether all the data output from the 3-bit majority circuit T has the same logical value as the 1-bit data stored in the EPROM cells M1 to M3, the 3-bit majority circuit T is normal. Diagnose whether or not.
[0063]
Therefore, in the EPROM 10 with the error correction function diagnosed as normal by the failure diagnosis device 20, during the subsequent use, one of the three EPROM cells M1 to M3 is erased or erroneously written. Even if an error occurs, normal 1-bit data stored in the remaining two can be output by the operation of the 3-bit majority circuit T.
[0064]
Then, on the side of the EPROM 10 with an error correction function diagnosed by the failure diagnosis device 20, there are three latch circuits L1 to L3 corresponding to the EPROM cells M1 to M3 as in the conventional EPROM shown in FIG. There is no need to provide this, and it is only necessary to provide one latch circuit L0 common to each of the EPROM cells M1 to M3. The electronic device in which the function-equipped EPROM 10 is incorporated can be reduced in size.
[0065]
In this embodiment, the processing of S100 for writing desired 1-bit data to each of the EPROM cells M1 to M3 corresponds to the data writing means according to claim 3, and latches data for failure diagnosis in the latch circuit L0. The processing of S110 to be performed corresponds to the diagnostic data input means according to claim 3, and S120 and S140 for driving the selectors S1 to S3 in order to sequentially switch the data input pattern to the 3-bit majority circuit T to the four patterns described above. , S160 and S180 correspond to the selector driving means according to claim 3, and every time the data input pattern to the 3-bit majority circuit T is set, the output DATA from the 3-bit majority circuit T is read and read. S130, S150, S170, S1 for performing failure diagnosis of the 3-bit majority circuit T based on the four types of data DO0 to DO3 0, the processing of S210~S240 correspond to the failure determining means according to claim 3.
[0066]
Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and can take various forms.
For example, in the above embodiment, the failure diagnosis device 20 has been described as performing data writing and failure diagnosis on one EPROM 10 with error correction function. However, the electronic device may include a plurality of EPROMs 10 with error correction function. In such a case, the writing of data into each error correcting function EPROM 10 and the failure diagnosis may be performed in the order described above. In addition, the failure diagnosis device 20 may be configured integrally with a plurality of EPROMs 10 with error correction functions or an electronic device incorporating the same.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of an EPROM with an error correction function according to an embodiment and a failure diagnosis apparatus connected thereto.
FIG. 2 is a flowchart showing data storage / inspection processing executed by the failure diagnosis apparatus.
FIG. 3 is a circuit diagram showing a configuration of a conventional EPROM with an error correction function.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... EPROM with an error correction function, 20 ... Fault diagnosis apparatus, L0 ... Latch circuit, M1, M2, M3 ... EEPROM cell, S1, S2, S3 ... Selector, T ... 3-bit majority circuit.

Claims (3)

Three EPROM cells to which 1-bit data having the same logical value is written;
A 3-bit majority decision that takes in the output from each of the EPROM cells and takes the majority decision of the taken-in three outputs and outputs 1-bit data having the same logical value as two or more of the three outputs. Circuit,
A fault diagnosis method for diagnosing a failure of the 3-bit majority circuit in an EPROM with an error correction function comprising:
After writing the same data to the three EPROM cells,
1 bit data output from the 3 bit majority circuit when the 3 outputs from each EPROM cell are directly input to the 3 bit majority circuit and
While changing one of the three outputs from each EPROM cell to 1-bit data having a different logical value from the data written to each EPROM cell, the 1-bit data and the other two By inputting the output from the EPROM cell to the 3-bit majority circuit, three types of 1-bit output from the 3-bit majority circuit when one of the outputs of each EPROM cell has a different logic value. Read data respectively
When all of the read four types of 1-bit data match the data written in each EPROM cell, it is determined that the 3-bit majority circuit is normal, and the four types of 1-bit data A fault diagnosis method for an EPROM with an error correction function, characterized in that if at least one of them is different from the data written in each EPROM cell, it is determined that the 3-bit majority circuit is faulty. Three EPROM cells to which 1-bit data having the same logical value is written;
A 3-bit majority decision that takes in the output from each of the EPROM cells and takes the majority decision of the taken-in three outputs and outputs 1-bit data having the same logical value as two or more of the three outputs. Circuit,
EPROM with error correction function with
One latch circuit that latches 1-bit data input from the outside and inputs the data to each of the EPROM cells as write data;
Each of the EPROM cells is provided on a data output line from the EPROM cell to the 3-bit majority circuit, and either the output from each EPROM cell or the output from the latch circuit is selected and input to the 3-bit majority circuit. Selectors,
The input data to the latch circuit is changed to a logical value different from the data written in each EPROM cell, and one of the selectors is sequentially switched to the latch circuit output selection side. An EPROM with an error correction function, wherein failure diagnosis of the 3-bit majority circuit by the failure diagnosis method described above can be executed. A failure diagnosis device for diagnosing a failure in a 3-bit majority circuit of an EPROM with an error correction function according to claim 2 using the failure diagnosis method according to claim 1,
Data writing means for causing the latch circuit to latch desired 1-bit data and writing the 1-bit data latched by the latch circuit to the EPROM cells, respectively;
Diagnostic data input means for inputting 1-bit data for failure diagnosis having a logic value different from that at the time of data writing to the latch circuit after data writing by the data writing means, and latching the data ,
After the diagnostic data input means latches the 1-bit data for failure diagnosis in the latch circuit, the three selectors are selected, and all of the three selectors select the output from each EPROM cell. From the selected state, one of the three selectors selects the output from the latch circuit, and the remaining two switch to the latch selected state for selecting the output from the corresponding EPROM cell, and the latch selection In the state, the selector driving means for sequentially changing the selection state of the three selectors to the four states including the normal selection state by sequentially changing the selector that selects the output from the latch circuit;
Each time the selection state of the three selectors is set to one of the four states by the selector driving means, 1-bit data output from the 3-bit majority circuit is read, and the read four types of 1-bit data Are all the same as the data written by the data writing means to the EPROM cell, it is determined that the 3-bit majority circuit is normal, and at least one of the four types of 1-bit data is determined. Failure determination means for determining that the 3-bit majority circuit has failed when the data writing means is different from the data written in each EPROM cell;
EPROM fault diagnosis apparatus with error correction function, characterized by comprising:

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