JP4061651B2 - Ferroelectric memory device and electronic device - Google Patents

Description

  The present invention relates to a ferroelectric memory device and an electronic apparatus.

As a conventional ferroelectric memory device, there is one disclosed in JP-A-11-191295 (Patent Document 1). In the ferroelectric memory device disclosed in Patent Document 1, a read operation is performed twice with respect to the same memory cell, and a charge read at the first time is used as data, and a charge is read at the second time. The memory cell data is detected by a sense amplifier with reference to.
Japanese Patent Laid-Open No. 11-191295

  However, since the conventional ferroelectric memory device disclosed in Patent Document 1 must have a sense amplifier for each bit line, the number of sense amplifiers is greatly increased. As a result, the circuit area of the ferroelectric memory device increases, and the power consumption also increases.

  Accordingly, an object of the present invention is to provide a ferroelectric memory device and an electronic apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above problems, according to the first aspect of the present invention, a plurality of memory cells having ferroelectric capacitors for storing predetermined data, and a plurality of word lines respectively connected to the plurality of memory cells By changing the potential of a plurality of bit lines, a plurality of plate lines, and a predetermined plate line connected to a predetermined memory cell, a data storage charge stored in a predetermined memory cell and indicating predetermined data is predetermined. The predetermined data stored in the predetermined memory cell is read out by discharging to a predetermined bit line connected to the memory cell, and the charge stored in the predetermined memory cell from which the predetermined data is read A plate line control unit for discharging a reference accumulated charge to a predetermined bit line, a first sense amplifier line and a second sense amplifier line, and a change in potential of the predetermined plate line And a bit line selection unit for selecting a predetermined bit line from a plurality of bit lines to be connected to the first sense amplifier line and the second sense amplifier line, and connecting the predetermined bit line to the first sense amplifier line. Thus, the potential of the predetermined bit line when the data storage charge is released is held in the first sense amplifier line, and the reference bit stored in the second sense amplifier line is released by connecting the predetermined bit line to the second sense amplifier line. A predetermined bit line stored in a predetermined memory cell based on a bit line connecting portion for holding the potential of the predetermined bit line in the second sense amplifier line and the potentials of the first sense amplifier line and the second sense amplifier line A ferroelectric memory device comprising a sense amplifier for determining data is provided.

  According to the above configuration, the bit line connection unit reads the data stored in the ferroelectric capacitor when the plate line is selected and the charge accumulated in the ferroelectric capacitor is discharged to the bit line. When this is done, the bit line is connected to the first sense amplifier line, and the potential of the bit line is held in the first sense amplifier line. In other words, the first sense amplifier line holds a potential corresponding to the data stored in the ferroelectric capacitor.

  The bit line connection unit connects the bit line to the second sense amplifier line when the charge accumulated in the ferroelectric capacitor from which data has already been read is discharged to the bit line. Is held in the second sense amplifier line. Here, for example, the potential held in the second sense amplifier line is substantially equal to the potential of the bit line when the “0” data stored in the ferroelectric capacitor is read.

  That is, in the first read operation, data stored in a predetermined ferroelectric capacitor is read, and the accumulated charge (data accumulated charge) corresponding to the data is held in the first sense amplifier line, and the second read is performed. In operation, the accumulated charge (reference accumulated charge) corresponding to the data stored in the predetermined ferroelectric capacitor from which the data is read is held in the second sense amplifier line. The reference accumulated charge released to the second sense amplifier line in the second read operation corresponds to the data written in the ferroelectric capacitor by inverting the polarization of the ferroelectric capacitor in the first read operation. The charge corresponding to the data held in the ferroelectric capacitor is read by reading out the data stored in the ferroelectric capacitor without inverting the polarization of the ferroelectric capacitor in the first read operation. Including. The data corresponding to the reference accumulated charge may be “0” data or “1” data.

  Therefore, according to the above configuration, for example, the data stored in the ferroelectric capacitor is determined based on the potential of the bit line when the “0” data stored in the ferroelectric capacitor is read. be able to. That is, since the reference voltage for determining the data stored in the ferroelectric capacitor can be generated by self-reading, the ferroelectric capacitor can be used even if there are manufacturing variations or changes with time of the ferroelectric capacitor. Can be determined with high accuracy. As a result, a highly reliable ferroelectric memory device with extremely few malfunctions can be provided.

  Further, according to the above configuration, the bit line is selected by selecting the bit line connected to the first sense amplifier line and the second sense amplifier line from among a large number of bit lines based on the potential of the plate line. Is held in the first sense amplifier line and the second sense amplifier line. Therefore, according to the above configuration, data stored in a large number of ferroelectric capacitors can be read out by one sense amplifier, so that the number of sense amplifiers can be greatly reduced. As a result, it is possible to provide an inexpensive ferroelectric memory device that consumes very little power.

  The ferroelectric memory device preferably further includes an offset voltage generation unit that adds an offset voltage to the second sense amplifier line, and the offset voltage generation unit includes a predetermined bit line discharged from the second sense amplifier line. When holding the potential, an offset voltage is added to the second sense amplifier line, and the sense amplifier can determine predetermined data based on the potential of the second sense amplifier line to which the offset voltage is added. preferable.

  According to the above configuration, the reference voltage when the sense amplifier determines the data stored in the ferroelectric capacitor by adding the offset voltage to the potential of the bit line when the charge is discharged from the ferroelectric capacitor. It is said. Therefore, according to the above configuration, since the reference voltage is generated based on the electric charge discharged from the ferroelectric capacitor, even if there are manufacturing variations or changes with time of the ferroelectric capacitor, the reference voltage is stored in the ferroelectric capacitor. The determined data can be accurately determined.

  In the ferroelectric memory device, the bit line selection unit is provided between the plurality of bit lines and the first sense amplifier line, and the plate lines corresponding to the bit lines are respectively connected to the gates. It is preferable to have a 1MOS transistor and a plurality of second MOS transistors provided between the plurality of bit lines and the second sense amplifier lines, respectively, and plate lines corresponding to the bit lines are respectively connected to the gates.

  According to the above configuration, a bit line to be connected to the first sense amplifier line and the second sense amplifier line can be easily selected from a large number of bit lines with a very simple configuration.

  In the ferroelectric memory device, the bit line connection unit includes a plurality of third MOS transistors provided between the plurality of bit lines and the plurality of first MOS transistors, a plurality of bit lines, and a plurality of second MOS transistors, respectively. It is preferable to have a plurality of fourth MOS transistors respectively provided between them.

  A write control unit for storing the data in a memory cell connected to the predetermined bit line by controlling the potential of the predetermined bit line based on the determination result of the data determined by the sense amplifier. preferable.

  According to the above configuration, the data is rewritten to the ferroelectric capacitor based on the determination result of the data read from the ferroelectric capacitor. Therefore, even when the data is destroyed when the data is read from the ferroelectric capacitor, for example, when data different from the data is written in the ferroelectric capacitor. The data can be reliably rewritten.

  The first sense amplifier line and the second sense amplifier line are preferably disposed substantially at right angles to the bit line.

  According to the above configuration, a large number of bit lines arranged in the memory cell block can be easily connected to the first sense amplifier line and the second sense amplifier line.

  According to a second aspect of the present invention, there is provided an electronic apparatus comprising the ferroelectric memory device. Here, the electronic device refers to a general device having a certain function provided with the ferroelectric memory device according to the present invention, and its configuration is not particularly limited. For example, a computer including the above ferroelectric memory device is used. General devices, mobile phones, PHS, PDAs, electronic notebooks, IC cards, and other devices that require storage devices are included.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential to the solution of the invention.

  FIG. 1 is a diagram showing an example of the configuration of a ferroelectric memory device 100 according to an embodiment of the present invention. The ferroelectric memory device 100 includes a memory cell block 110, a word line driver 120, a plate line driver 130 which is an example of a plate line control unit, a read control circuit 132, an address decoder 134, a discharge unit 140, A rewrite control unit 150, which is an example of a write control unit, a bit line connection unit 160, a bit line selection unit 170, a first sense amplifier line SLA and a second sense amplifier line SLB, and a sense amplifier line discharge unit 180 The offset voltage generator 190 and the sense amplifier 210 are provided.

  The memory cell block 110 includes a plurality of memory cells MC arranged in an array, each of which includes a ferroelectric capacitor C and an n-type MOS transistor TR. The memory cell block 110 includes a plurality of word lines WL1 to WLm (m is an integer of 2 or more), a plurality of bit lines BL1 to BLn (n is an integer of 2 or more), and a plurality of plate lines PL1 to PLn. Has been placed. In each memory cell MC, a predetermined word line WLi (i is an integer of 1 to m) is connected to the gate of the n-type MOS transistor TR, and one end of the ferroelectric capacitor C is connected via the n-type MOS transistor TR. A predetermined bit line BLj (j is an integer of 1 to n) is connected, and a predetermined plate line PLj (j is an integer of 1 to n) is connected to the other end of the ferroelectric capacitor C. Yes.

  The address decoder 134 generates a word line selection signal indicating a word line to be selected and a plate line selection signal indicating a plate line to be selected based on an address signal supplied from the outside. Supplied to the driver 130. Further, the address decoder 134 supplies a control signal for controlling the discharge unit 140 and the bit line connection unit 160 to the read control circuit 132 in a read operation of reading data stored in the memory cell MC.

  The word line driver 120 and the plate line driver 130 change the potentials of the predetermined word line WLi and the predetermined plate line PLj based on the word line selection signal and the plate line selection signal, respectively. WLi and the predetermined plate line PLj are selected.

  The read control circuit 132 controls the operations of the discharge unit 140 and the bit line connection unit 160 based on the control signal supplied from the address decoder 134. Specifically, the read control circuit 132 controls the potentials of the bit line precharge signal BLP supplied to the discharge unit 140 and the bit line connection control signals SWA and SWB supplied to the bit line connection unit 160, thereby discharging. The operations of the unit 140 and the bit line connection unit 160 are controlled.

  The discharge unit 140 grounds each bit line BLj based on the potential of BLP. The discharge unit 140 includes an n-type MOS transistor 142 having a drain connected to each bit line BLj, a source grounded, and a gate supplied with BLP. The discharge unit 140 also functions as a precharge unit that precharges the bit line BLj by discharging the bit line BLj.

  The bit line selection unit 170 selects the bit line BLj to be connected to the first sense amplifier line SLA and the second sense amplifier line SLB from the bit lines BL1 to BLn. The bit line selection unit 170 includes n-type MOS transistors 172 and 174 provided between the bit lines BL1 to BLn and the first sense amplifier line SLA and the second sense amplifier line SLB, respectively. The plate line PLj is connected to the gates of the n-type MOS transistors 172 and 174 provided on the bit line BLj. The n-type MOS transistors 172 and 174 connect the bit line BLj based on the potential of the plate line PLj. The first sense amplifier line SLA and the second sense amplifier line SLB are connected. That is, among the bit lines BL1 to BLn, the bit line BLj for which the corresponding plate line PLj is selected is placed in a state where it can be connected to the first sense amplifier line SLA and the second sense amplifier line SLB.

  The bit line connection unit 160 connects the bit lines BL1 to BLn to one of the first sense amplifier line SLA and the second sense amplifier line SLB. The bit line connection unit 160 includes an n-type MOS transistor 162 provided between the bit lines BL1 to BLn and the first sense amplifier line SLA, and between the bit lines BL1 to BLn and the second sense amplifier line SLB. Each of the n-type MOS transistors 164 is provided. A control signal SWA is supplied to the gate of the n-type MOS transistor 162, and a control signal SWB is supplied to the gate of the n-type MOS transistor 164. The n-type MOS transistors 162 and 164 are connected to SWA and SWB, respectively. Based on the potential, the bit lines BL1 to BLn are connected to either the first sense amplifier line SLA or the second sense amplifier line SLB.

  In the present embodiment, the bit line connection unit 160 connects the selected bit line BLj and the first sense amplifier line SLA to read data stored in the ferroelectric capacitor C, that is, The potential of the bit line BLj when the accumulated charge in the ferroelectric capacitor C is released is held in the first sense amplifier line SLA. In addition, the bit line connection unit 160 holds the discharged potential of the bit line BLj in the second sense amplifier line SLB by connecting the bit line BLj and the second sense amplifier line SLB.

  The sense amplifier line discharge unit 180 discharges the first sense amplifier line SLA and the second sense amplifier line SLB based on the sense amplifier line precharge signal SLP supplied from the read control circuit 132. The sense amplifier line discharge unit 180 includes n-type MOS transistors 182, 184, and 186. The n-type MOS transistor 182 is provided between the first sense amplifier line SLA and the second sense amplifier line SLB, and the first sense amplifier line SLA and the second sense amplifier line SLB are connected based on the potential of SLP. Set to the same potential. Each of the n-type MOS transistors 182 and 184 has a drain connected to the first sense amplifier line SLA or the second sense amplifier line SLB, a source grounded, and based on the potential of the SLP, The second sense amplifier line SLB is grounded.

  The offset voltage generator 190 adds an offset voltage to the second sense amplifier line SLB. The offset voltage generator 190 is, for example, a constant voltage circuit that generates a constant voltage.

  The sense amplifier 210 is connected to the first sense amplifier line SLA and the second sense amplifier line SLB, and is stored in the ferroelectric capacitor C based on the potentials of the first sense amplifier line SLA and the second sense amplifier line SLB. Determine the processed data.

  In the present embodiment, the sense amplifier 210 is the first potential of the bit line BLj when the accumulated charge of the ferroelectric capacitor C is discharged with reference to the potential of the second sense amplifier line SLB to which the offset voltage is added. The data stored in the ferroelectric capacitor C is determined by detecting the potential of one sense amplifier line SLA. Further, the sense amplifier 210 outputs a sense amplifier output signal SAOUT indicating the determination result of the data.

  The first sense amplifier line SLA and the second sense amplifier line SLB are arranged substantially at right angles to the bit lines BL1 to BLn. In the present embodiment, one set of the first sense amplifier line SLA and the second sense amplifier line SLB is provided for one memory cell block 110, that is, one sense amplifier 210 is provided for one memory cell block 110. However, in another example, one memory cell block 110 is divided into a plurality of regions, and a set of first sense amplifier line SLA and second sense amplifier line SLB is provided for each region. It may be configured. One memory cell block 110 is a block including a plurality of memory cells MC controlled by one word line driver 120 and one plate line driver 130, for example.

  The rewrite control unit 150 controls the potentials of the bit lines BL1 to BLn in order to rewrite the data read from the ferroelectric capacitor C to the ferroelectric capacitor C. The bit lines BL1 to BLn are connected to the drains of a p-type MOS transistor 152 whose source is supplied with VCC and an n-type MOS transistor 154 whose source is grounded. Then, the rewrite control unit 150 controls the potential of the bit line BLj to which the memory cell MC from which data is read is connected based on the SAOUT and the rewrite control signal RW received as inputs. The data is rewritten to the memory cell MC (ferroelectric capacitor C).

  FIG. 2 is a timing chart showing the operation of the ferroelectric memory device 100 of this embodiment. The operation of the ferroelectric memory device 100 will be described with reference to FIGS. In FIG. 2, in a period in which both the solid line and the dotted line exist, the solid line indicates that the data stored in the ferroelectric capacitor C is “1”, and the dotted line indicates that the data is “0”. Indicates.

  First, in cycle I, the read control circuit 132 changes the potentials of BLP and SLP to VCC, thereby discharging the bit lines BL1 to BLn, the first sense amplifier line SLA, and the second sense amplifier line SLB. The read control circuit 132 discharges the bit lines BL1 to BLn, the first sense amplifier line SLA, and the second sense amplifier line SLB, sets the potentials of BLP and SLP to 0 V, and sets the bit lines BL1 to BLn and the first sense amplifier line. The SLA and the second sense amplifier line SLB are brought into a floating state.

  Next, in cycle II, the plate line driver 130 changes the potential of the bit line BL1 from 0V to VCC. Thereby, based on the data stored in the ferroelectric capacitor C, the accumulated charge is discharged from the ferroelectric capacitor C to the bit line BL1, and the potential of the bit line BL1 changes based on the data.

  Specifically, when “1” is stored in the ferroelectric capacitor C, the polarization of the ferroelectric capacitor C is inverted, so that the change in the polarization amount accompanying the inversion is large. Accordingly, a large amount of accumulated charge is released from the ferroelectric capacitor C to the bit line BL1, and the potential of the bit line BL1 greatly increases.

  On the other hand, when “0” is stored in the ferroelectric capacitor C, the polarization of the ferroelectric capacitor C is not reversed, so the change in the polarization amount is small. Accordingly, the accumulated charge discharged from the ferroelectric capacitor C to the bit line BL1 is smaller than that in the case where the data stored in the ferroelectric capacitor C is “1”, so that the potential of the bit line BL1 rises so much. do not do.

  Further, when the potential of the plate line PL1 changes from 0V to VCC, the n-type MOS transistors 172 and 174 become conductive, so that the bit line BL1 can be connected to the first sense amplifier line SLA and the second sense amplifier line SLB. I'm left.

  Next, the read control circuit 132 connects the bit line BL1 and the first sense amplifier line SLA by changing the potential of SWA from 0 V to VCC. As a result, the potential of the first sense amplifier line SLA in the floating state becomes substantially the same as the potential of the bit line BL1. Then, the read control circuit 132 electrically disconnects the bit line BL1 and the first sense amplifier line SLA by changing the potential of SWA from VCC to 0V, and reads the data stored in the ferroelectric capacitor C. The potential of the bit line BL1 when it is output is held in the first sense amplifier line SLA.

  Next, the plate line driver 130 changes the potential of the plate line PL1 from VCC to 0V, thereby setting the potential of the plate line PL1 to 0V. Further, the read control circuit 132 changes the potential of BLP from 0 V to VCC, thereby storing the reference accumulated charge in the ferroelectric capacitor C as “0” data.

  Next, in cycle III, after the read control circuit 132 causes the bit line BL1 to float again, the plate line driver 130 changes the potential of the plate line PL1 from 0 V to VCC, thereby accumulating the ferroelectric capacitor C. Charge is discharged to the bit line BL1. At this time, since “0” is stored in the ferroelectric capacitor C, the change in the polarization amount of the ferroelectric capacitor C is small, and the accumulated charge discharged from the ferroelectric capacitor C to the bit line BL1 is Few. Therefore, the potential of the bit line BL1 rises to substantially the same potential as the potential of the bit line BL1 when the accumulated charge based on the “0” data is released from the ferroelectric capacitor C in the cycle II.

  Next, the read control circuit 132 connects the bit line BL1 and the second sense amplifier line SLB by changing the potential of SWB from 0V to VCC. As a result, the potential of the second sense amplifier line SLB in the floating state becomes substantially the same as the potential of the bit line BL1. Then, the read control circuit 132 electrically disconnects the bit line BL1 and the second sense amplifier line SLB by changing the potential of SWB from VCC to 0V, and reads “0” data from the ferroelectric capacitor C. The second sense amplifier line SLB holds the potential of the bit line BL1, which is substantially the same potential as when it is emitted.

  Further, the offset voltage generation unit 190 generates the offset voltage Vp and adds it to the second sense amplifier line SLB. That is, the potential of the second sense amplifier line SLB rises to a potential obtained by adding the offset voltage Vp to the potential of the bit line BL1. As for the offset voltage Vp, when the offset voltage Vp is added to the potential of the second sense amplifier line SLB, the potential of the second sense amplifier line SLB after the addition is read from the ferroelectric capacitor C as “1” data. It is set to be a potential between the potential of the first sense amplifier line SLA when it is output and the potential of the second sense amplifier line SLB when “0” data is read.

Here, as described above, the reference accumulated charge is not limited to storing and using “0” data, but may be configured to use “1” data. In that case, the offset voltage Vp is configured so that a voltage obtained by subtracting Vp as a negative voltage becomes the reference potential. Further, when “0” data is used for the reference accumulated charge, when the data stored in the ferroelectric capacitor C in the cycle II is “0”, the read charge is used as the reference accumulated charge. Also good.

  Next, in cycle IV, the data stored in the ferroelectric capacitor C is determined. First, the SAE potential changes from 0 V to VCC, and the sense amplifier 210 becomes operable. When the sense amplifier 210 becomes operable, the sense amplifier 210 compares the first sense amplifier line SLA and the second sense amplifier line SLB, and stores the comparison result SAOUT in the ferroelectric capacitor C. Is output as a result of determining the determined data.

  In the present embodiment, the first sense amplifier line SLA holds the potential of the bit line BL1 when the data stored in the ferroelectric capacitor C is read. The second sense amplifier line SLB is a bit line when data stored in the ferroelectric capacitor C is read and the bit line BL1 is discharged and then data is read from the ferroelectric capacitor C again. A potential obtained by adding the offset voltage Vp to the potential of BL1 is held. Then, the sense amplifier 210 determines the data stored in the ferroelectric capacitor C by using the potential held in the second sense amplifier line SLB as a reference voltage and comparing it with the potential of the first sense amplifier line SLA. .

  Specifically, the sense amplifier 210 determines that the data stored in the ferroelectric capacitor C is “1” when the potential of the first sense amplifier line SLA is higher than the potential of the second sense amplifier line SLB. Then, H logic (voltage VCC) is output as SAOUT. On the other hand, when the potential of the first sense amplifier line SLA is lower than the potential of the second sense amplifier line SLB, the sense amplifier 210 determines that the data stored in the ferroelectric capacitor C is “0”, and SAOUT L logic (voltage 0 V) is output.

  Next, the rewrite control unit 150 rewrites the data to the ferroelectric capacitor C from which the data has been read based on the SAOUT and the rewrite control signal RW. Specifically, the rewrite control unit 150 determines that RW has H logic when SAOUT indicates H logic, that is, if it is determined that the data stored in the ferroelectric capacitor C is “1”. In the period shown, the potential of the bit line BL1 is raised to VCC by setting the potential of RWA to 0V. Further, the plate line driver 130 changes the potential of the plate line PL1 from VCC to 0V. Thereby, since the voltage of + VCC is applied to the ferroelectric capacitor C with reference to the plate line PL1, the data “1” is written again.

  On the other hand, when SAOUT indicates L logic, that is, when it is determined that the data stored in the ferroelectric capacitor C is “0”, the rewrite controller 150 determines that RW indicates H logic. The potential of the bit line BL1 is set to 0V by setting the potential of RWB to VCC. Thereby, since the voltage of −VCC is applied to the ferroelectric capacitor C with respect to the plate line PL1, the data “0” is written again. Further, since the voltage applied to the ferroelectric capacitor C is substantially zero after the plate line driver 130 changes the potential of the plate line PL1 from VCC to 0V, the ferroelectric capacitor C stores the rewritten data “0”. ”. With the above operation, the data stored in the ferroelectric capacitor C can be read and the read data can be rewritten to the ferroelectric capacitor C.

  According to the present embodiment, for example, the data stored in the ferroelectric capacitor C is determined based on the potential of the bit line BLj when the “0” data stored in the ferroelectric capacitor C is read. can do. That is, as shown in FIG. 3, since the reference voltage for determining the data stored in the ferroelectric capacitor can be generated by self-reading, there is a manufacturing variation of the ferroelectric capacitor or a change with time. However, the data stored in the ferroelectric capacitor can be accurately determined. As a result, a highly reliable ferroelectric memory device with extremely few malfunctions can be provided.

  Further, according to the present embodiment, the connection to the first sense amplifier line SLA and the second sense amplifier line SLB from a number of bit lines, for example, the bit lines BL1 to BLn, based on the potential of the plate line PLj. By selecting the bit line BLj to be held, the potential of the bit line BLj is held in the first sense amplifier line SLA and the second sense amplifier line SLB. Therefore, according to the present embodiment, since the data stored in a large number of ferroelectric capacitors C can be read by one sense amplifier 210, the number of sense amplifiers 210 can be greatly reduced. As a result, it is possible to provide an inexpensive ferroelectric memory device that consumes very little power.

  FIG. 4 is a perspective view showing a configuration of a personal computer 1000 which is an example of the electronic apparatus of the present invention. In FIG. 4, the personal computer 1000 includes a display panel 1002 and a main body 1006 having a keyboard 1004. As a storage medium of the main body 1004 of the personal computer 1000, particularly a non-volatile memory, a semiconductor device including the storage circuit of the present invention is used.

  The examples and application examples described through the embodiments of the present invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not a thing. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

1 is a diagram illustrating an example of a configuration of a ferroelectric memory device 100 according to an embodiment of the present invention. 3 is a timing chart showing the operation of the ferroelectric memory device 100 of the present embodiment. It is a figure which shows the relationship between the electric potential of a bit line when data is read from a ferroelectric capacitor, and a reference voltage. 1 is a perspective view illustrating a configuration of a personal computer 1000 which is an example of an electronic apparatus according to the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device, 110 ... Memory cell block, 120 ... Word line driver, 130 ... Plate line driver, 132 ... Read control circuit, 134 ... Address decoder, 140 ... Discharge unit, 150 ... Rewrite control unit, 160 ... Bit line connection unit, 170 ... Bit line selection unit, 180 ... Sense amplifier line discharge unit, 190 ... Offset voltage generation 210, sense amplifier, RW, rewrite control signal, SAOUT, sense amplifier output signal, SLA, sense amplifier line, SLB, sense amplifier line, SLP, sense amplifier line. Precharge signal, SWA, SWB ... Bit line connection control signal

Claims (8)

A plurality of memory cells having ferroelectric capacitors for storing predetermined data;
A plurality of word lines, a plurality of bit lines, and a plurality of plate lines respectively connected to the plurality of memory cells;
By changing the potential of a predetermined plate line connected to a predetermined memory cell, a data storage charge indicating the predetermined data stored in the predetermined memory cell is changed to a predetermined value connected to the predetermined memory cell. The predetermined data stored in the predetermined memory cell is read by being discharged to the bit line, and the reference accumulated charge, which is the charge accumulated in the predetermined memory cell from which the predetermined data is read, is read out. A plate line controller that emits to the bit line of
A first sense amplifier line and a second sense amplifier line;
A bit line selector that selects the predetermined bit line from the plurality of bit lines to be connected to the first sense amplifier line and the second sense amplifier line based on a change in potential of the predetermined plate line;
By connecting the predetermined bit line to the first sense amplifier line, the potential of the predetermined bit line when the data storage charge is released is held in the first sense amplifier line, and the predetermined bit line is retained. A bit line connection unit for holding the potential of the predetermined bit line in the second sense amplifier line when the reference accumulated charge is released by connecting a line to the second sense amplifier line;
A ferroelectric memory comprising: a sense amplifier that determines the predetermined data stored in the predetermined memory cell based on a potential of the first sense amplifier line and the second sense amplifier line. apparatus. 2. The ferroelectric memory device according to claim 1, further comprising an offset voltage generation unit that adds an offset voltage to the second sense amplifier line . The offset voltage generator adds the offset voltage to the second sense amplifier line when the second sense amplifier line holds the discharged potential of the predetermined bit line,
3. The ferroelectric memory device according to claim 2, wherein the sense amplifier determines the predetermined data based on a potential of the second sense amplifier line to which the offset voltage is added. The bit line selector is
A plurality of first MOS transistors provided between the plurality of bit lines and the first sense amplifier line, each of the plate lines corresponding to the bit lines being connected to a gate;
And a plurality of second MOS transistors provided between the plurality of bit lines and the second sense amplifier lines, respectively, and the plate lines corresponding to the bit lines are respectively connected to gates. The ferroelectric memory device according to claim 1. The bit line connection part is:
A plurality of third MOS transistors respectively provided between the plurality of bit lines and the plurality of first MOS transistors;
5. The ferroelectric memory according to claim 1, further comprising a plurality of fourth MOS transistors respectively provided between the plurality of bit lines and the plurality of second MOS transistors. 6. apparatus.   A write control unit configured to store the data in the memory cell connected to the predetermined bit line by controlling a potential of the predetermined bit line based on a determination result of the sense amplifier determining the data; 6. The ferroelectric memory device according to claim 1, further comprising a ferroelectric memory device.   7. The ferroelectric memory device according to claim 1, wherein the first sense amplifier line and the second sense amplifier line are arranged substantially at right angles to the bit line. 8. .   An electronic apparatus comprising the ferroelectric memory device according to claim 1.

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