JP2005078756A - Sense amplifier circuit, memory device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sense amplifier circuit small in circuit scale. <P>SOLUTION: This sense amplifier circuit for detecting data written in a capacitor connected electrically to the bit line between one end and the other end of the bit line is provided with: a potential control part connected electrically to one end of the bit line and attenuating a potential of the bit line when the circuit is in a floating state; and a detecting part connected electrically to one end of the bit line and detecting electric charge accumulated in the capacitor based on the potential of the bit line. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a sense amplifier circuit, a memory device, and an electronic device. In particular, the present invention relates to a sense amplifier circuit having a small circuit scale, and a memory device and an electronic device having the sense amplifier circuit.

As a conventional sense amplifier circuit, one disclosed in “IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.37, NO.11, NOVEMBER 2002, A Quasi-Matrix Ferroelectric Memory for Future Silicon Storage” (Non-patent Document 1) is there. The sense amplifier circuit disclosed in FIG. 5 of the same document includes a gain transistor, a read transistor that connects a source or drain of the gain transistor and a bit line at the time of reading, and a write transistor that connects a capacitor and the bit line at the time of writing. It is comprised.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.37, NO.11, NOVEMBER 2002, A Quasi-Matrix Ferroelectric Memory for Future Silicon Storage

  However, the conventional sense amplifier circuit disclosed in the above document requires three transistors: a gain transistor, a read transistor, and a write transistor. Therefore, there has been a problem that the circuit scale of the sense amplifier circuit becomes large. In particular, since it is necessary to provide a read transistor and a write transistor for each bit line, the influence of the read transistor and the write transistor on the circuit scale is extremely large. Further, the sense amplifier circuit further requires two control signals for controlling the read transistor and the write transistor, which causes a problem that the control circuit becomes complicated.

  Therefore, an object of the present invention is to provide a sense amplifier circuit, a memory device, and an electronic device that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

  In order to solve the above problem, according to the first aspect of the present invention, a sense for detecting data written in a capacitor electrically connected to a bit line between one end and the other end of the bit line. An amplifier circuit electrically connected to the one end of the bit line, and when the bit line is in a floating state, a potential control unit for attenuating the potential of the bit line; and the one end of the bit line There is provided a sense amplifier circuit comprising a detection unit that is electrically connected and detects the amount of charge accumulated in the capacitor based on the potential of the bit line.

  According to the above configuration, when a bit line is in a floating state, the potential of the bit line gradually attenuates with time. Therefore, by controlling the decay rate at which the potential of the bit line is attenuated, the bit line can be kept at an appropriate potential in each of the read operation and the write operation. That is, according to the above configuration, since it is not necessary to provide a read capacitor and a write capacitor, it is possible to provide a sense amplifier circuit with a very small circuit scale.

  The potential control unit is preferably a resistor having one end electrically connected to the one end of the bit line and the other end grounded. The bit line is in a floating state during a read operation for reading data written to the capacitor connected to the bit line, and the resistor writes data to the capacitor electrically connected to the bit line The bit line in the floating state is preferably configured to be grounded before the write operation is started.

  According to the above configuration, the potential of the bit line can be maintained at a potential appropriate for the read operation during the read operation and the potential of the bit line can be set to the ground potential during the write operation without providing the read transistor and the write transistor. Therefore, it is possible to provide a sense amplifier circuit with a smaller circuit scale.

  The detection unit preferably includes a transistor whose gate is electrically connected to the bit line and a current mirror circuit electrically connected to the source or drain of the transistor.

  According to a second aspect of the present invention, there is provided a memory device including the sense amplifier circuit.

  According to a third aspect of the present invention, there is provided an electronic apparatus comprising the memory device. Here, the electronic device refers to a general device having a certain function provided with the memory device according to the present invention, and the configuration thereof is not particularly limited. For example, a computer device including the memory device, a mobile phone, Any device that requires a non-volatile storage device is included, such as a PHS, PDA, electronic notebook, and IC card.

  Hereinafter, the present invention will be described through embodiments of the invention with reference to the drawings. However, the following embodiments do not limit the invention according to the claims, and are described in the embodiments. Not all combinations of features are essential for the solution of the invention.

  FIG. 1 is a diagram showing a configuration of a memory device 100 according to the first embodiment of the present invention. The memory device 100 includes a capacitor array 140 in which a plurality of capacitors 142 for accumulating charges are provided in an array, and word line control for controlling operations of writing data to the capacitor 142 and reading data written to the capacitor 142 Unit 130, main bit line control unit 122 and sub bit line control unit 124, and sense amplifier circuit 150 that detects data written in capacitor 142.

  In the present embodiment, the memory device 100 includes a main bit line MBL and a plurality of sub bit lines SBL connected to the main bit line MBL as bit lines. The capacitor 142 is electrically connected to the word line WL and the sub bit line SBL at the intersection of the word line WL and the sub bit line SBL. In the present embodiment, the memory device 100 is a ferroelectric memory device, in which the word line WL constitutes one electrode of the capacitor 142 and the sub-bit line SBL constitutes the other electrode of the capacitor 142. It has a point-type structure.

  The word line control unit 130 controls the voltage supplied to the word line WL. The main bit line control unit 122 controls the voltage supplied to the main bit line MBL. The sub bit line control unit 124 controls the selection transistor ST that switches whether the main bit line MBL and the sub bit line SBL corresponding to the main bit line MBL are conducted. That is, when the sub bit line control unit 124 turns on the selection transistor ST to make the main bit line MBL and the sub bit line SBL conductive, the potential of the sub bit line SBL is equal to the potential of the main bit line MBL. Has been.

  In the present embodiment, the word line control unit 130 and the main bit line control unit 122 supply a voltage of 0 V (volt), 1/2 VDD, or −1/2 VDD to the word line WL and the main bit line MBL, respectively. Here, VDD is a voltage for driving a peripheral circuit including the selection transistor ST. In the present embodiment, the sub bit line control unit 124 switches whether the selection transistor ST is made conductive by supplying a voltage of 0 V or VDD to the gate electrode SL of the selection transistor ST.

  The sense amplifier circuit 150 includes a resistor R, a detection transistor DT, and a current mirror circuit 152. The resistor R has one end connected to one end of the sub bit line SBL and the other end grounded. The resistor R attenuates the potential of the sub-bit line SBL when the sub-bit line SBL is in a floating state.

  The detection transistor DT has a gate electrode connected to the sub bit line SBL, a source grounded, and a drain connected to the main bit line MBL. That is, the detection transistor DT controls the amount and potential of the current flowing through the main bit line MBL in accordance with the voltage applied to the gate electrode, that is, the potential of the sub bit line SBL.

  In the current mirror circuit 152, the main bit line MBL is connected as one input, and a reference voltage is supplied as the other input. Then, a current having a predetermined current value is output from the current mirror circuit 152 in accordance with the potential of the main bit line MBL.

  FIG. 2 is a timing chart of the read operation and the write operation of the memory device 100. In FIG. 2, “selected” indicates that the capacitor 142 that reads / writes data is connected, and “non-selected” indicates that the capacitor 142 that does not read / write data is connected. It shows that. With reference to FIGS. 1 and 2, an operation in a cycle in which the memory device 100 reads data written in the capacitor 142 and an operation in a cycle in which data is written (re-) to the capacitor 142 will be described.

  First, the main bit line controller 122 precharges the potential of the selected MBL to ½ VDD by supplying ½ VDD to the selected MBL. Next, the sub bit line control unit 124 supplies VDD to the gate electrode SL of the selected ST and makes the selected ST conductive, thereby precharging the potential of the selected SBL to the same potential as the potential of the selected MBL (period I).

  Next, the sub bit line control unit 124 changes the voltage supplied to the gate electrode SL of the selected ST from VDD to 0 V, and makes the selected ST non-conductive, thereby bringing the selected SBL into a floating state. Further, the main bit line control unit 122 causes the selected MBL to be in a floating state. When the selected SBL is in a floating state, one end of the selected SBL is grounded via the resistor R, so that the potential of the selected SBL gradually attenuates over time based on the resistance value of the resistor R. (Period II). On the other hand, since one end of the selected MBL is connected to the gate of the transistor of the current mirror circuit 152 and the other end is in a floating state by the main bit line control unit 122, the potential is almost the same as that of the selected SBL. Does not decay.

  Next, the word line control unit 130 supplies −1/2 VDD to the selection WL. As a result, a potential difference of about VDD is generated between the selected WL and the selected SBL, that is, between one electrode and the other electrode of the capacitor 142. Then, since charge is supplied from the selected SBL to the capacitor 142 in accordance with the data written in the capacitor 142 (polarization direction data), it is further based on the data written in the capacitor 142 (polarization direction data). Thus, the potential of the selected SBL is attenuated (period III).

  The resistance value of the resistor R is determined according to the time during which the potential of the selected SBL should be set to the ground potential. For example, the resistance value of the resistor R is determined according to a time interval between a read cycle for reading data written to the capacitor 142 and a write cycle for writing data to the capacitor 142. Specifically, when the selected SBL is in a floating state in the read cycle, the resistance value of the resistor R is set so that the potential of the selected SBL becomes the ground potential until the next write cycle starts. Determine.

  In addition, the resistance value of the resistor R may be determined such that the potential of the selection SBL is attenuated to the ground potential during the period III, that is, while the drive voltage (−1 / 2VDD) is applied to the selection WL. Good. Further, the resistance value of the resistor R is such that the potential of the SBL is 90% to 90% of ½ VDD in the period II, that is, in the period in which the selected SBL is in a floating state and the drive voltage is not applied to the selected WL. It is preferable that the potential be set to about%.

  Since the potential of the selected SBL decreases in the period III, the potential of the selected MBL in the floating state is also attenuated in the period III based on the potential. In the period III, the current mirror circuit 152 detects (senses) the potential of the selected MBL, whereby the data written in the capacitor 142 can be determined.

  On the other hand, in the read cycle, the main bit line control unit 122 and the sub bit line control unit supply 0 V to the non-selected MBL and the non-selected SL, respectively. Since one end of the non-selected SBL is grounded via the resistor R, the potential of the non-selected SBL becomes the ground potential without conducting the selection transistor ST connected to the other end of the non-selected SBL. Further, the word line control unit 130 supplies 0 V to the non-selected WL. Therefore, in the read cycle, the potentials of the non-selected MBL, non-selected SL, non-selected WL, and non-selected SBL are all 0V. Therefore, the power consumption of the memory device 100 can be greatly reduced during the read operation.

  Next, an operation of the memory device 100 in a write cycle in which data is written again to the capacitor 142 from which data has been read will be described. By the time the write cycle starts, the potential of the selection SBL has decayed to the ground potential. Further, the potentials of the selection MBL, the selection SL, and the selection WL are 0 V before the writing cycle starts.

  The sub bit line control unit 124 supplies VDD to the selection SL and makes the selection ST conductive, thereby setting the potential of the selection SBL to the same potential as the potential of the selection MBL. Then, while the word line control unit 130 supplies 1/2 VDD to the selection WL, the main bit line control unit 122 sets the potential of the selection MBL and the selection SBL to −1/2 VDD (dotted line), thereby selecting A potential difference of VDD is provided between SBL and the selected WL, and data (polarization direction data) is written to the capacitor 142. On the other hand, when data is not written to the capacitor 142, the main bit line control unit 122 sets the potentials of the selected MBL and the selected SBL to 0 V (solid line), so that 1/2 VDD between the selected SBL and the selected WL. Thus, no data (polarization direction data) is written in the capacitor 142.

  On the other hand, in the write cycle, the main bit line control unit 122 and the sub bit line control unit supply 0 V to the non-selected MBL and the non-selected SL, respectively. Since one end of the non-selected SBL is grounded via the resistor R, the potential of the non-selected SBL becomes the ground potential without conducting the selection transistor ST connected to the other end of the non-selected SBL. Further, the word line control unit 130 supplies 0 V to the non-selected WL. Therefore, even in the write cycle, the potentials of the non-selected MBL, non-selected SL, non-selected WL, and non-selected SBL are all 0V. Therefore, even during the write operation, the power consumption of the memory device 100 can be greatly reduced.

  According to this embodiment, since the potential of the sub-bit line SBL is controlled by the resistor having one end grounded, it is not necessary to provide a write transistor and a read transistor, and the circuit scale of the sense amplifier circuit 150 can be extremely reduced. . Further, according to the present embodiment, since it is not necessary to perform complicated control during the read operation and the write operation of the memory device 100, the operation of the memory device 100 can be speeded up.

  FIG. 3 is a perspective view showing the configuration of a personal computer 1000 according to the second embodiment of the present invention. In FIG. 3, the personal computer 1000 includes a display panel 1001 and a main body 1004 provided with a keyboard 1002. As a storage medium of the main body 1004 of the personal computer 1000, a memory device including the sense amplifier circuit of the present invention is used as a non-volatile memory.

  The memory device according to the present invention is not limited to a computer device, and has low power consumption compared to conventional products and is suitable for circuit miniaturization. Therefore, the memory device is suitable as a storage device for all electronic devices mainly for portable use. .

  The examples and application examples described through the embodiments of the present invention can be used in appropriate combination according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not something. It is apparent from the description of the scope of claims that the embodiments added with such combinations or changes or improvements can be included in the technical scope of the present invention.

1 is a diagram showing a configuration of a memory device 100 according to a first embodiment of the present invention. 4 is a timing chart of a read operation and a write operation of the memory device 100. It is a perspective view which shows the structure of the personal computer 1000 which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Memory device, 122 ... Main bit line control part, 124 ... Sub bit line control part, 130 ... Word line control part, 140 ... Capacitor array, 142 ... Capacitor, 150 * ..Sense amplifier circuit, 152 ... Current mirror circuit, 1000 ... Personal computer, 1001 ... Display panel, 1002 ... Keyboard, 1004 ... Main body, DT ... Detection transistor, MBL ..Main bit line, R ... resistor, SBL ... sub bit line, SL ... gate electrode, ST ... select transistor, WL ... word line

Claims (6)

A sense amplifier circuit for detecting data written in a capacitor electrically connected to the bit line between one end and the other end of the bit line,
A potential control unit that is electrically connected to the one end of the bit line and attenuates the potential of the bit line when the bit line is in a floating state;
A detector that is electrically connected to the one end of the bit line and detects the amount of charge accumulated in the capacitor based on the potential of the bit line;
A sense amplifier circuit comprising: The sense amplifier circuit according to claim 1, wherein the potential control unit is a resistor having one end electrically connected to the one end of the bit line and the other end grounded. The bit line is in a floating state during a read operation for reading data written in the capacitor connected to the bit line,
The resistor is configured to ground the bit line in the floating state before the write operation for writing data to the capacitor electrically connected to the bit line is started. The sense amplifier circuit according to claim 2. The detector is
A transistor having a gate electrically connected to the bit line;
A current mirror circuit electrically connected to the source or drain of the transistor;
The sense amplifier circuit according to claim 2, further comprising: 5. A memory device comprising the sense amplifier circuit according to claim 1. An electronic apparatus comprising the memory device according to claim 5.