JP2008112476A - Ferroelectric memory device and drive method thereof, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric memory device securing a sufficient read margin for positive charge noise. <P>SOLUTION: The ferroelectric memory device 100 comprises: a plurality of bit lines BL1-BLn; a plurality of memory cells MC storing data; a sense amplifier 150; and a positive charge cancellation circuit 190 extracting a positive charge charged to each of the plurality of bit lines BL1-BLn. The sense amplifier 150 has: an operational amplifier 151; a MOS transistor 154; and a capacitor 160. A non-inverted input terminal of the operational amplifier is connected to the bit lines BL1-BLn; the inverted input terminal of the operational amplifier is connected to ground potential; and the output terminal of the operational amplifier is connected to the gate electrode of the MOS transistor 154. The MOS transistor 154 is connected between a node Vd and the ground potential. The capacitor 160 is connected between the node Vd and the bit lines BL1-BLn. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a ferroelectric memory device that stores data in accordance with the polarization state of a ferroelectric capacitor, a driving method thereof, and an electronic apparatus.

In a ferroelectric memory device that stores data using the hysteresis characteristics of a ferroelectric capacitor, a read voltage is applied to a plate line, and the potential of a bit line that rises in accordance with the amount of electric charge discharged from the ferroelectric capacitor. Data determination is performed by comparing the potential with the reference potential. At this time, the read voltage applied to the plate line is divided by the capacitance of the ferroelectric capacitor and the parasitic capacitance of the bit line. Therefore, the read voltage applied to the ferroelectric capacitor is smaller than the read voltage applied to the plate line. The power supply voltage tends to be set lower due to the demand for lower power consumption of electronic devices. When the power supply voltage is low, the amount of read charge discharged from the ferroelectric capacitor to the bit line is reduced, and the read margin is reduced. descend. In order to solve this problem, a bit line ground sense method is proposed in which the initial potential of the bit line is controlled to the ground potential, and the read voltage applied to the plate line is applied to the ferroelectric capacitor as it is to increase the read margin. Has been. For example, Japanese Patent Laid-Open No. 2002-133857 is known as a patent document referring to the bit line ground sense system.
JP 2002-133857 A

  However, even if the read margin is increased by applying the bit line ground sense method, the parasitic capacitance of the bit line is large with respect to the read charge amount from the ferroelectric capacitor, so that “0” data is read. There is only a slight difference between the potential rise of the bit line at this time and the potential rise when the “1” data is read. Therefore, if positive charge noise enters the bit line at the time of data reading, there is a risk of erroneous data determination.

  Accordingly, it is an object of the present invention to provide a ferroelectric memory device, a driving method thereof, and an electronic apparatus that can solve such problems and can secure a sufficient read margin against positive charge noise.

  In order to solve the above problems, a ferroelectric memory device according to the present invention is connected to a plurality of bit lines, a plurality of memory cells connected to each of the plurality of bit lines, and storing predetermined data, and the bit lines. And a positive charge cancellation circuit that extracts positive charges charged in each of the plurality of bit lines. The sense amplifier has an operational amplifier, a MOS transistor, and a capacitor. The first input portion of the operational amplifier is connected to the bit line, the second input portion of the operational amplifier is connected to the first potential, and the output portion of the operational amplifier is connected to the gate electrode of the MOS transistor. The MOS transistor is connected between the node and a second potential lower than the node potential. The capacitor is connected between the node and the bit line.

  According to such a configuration, by pulling out the positive charge charged in the bit line, a decrease in the potential of the node when “0” data is read can be suppressed, and a sufficient read margin can be secured.

  Here, the memory cell stores “0” data or “1” data corresponding to the polarization state, and the read charge amount of “0” data is smaller than the read charge amount of “1” data. The amount of charge.

  In a preferred embodiment of the present invention, the positive charge cancellation circuit is a circuit that extracts from the bit line a positive charge that is less than the read charge amount of “0” data.

  Since the positive charge noise charged on the bit line can be considered to be less than the read charge amount of “0” data, the positive charge less than the read charge amount of “0” data can be extracted from the memory cell. It is possible to suppress the potential drop of the node when “0” data is read, cancel the influence of noise, and secure a sufficient read margin.

  In another preferred embodiment of the present invention, the positive charge cancellation circuit is a circuit that extracts from the bit line a positive charge that is equal to or more than the read charge amount of “0” data and less than the read charge amount of “1” data. is there.

  The potential of the node when “1” data is read out is saturated when it is lowered to the ground potential, so that the amount of charge drawn from the bit line to secure a read margin is smaller than the read charge amount of “1” data. For example, a positive charge equal to or more than the read charge amount of “0” data and less than the read charge amount of “1” data is preferable.

As a specific circuit configuration example of the positive charge cancellation circuit, for example,
(1) a ferroelectric capacitor having a capacitance corresponding to a ferroelectric capacitor of “0” data;
(2) a paraelectric capacitor having a capacity smaller than the ferroelectric capacity of “0” data;
(3) a paraelectric capacitor having a capacitance corresponding to a capacitance smaller than the ferroelectric capacitance of “1” data;
(4) A ferroelectric capacitor having a capacitance corresponding to the ferroelectric capacitor of “0” data and a paraelectric capacitor, and the combined value of the capacitors is smaller than the ferroelectric capacitor of “1” data. A capacitor having a capacity;
Etc. can be applied.

  By using a paraelectric capacitor in addition to a ferroelectric capacitor, fine adjustment of the amount of charge drawn from the bit line is facilitated.

  As another specific circuit configuration example of the positive charge cancellation circuit, for example, a means for precharging the bit line to a predetermined negative potential or a switch for connecting the bit line to the negative potential for a predetermined time can be cited.

  By lowering the bit line to a negative potential, the positive charge noise on the bit line is canceled, and the potential drop of the node when “0” data is read is suppressed, so that a sufficient read margin can be secured.

  The positive charge cancellation circuit preferably extracts positive charges from the bit line before the read voltage is applied to the memory cell.

  If positive charges are extracted from the bit line at a timing before the read voltage is applied to the memory cell, a higher read voltage can be applied to the memory cell, so that the read speed can be improved.

  The positive charge cancellation circuit preferably extracts positive charges from the bit line at substantially the same timing as the read voltage is applied to the memory cell.

  If peripheral circuits such as a positive charge cancellation circuit are driven at the timing before the read voltage is applied to the memory cell, noise may enter the bit line, but at substantially the same time as the read voltage is applied to the memory cell. The noise margin can be expanded by driving the positive charge cancellation circuit at the timing and extracting the positive charge from the bit line.

  In a preferred embodiment of the present invention, a ferroelectric capacitor is provided in the memory cell, and one end of the ferroelectric capacitor is connected to the bit line during reading. The first potential is a ground potential, and the MOS transistor is an n-type MOS transistor.

  According to such a configuration, the bit line can be maintained substantially at the ground potential, so that a sufficient read voltage can be applied to the ferroelectric capacitor in the memory cell at the time of reading. As a result, the amount of charge taken out from the ferroelectric capacitor can be increased.

  In a preferred embodiment of the present invention, the ferroelectric memory device further includes a determination unit connected to the node.

  With this configuration, the data stored in the memory cell connected to the bit line can be determined by the determination unit.

  In a preferred embodiment of the present invention, a dummy bit line connected to a memory cell storing a charge larger than a read charge amount of “0” data and smaller than a read charge amount of “1” data, and a sense connected to the dummy bit line And a reference voltage generation unit connected to the node of the amplifier, and an output signal of the reference voltage generation unit is input to the determination unit.

  According to this configuration, the reference potential can be generated using the same sense amplifier as the sense amplifier used for reading, so that the design is easy and the reading operation is sufficiently stable with respect to fluctuations in characteristics of transistors and ferroelectrics. realizable.

  An electronic apparatus according to the present invention includes the ferroelectric memory device according to the present invention. Here, the electronic device means a general electronic device having a certain function provided with the ferroelectric memory device according to the present invention, and its configuration is not particularly limited. For example, a personal computer, a mobile phone, a PHS, etc. , PDA, electronic notebook, IC card, sheet computer, electronic paper, wearable computer, smart card, video camera, head mounted display, projector, RFID, fax machine, portable TV, sheet type calculator, etc. Including any electronic equipment that does.

  A ferroelectric memory device to which a driving method according to the present invention is applied is connected to a plurality of bit lines, a plurality of memory cells connected to each of the plurality of bit lines and storing predetermined data, and the bit lines. And a positive charge cancellation circuit that extracts positive charges charged in each of the plurality of bit lines. The sense amplifier has an operational amplifier, a MOS transistor, and a capacitor. The first input portion of the operational amplifier is connected to the bit line, the second input portion of the operational amplifier is connected to the first potential, and the output portion of the operational amplifier is connected to the gate electrode of the MOS transistor. The MOS transistor is connected between the node and a second potential lower than the node potential. The capacitor is connected between the node and the bit line.

  The driving method according to the present invention includes a step of extracting positive charges from a bit line before or substantially simultaneously with reading data stored in a memory cell, and in response to a potential increase from a predetermined potential of the bit line. A step of lowering the potential of the bit line by turning on the MOS transistor; and a step of turning off the MOS transistor in response to a potential drop from a predetermined potential of the bit line.

  According to this driving method, by pulling out the positive charge charged in the bit line, a decrease in the potential of the node when “0” data is read can be suppressed, and a sufficient read margin can be secured.

  Embodiments of the present invention will be described below with reference to the drawings. The following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention.

  FIG. 1 shows a circuit configuration of a ferroelectric memory device 100 according to this embodiment. The ferroelectric memory device 100 includes a memory cell array 110, a word line control unit 120, a plate line control unit 130, an n-type MOS transistor 140, a sense amplifier 150, a reference voltage generation unit 170, and a determination unit 180. Is provided.

  The ferroelectric memory device 100 includes m (m is a positive integer) word lines WL1 to WLm and plate lines PL1 to PLm, n (n is a positive integer) bit lines BL1 to BLn, And a dummy bit line DBL.

  Memory cell array 110 has m × (n + 1) memory cells MC (including memory cells MC connected to dummy bit line DBL) arranged in an array. The memory cell MC includes an n-type MOS transistor TR and a ferroelectric capacitor C.

  The n-type MOS transistor (n-channel MOS transistor, n-channel MISFET) TR has a gate (gate electrode) connected to one of the word lines WL1 to WLm, and a source connected to the dummy bit line DBL and the bit lines BL1 to BLn. The drain is connected to one end of the ferroelectric capacitor C. The n-type MOS transistor TR switches whether to connect one end of the ferroelectric capacitor C to the dummy bit line DBL and the bit lines BL1 to BLn based on the voltages of the word lines WL1 to WLm.

  In this specification, the source and the drain refer to one end and the other end of the MOS transistor, and these may be collectively referred to as “source / drain electrodes”.

  The ferroelectric capacitor C has the other end connected to one of the plate lines PL1 to PLm, and stores “0” data or “1” data based on a voltage difference between one end and the other end. In addition, a predetermined amount of charge is discharged to the dummy bit line DBL and the bit lines BL1 to BLn based on the stored data. In this embodiment, the ferroelectric capacitor C stores “0” when the potential at the other end is higher than the coercive voltage with respect to the potential at one end, When the voltage at the end becomes higher than the coercive voltage, “1” is stored. Here, it is assumed that the read charge amount of “0” data is smaller than the read charge amount of “1” data.

  The word line control unit 120 is connected to the word lines WL1 to WLm and controls the voltages of the respective word lines WL1 to WLm. Specifically, the word line control unit 120 sets the voltage of a predetermined word line WL among the word lines WL1 to WLm based on an address signal supplied from the outside of the ferroelectric memory device 100 to another word. The n memory cells MC connected to a predetermined word line WL are selected with a voltage higher than that of the line WL.

  The plate line control unit 130 is connected to the plate lines PL1 to PLm, and controls the voltages of the respective plate lines PL1 to PLm. Specifically, the plate line control unit 130 sets the voltage of a predetermined plate line PL among the plate lines PL1 to PLm higher than the voltages of the other plate lines PL based on the address signal, Select line PL.

  The n-type MOS transistor 140 has a source grounded (connected to the ground potential) and a drain connected to the dummy bit line DBL and the bit lines BL1 to BLn. The n-type MOS transistor 140 is supplied with a signal BLEQ at the gate, and switches whether to ground the dummy bit line DBL and the bit lines BL1 to BLn based on the voltage of the signal BLEQ.

  The sense amplifier 150 includes an operational amplifier (operational amplifier) 151, an n-type MOS transistor 154, a p-type MOS transistor (precharge unit) 158, a capacitor 160, and a positive charge cancellation circuit 190. The sense amplifier 150 is provided corresponding to each of the dummy bit line DBL and the bit lines BL1 to BLn, and determines the voltages of the dummy bit line DBL and the bit lines BL1 to BLn when data is read from the memory cell MC. Amplify and output.

  The operational amplifier 151 has its + input (in-phase input terminal, non-inverting input terminal, first input unit) connected to the dummy bit line DBL and the bit lines BL1 to BLn, and − input (reverse phase input terminal, inverting input terminal). , The second input unit) is grounded. The output is connected to the gate of the n-type MOS transistor 154. The operational amplifier 151 controls the gate voltage of the n-type MOS transistor 154 based on the voltage change of the dummy bit line DBL and the bit lines BL1 to BLn.

  The n-type MOS transistor 154 has a source grounded and a drain connected to the output (node Vd) of the sense amplifier 150. The n-type MOS transistor 154 is turned on or off based on the gate voltage, and further, when on, controls the resistance between the source and the drain based on the gate voltage.

  The p-type MOS transistor 158 is supplied at its source with the operating voltage (power supply potential, drive potential) VCC of the ferroelectric memory device, and its drain is connected to the drain of the n-type MOS transistor 154. That is, it is connected to the output (node Vd) of the sense amplifier 150. Then, the p-type MOS transistor 158 charges the drain (node Vd) of the n-type MOS transistor 154 to the voltage VCC based on the signal / PRE (inverted signal of the signal PRE) supplied to the gate.

  Capacitor 160 has one end connected to the drain of n-type MOS transistor 154 and the other end connected to dummy bit line DBL and bit lines BL1 to BLn. The capacitor 160 changes the voltages of the dummy bit line DBL and the bit lines BL1 to BLn based on the change of the drain voltage of the n-type MOS transistor 154.

  The positive charge cancellation circuit 190 is a circuit for extracting positive charges from the dummy bit line DBL and the bit lines BL1 to BLn. The charge amount extracted from the dummy bit line DBL and the bit lines BL1 to BLn may be a positive charge amount (for example, a minute charge amount corresponding to positive charge noise) smaller than the read charge amount of “0” data, or “ The positive charge amount may be equal to or more than the read charge amount of 0 ”data and less than the read charge amount of 1 data. For convenience of explanation, a paraelectric capacitor having a capacitance equivalent to the ferroelectric capacitor of “0” data will be described as an example of the positive charge cancellation circuit 190. One end of the paraelectric capacitor constituting the positive charge cancellation circuit 190 is connected to the dummy bit line DBL and the bit lines BL1 to BLn, and the other end is supplied with the signal ZCCb.

  The reference voltage generation unit 170 includes a p-type MOS transistor 172 and an n-type MOS transistor 174. The determination unit 180 includes a p-type MOS transistor 182 and an n-type MOS transistor 184. Then, the determination unit 180 determines the data stored in the memory cell MC by comparing the output (node Vd) of the sense amplifier 150 connected to the bit lines BL1 to BLn with the output of the reference voltage generation unit 170. .

  Specifically, the output (node Vd) of the sense amplifier 150, that is, the drain voltage of the n-type MOS transistor 154 is supplied to the gates of the p-type MOS transistors 172 and 182, respectively. The drain of the p-type MOS transistor 172 is connected to the drain of the n-type MOS transistor 174, and the drain of the p-type MOS transistor 182 is connected to the drain of the n-type MOS transistor 184. The gate of the n-type MOS transistor 174 is connected to its drain, and the n-type MOS transistor 184 has its gate connected to the gate and drain of the n-type MOS transistor 174, and its source is grounded. The drains are outputs OUT1 to OUTn. That is, the p-type MOS transistor 172 and the n-type MOS transistor 174 and the p-type MOS transistor 182 and the n-type MOS transistor 184 form a current mirror circuit.

  FIG. 2 is a timing chart showing the operation of the ferroelectric memory device 100. An operation of selecting the word line WL1 and the plate line PL1 and reading data stored in the memory cells MC connected to the bit lines BL1 to BLn will be described with reference to FIGS.

  In the following example, the signal potential when each signal indicates L logic is the ground potential (GND, reference potential, 0 V), and the signal potential when each signal indicates H logic is the ferroelectric memory device 100. The operating voltage is VCC, VDD, or VPP. Note that the signal potential is not limited to this, and it is sufficient that the signal voltage (potential) when H logic is indicated is higher than the signal voltage when L logic is indicated.

  First, in an initial state (time t0), the signal BLEQ indicates H logic, each n-type MOS transistor 140 is turned on, and the voltages of the dummy bit line DBL and the bit lines BL1 to BLn become the ground voltage. At time t1, the signal BLEQ becomes L logic, each n-type MOS transistor 140 is turned off, and the dummy bit line DBL and the bit lines BL1 to BLn are disconnected from the ground potential.

  In the initial state (time t0), the signal / PRE indicates L logic, the p-type MOS transistor 158 is turned on, and the drain voltage (node Vd) of the n-type MOS transistor 154 is charged to VCC. At time t1, the signal / PRE becomes H logic, the p-type MOS transistor 158 is turned off, and the drain of the n-type MOS transistor 154 is disconnected from VCC.

  Next, at time t2, the word line control unit 120 increases the voltage of the word line WL1, and turns on the n-type MOS transistor TR constituting the memory cell MC connected to the word line WL1. Thereby, the ferroelectric capacitor C constituting the memory cell MC connected to the word line WL1 is connected to the dummy bit line DBL and the bit lines BL1 to BLn.

  Next, at time t3, the sense amplifier 150 causes the signal ZCCb to fall to the L logic level. Then, the positive charge cancel circuit 190 pulls out the positive charge amount smaller than the read charge amount of the “0” data from the dummy bit line DBL and the bit lines BL1 to n, so that the potentials of the dummy bit line DBL and the bit lines BL1 to BLn are extracted. Is reduced to a negative potential. Further, at the same time t3, the plate line control unit 130 increases the voltage of the plate line PL1 to VCC. Then, a high potential is applied to the ferroelectric capacitor C constituting the memory cell MC connected to the word line WL1 with reference to the potentials of the dummy bit line DBL and the bit lines BL1 to BLn. Since charges are discharged from the ferroelectric capacitor C to the dummy bit line DBL and the bit lines BL1 to n, the potentials of the dummy bit line DBL and the bit lines BL1 to BLn are based on the potentials lowered to the negative potential. It starts to rise according to the data stored in the memory cell MC.

  FIG. 3 is a graph showing potential changes of the bit line BL, the plate line PL, and the node Vd after time t3. The horizontal axis represents time t (s) after time t3, and the vertical axis represents potential (V). BL “1” and Vd “1” indicate potential changes of the bit line BL and the node Vd when “1” data is stored in the memory cell, and BL “0” and Vd “0” The potential change of the bit line BL and the node Vd when “0” data is stored in the cell is shown.

  The potential (Vd “1”) of the node Vd when the data stored in the memory cell MC is “1” is the potential (Vd) of the node Vd when the data stored in the memory cell MC is “0”. It begins to decline more rapidly than “0”). The reason will be described below.

  When the voltage of the plate line PL1 is increased toward VCC, a read voltage less than VCC is applied to the memory cell MC due to the action of parasitic capacitance and parasitic resistance (not shown) existing on the bit line BL, and the read voltage is changed according to the read voltage. The discharged charges are released to the bit line BL.

  When the data stored in the memory cell MC is “1”, the potential of the bit line BL connected to the + input of the operational amplifier 151 rises, and the potential difference between the + input and the − input of the operational amplifier 151 is a predetermined value. When the voltage is exceeded, the output of the operational amplifier 151 rapidly becomes H level. Then, the n-type MOS transistor 154 is turned on. When n-type MOS transistor 154 is turned on, its drain is connected to the grounded source via the channel resistance (on-resistance) of n-type MOS transistor 154. As a result, the drain voltage Vd, that is, the voltage at one end of the capacitor 160 rapidly decreases.

  At this time, the capacitor 160 suppresses the voltage increase (lowers the voltage) of the other end, that is, the bit lines BL1 to BLn, based on the decrease (by coupling). When the potential of the bit line BL connected to the + input of the operational amplifier 151 falls and the potential difference from the ground potential becomes equal to or lower than a predetermined voltage, the output of the operational amplifier 151 rapidly becomes L level. As a result, the n-type MOS transistor 154 is turned off and the voltage drop of the bit line BL stops.

  As described above, when the potential of the bit line BL decreases and the voltage of the plate line PL1 increases, the high potential applied to the memory cell MC via the parasitic capacitance and parasitic resistance (not shown) existing on the bit line BL is increased. The voltage further rises, and the charge is released again from the memory cell MC to the bit line BL, and the potential of the bit line BL rises. Then, the output of the operational amplifier 151 becomes H level again, and the type MOS transistor 154 is turned on. In this way, switching of the output of the operational amplifier 151 (ON / OFF of the n-type MOS transistor 154) is repeated until a voltage of approximately VCC is applied to the memory cell MC and the discharge of charge from the memory cell MC stops. Through the above operation, the potential of the node Vd rapidly decreases.

  On the other hand, when the data stored in the memory cell MC is “0”, a positive charge amount equivalent to the read charge amount of the “0” data is previously extracted from the bit line BL by the positive charge cancel circuit 190. Therefore, the potential rise due to the charge read from the memory cell MC onto the bit line BL is negligible, and the potential of the bit line BL stops near the ground potential. Therefore, the potential difference between the potential of the bit line BL connected to the + input of the operational amplifier 151 and the ground potential connected to the − input does not exceed a predetermined voltage, and the output of the operational amplifier 151 remains at the L level. .

  As can be seen from the above description, the output switching frequency of the operational amplifier 151 varies depending on the data stored in the memory cell MC. When the data stored in the memory cell MC is “1”, since the amount of charge released from the memory cell MC is large, the output of the operational amplifier 151 is switched many times, and the potential of the bit line BL increases and decreases. Since it is repeated many times, the potential of the node Vd greatly decreases. On the other hand, when the data stored in the memory cell MC is “0”, in addition to the small amount of charge released from the memory cell MC, the positive charge amount smaller than the read charge amount of the “0” data is positive charge cancellation. Since it is previously extracted from the bit line BL by the circuit 190, the operational amplifier 151 does not operate, and the potential of the node Vd remains at VCC.

  Here, the operation of the ferroelectric memory device 100 after time t4 will be described with reference to FIGS. The ferroelectric capacitor C connected to the dummy bit line DBL is set to be larger than the area of other ferroelectric capacitors C, and “0” data is stored therein. For this reason, the amount of charge released from the ferroelectric capacitor C to the dummy bit line DBL is larger than the amount of charge released from the ferroelectric capacitor C storing “0” to the bit lines BL1 to BLn. Accordingly, the drain voltage Vd when the data stored in the memory cells MC connected to the bit lines BL1 to BLn is “0” at the gate of the p-type MOS transistor 172 of the reference voltage generator 170, and the data is A voltage between the drain voltage in the case of “1” is applied. At this time, the reference voltage generation unit 170 converts the current flowing through the p-type MOS transistor 172 into a reference voltage and supplies the reference voltage to the determination unit 180.

  Then, the determination unit 180 compares the current flowing through the p-type MOS transistor 172 and the current flowing through the p-type MOS transistor 182 to determine data stored in the memory cell MC. Specifically, when the gate voltage of the p-type MOS transistor 182 is higher than the gate voltage of the p-type MOS transistor 172, that is, the data stored in the memory cells MC connected to the bit lines BL1 to BLn is “0”. In this case, since the current flowing through the p-type MOS transistor 182 is smaller than the current flowing through the p-type MOS transistor 172, the drain voltage of the p-type MOS transistor 182 that is the output of the determination unit 180 decreases to near the ground voltage. Is “1”, the current flowing through the p-type MOS transistor 182 is larger than the current flowing through the p-type MOS transistor 172, so that the drain voltage rises to near VCC (see OUT1, time t4 to t5 in FIG. 2). .

  FIG. 4 shows a configuration example of the operational amplifier. As shown, the operational amplifier can be composed of a plurality of MOS transistors and resistors. In + is a + input, In− is a − input, and Out is an output. Vref0, Vref1, and Vref2 are reference voltages. Note that the circuit is merely an example of an operational amplifier, and is not limited to such a configuration.

  FIG. 5 shows a circuit configuration of a high-power memory device 200 as a comparative example. Devices having the same reference numerals as those shown in FIG. 1 indicate the same devices, and detailed description thereof is omitted. The difference between the ferroelectric memory device 100 according to the present embodiment and the ferroelectric memory device 200 according to the comparative example is that the ferroelectric memory device 100 has a positive charge cancel circuit 190. The ferroelectric memory device 200 does not have the positive charge cancellation circuit 190.

  FIG. 6 is a graph showing the potential change of the bit line BL and the potential change of the node Vd in the ferroelectric memory device 200. When a read voltage is applied to the memory cell MC in which “0” data is stored and charge is discharged from the memory cell MC to the bit line BL, if positive charge noise enters the bit line BL, the + input of the operational amplifier 151 In some cases, the potential of the bit line BL connected to the voltage increases, and the potential difference between the + input and the − input of the operational amplifier 151 exceeds a predetermined voltage. When the potential difference between the + input and − input of the operational amplifier 151 exceeds a predetermined voltage, the output of the operational amplifier 151 rapidly becomes H level, and the n-type MOS transistor 154 is turned on. When the n-type MOS transistor 154 is turned on, the drain thereof is connected to the grounded source via the channel resistance of the n-type MOS transistor 154, so that the potential of the node Vd drops as shown in FIG.

  In the ferroelectric memory device 200 according to the comparative example, similarly to the ferroelectric memory device 100 according to the present embodiment, the potential of the node Vd when “1” data is read is saturated when the potential drops to the ground potential. Therefore, if positive charge noise enters the bit line BL, the voltage drops to the potential of the node Vd when “0” data is read. Therefore, the potential of the node Vd when “0” data is read and “1” “There arises a problem that a difference (read margin) from the potential of the node Vd when data is read is reduced. Further, in the ferroelectric memory device 200 according to the comparative example, when the output of the operational amplifier 151 is switched from the H level to the L level, the n-type MOS transistor 154 is switched from on to off due to the limit of the response of the operational amplifier 151. Timing may be delayed. If the timing at which the n-type MOS transistor 154 switches from on to off is delayed, the potential of the node Vd when “0” data is read out decreases too much, and the potential of the node Vd when “1” data is read out. There is also a problem that the difference is reduced.

  On the other hand, in the ferroelectric memory device 100 according to the present embodiment, the positive charge amount equivalent to the read charge amount of “0” data is extracted from the bit line BL, so that “0” data is read out. The potential of the node Vd does not decrease or only slightly decreases. For this reason, even if the timing at which the n-type MOS transistor 154 switches from on to off is delayed due to the influence of positive charge noise or the response of the operational amplifier 151, the potential of the node Vd drops when "0" data is read. Therefore, a sufficient read margin can be secured.

  The examples and application examples described through the embodiments of the present invention can be used in appropriate combination according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the above-described embodiments. It is not something.

For example, the positive charge cancellation circuit 190 may have a circuit configuration as shown in FIGS.
The positive charge cancel circuit 190 shown in FIG. 7 is composed of a ferroelectric capacitor having a capacitance corresponding to the ferroelectric capacitor of “0” data.
The positive charge cancellation circuit 190 shown in FIG. 8 is formed of a paraelectric capacitor having a capacitance corresponding to a capacitance smaller than the ferroelectric capacitance of “1” data.
The positive charge cancellation circuit 190 shown in FIG. 9 includes a ferroelectric capacitor having a capacitance corresponding to the ferroelectric capacitor of “0” data and a paraelectric capacitor, and the combined value of the capacitances is “1” data. A capacitor having a capacitance smaller than that of the ferroelectric capacitor.
The positive charge cancellation circuit 190 shown in FIG. 10 precharges the potential of the bit line BL to a negative potential by connecting the bit line BL to a negative potential (for example, −0.1 V) for a sufficient time (time required for precharging). It comprises a p-type MOS transistor as precharging means.
A positive charge cancel circuit 190 shown in FIG. 11 is a p-type switch that instantaneously connects the bit line BL to a negative potential, thereby injecting negative charges into the bit line BL and instantaneously lowering the potential of the bit line BL. It consists of MOS transistors.

  In order to prevent current from flowing through the substrate when the bit line BL is precharged to a negative potential, a p-type MOS transistor is preferable as the precharge means or the transistor as the switch.

  A positive charge amount smaller than the read charge amount of “0” data (for example, a minute charge amount corresponding to positive charge noise), or equal to or more than the read charge amount of “0” data and smaller than the read charge amount of one data. By pulling out the positive charge amount from the dummy bit DBL and the bit lines BL1 to BLn, the influence of noise can be canceled, the potential drop of the node Vd when “0” data is read out, or the potential of the node Vd Even if it falls, the fall amount can be restrict | limited to a very slight range.

  Note that when the positive charge is extracted from the dummy bit DBL and the bit lines BL1 to BLn at the timing before the plate line PL is driven, any of the positive charge cancellation circuits 190 shown in FIGS. 1 and 7 to 11 can be applied. . If positive charges are extracted from the dummy bit DBL and the bit lines BL1 to BLn at a timing before the plate line is driven, a larger read voltage can be applied to the memory cell MC, so that the read speed can be improved.

  Further, when the positive charge is extracted from the dummy bit DBL and the bit lines BL1 to BLn at substantially the same timing as driving the plate line PL, any of the positive charge cancellation circuits 190 shown in FIGS. 1 and 7 to 9 is used. Is also applicable. When peripheral circuits such as the positive charge cancellation circuit 190 are driven at a timing before driving the plate line PL, noise may enter the bit line BL. However, at a timing almost simultaneously with the timing at which the plate line PL is driven. By driving the positive charge cancel circuit 190 and extracting positive charges from the dummy bit DBL and the bit lines BL1 to BLn, the noise margin can be expanded.

  In this embodiment, the area of the ferroelectric capacitor C connected to the dummy bit line DBL is increased to store “0”, but the ferroelectric capacitor C connected to the dummy bit line DBL is stored. “1” may be stored with a smaller area. Further, the area of the ferroelectric capacitor C connected to the dummy bit line DBL is made equal to the areas of the other ferroelectric capacitors C, and the driving capability of the p-type MOS transistor 172 is larger than the driving capability of the p-type MOS transistor 182. Alternatively, the driving capability of the n-type MOS transistor 174 may be made smaller than that of the n-type MOS transistor 184. Further, the source of the n-type MOS transistor 154 is grounded, and the source of the p-type MOS transistor 158 is VCC. However, the former has a low potential and the latter has a high potential, and there should be a potential difference between the former and the latter. . The p-type MOS transistor 158 may be an n-type MOS transistor as long as it has a function of precharging the node Vd.

  In this embodiment, a so-called 1T1C type memory cell has been described as an example, but the present invention may be applied to a 2T2C type memory cell.

  The examples and application examples described through the embodiments of the invention can be used in combination as appropriate according to the application, or can be used with modifications or improvements, and the present invention is limited to the description of the embodiment described above. It is not something. It will be apparent from the scope of the claims that the embodiments added with such combinations or changes or improvements can also be included in the technical scope of the present invention.

1 is a circuit configuration diagram of a ferroelectric memory device according to an embodiment. FIG. 3 is a timing chart showing the operation of the ferroelectric memory device according to the present embodiment. It is a graph which shows the electric potential change of the bit line concerning this embodiment, and the electric potential change of a node. It is a circuit block diagram of an operational amplifier. It is a circuit block diagram of the ferroelectric memory device concerning a comparative example. It is a graph which shows the potential change of the bit line concerning a comparative example, and the potential change of a node. It is a circuit block diagram of a positive charge cancellation circuit. It is a circuit block diagram of a positive charge cancellation circuit. It is a circuit block diagram of a positive charge cancellation circuit. It is a circuit block diagram of a positive charge cancellation circuit. It is a circuit block diagram of a positive charge cancellation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Ferroelectric memory device 110 ... Memory cell array 120 ... Word line control part 130 ... Plate line control part 140 ... N-type MOS transistor 150 ... Sense amplifier 160 ... Capacitor 170 ... Reference voltage generation part 180 ... Determination part 190 ... Positive charge Cancel circuit

Claims (16)

Multiple bit lines,
A plurality of memory cells connected to each of the plurality of bit lines and storing predetermined data;
A sense amplifier connected to the bit line;
A positive charge cancellation circuit for extracting a positive charge charged in each of the plurality of bit lines,
The sense amplifier includes an operational amplifier, a MOS transistor, and a capacitor.
A first input of the operational amplifier is connected to the bit line; a second input of the operational amplifier is connected to a first potential; an output of the operational amplifier is connected to a gate electrode of the MOS transistor;
The MOS transistor is connected between a node and a second potential lower than the potential of the node;
The ferroelectric memory device, wherein the capacitor is connected between the node and the bit line. The ferroelectric memory device according to claim 1, comprising:
The memory cell stores “0” data with a small read charge amount or “1” data with a large read charge amount corresponding to the polarization state,
The ferroelectric memory device, wherein the positive charge cancel circuit extracts a positive charge smaller than a read charge amount of the “0” data from the bit line. The ferroelectric memory device according to claim 1, comprising:
The memory cell stores “0” data with a small read charge amount or “1” data with a large read charge amount corresponding to the polarization state,
The ferroelectric memory device, wherein the positive charge cancellation circuit extracts from the bit line a positive charge that is equal to or greater than a read charge amount of the “0” data and less than a read charge amount of the “1” data. The ferroelectric memory device according to claim 3, comprising:
The ferroelectric memory device, wherein the positive charge cancellation circuit is a ferroelectric capacitor having a capacitance corresponding to the ferroelectric capacitance of the “0” data. The ferroelectric memory device according to claim 2, comprising:
The ferroelectric memory device, wherein the positive charge cancellation circuit is a paraelectric capacitor having a capacity smaller than the ferroelectric capacity of the “0” data. The ferroelectric memory device according to claim 3, comprising:
The ferroelectric memory device, wherein the positive charge cancellation circuit is a paraelectric capacitor having a capacity smaller than the ferroelectric capacity of the “1” data. The ferroelectric memory device according to claim 3, comprising:
The positive charge cancellation circuit includes a ferroelectric capacitor having a capacitance corresponding to a ferroelectric capacitor of “0” data and a paraelectric capacitor, and a composite value of the capacitance is a ferroelectric of “1” data. A ferroelectric memory device, which is a capacitor having a capacity smaller than a capacity. The ferroelectric memory device according to claim 1, comprising:
The ferroelectric memory device, wherein the positive charge cancellation circuit is precharge means for precharging the bit line to a predetermined negative potential. The ferroelectric memory device according to claim 1, comprising:
The ferroelectric memory device, wherein the positive charge cancellation circuit is a switch for connecting the bit line to a negative potential for a predetermined time. A ferroelectric memory device according to any one of claims 1 to 9, wherein
The ferroelectric memory device, wherein the positive charge cancel circuit extracts a positive charge from the bit line before a read voltage is applied to the memory cell. A ferroelectric memory device according to any one of claims 1 to 7, comprising:
The ferroelectric memory device, wherein the positive charge cancellation circuit extracts positive charges from the bit line at substantially the same timing as a read voltage is applied to the memory cell. A ferroelectric memory device according to any one of claims 1 to 11, wherein
A ferroelectric capacitor is provided in the memory cell,
One end of the ferroelectric capacitor is connected to the bit line at the time of reading,
The first potential is a ground potential;
The ferroelectric memory device, wherein the MOS transistor is an n-type MOS transistor. A ferroelectric memory device according to any one of claims 1 to 12, wherein
A determination unit connected to the node;
A ferroelectric memory device, wherein the determination unit determines data stored in the memory cell connected to the bit line. 14. The ferroelectric memory device according to claim 1, wherein the ferroelectric memory device is any one of claims 1 to 13.
A dummy bit line connected to a memory cell storing a charge larger than the read charge amount of the “0” data and smaller than the read charge amount of the “1” data;
A reference voltage generator connected to a node of a sense amplifier connected to the dummy bit line;
Further comprising
The ferroelectric memory device, wherein an output signal of the reference voltage generation unit is input to the determination unit.   An electronic apparatus comprising the ferroelectric memory device according to any one of claims 1 to 14. Multiple bit lines,
A plurality of memory cells connected to each of the plurality of bit lines and storing predetermined data;
A positive charge cancellation circuit for extracting a positive charge charged in each of the plurality of bit lines;
A sense amplifier connected to the bit line, a MOS transistor connected between a node and a second potential lower than the potential of the node, and a first input portion thereof connected to the bit line, Sense-up having an operational amplifier having two inputs connected to the first potential and an output connected to the gate electrode of the MOS transistor, and a capacitor connected between the node and the bit line;
A method for driving a ferroelectric memory device comprising:
Extracting positive charge from the bit line by the positive charge cancellation circuit before or substantially simultaneously with reading data stored in the memory cell to the bit line;
Lowering the potential of the bit line by turning on the MOS transistor in response to a potential increase from a predetermined potential of the bit line;
Turning off the MOS transistor in response to a potential drop from a predetermined potential of the bit line;
For driving a ferroelectric memory device.

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