JP4059675B2 - 集積回路コンポーネントのシステム - Google Patents

集積回路コンポーネントのシステム Download PDF

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Publication number
JP4059675B2
JP4059675B2 JP2002011035A JP2002011035A JP4059675B2 JP 4059675 B2 JP4059675 B2 JP 4059675B2 JP 2002011035 A JP2002011035 A JP 2002011035A JP 2002011035 A JP2002011035 A JP 2002011035A JP 4059675 B2 JP4059675 B2 JP 4059675B2
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JP
Japan
Prior art keywords
node
nodes
ram
memory
work queue
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Expired - Fee Related
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JP2002011035A
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English (en)
Japanese (ja)
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JP2002319032A5 (enExample
JP2002319032A (ja
Inventor
ダレル・エヌ・エモット
バイロン・エー・アルコーン
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HP Inc
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Hewlett Packard Co
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Publication of JP2002319032A publication Critical patent/JP2002319032A/ja
Publication of JP2002319032A5 publication Critical patent/JP2002319032A5/ja
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Publication of JP4059675B2 publication Critical patent/JP4059675B2/ja
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/509—Offload
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Image Generation (AREA)
  • Multi Processors (AREA)
JP2002011035A 2001-01-24 2002-01-21 集積回路コンポーネントのシステム Expired - Fee Related JP4059675B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/768,664 2001-01-24
US09/768,664 US6657632B2 (en) 2001-01-24 2001-01-24 Unified memory distributed across multiple nodes in a computer graphics system

Publications (3)

Publication Number Publication Date
JP2002319032A JP2002319032A (ja) 2002-10-31
JP2002319032A5 JP2002319032A5 (enExample) 2005-06-23
JP4059675B2 true JP4059675B2 (ja) 2008-03-12

Family

ID=25083144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002011035A Expired - Fee Related JP4059675B2 (ja) 2001-01-24 2002-01-21 集積回路コンポーネントのシステム

Country Status (2)

Country Link
US (3) US6657632B2 (enExample)
JP (1) JP4059675B2 (enExample)

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US6864896B2 (en) * 2001-05-15 2005-03-08 Rambus Inc. Scalable unified memory architecture
KR100441712B1 (ko) * 2001-12-29 2004-07-27 엘지전자 주식회사 확장 가능형 다중 처리 시스템 및 그의 메모리 복제 방법
CA2503611C (en) * 2002-10-31 2013-06-18 Lockheed Martin Corporation Peer-vector system utilizing a host processor and pipeline accelerator
US8749561B1 (en) 2003-03-14 2014-06-10 Nvidia Corporation Method and system for coordinated data execution using a primary graphics processor and a secondary graphics processor
US8941668B2 (en) * 2004-06-25 2015-01-27 Nvidia Corporation Method and system for a scalable discrete graphics system
US7663633B1 (en) 2004-06-25 2010-02-16 Nvidia Corporation Multiple GPU graphics system for implementing cooperative graphics instruction execution
US8446417B2 (en) 2004-06-25 2013-05-21 Nvidia Corporation Discrete graphics system unit for housing a GPU
US8411093B2 (en) * 2004-06-25 2013-04-02 Nvidia Corporation Method and system for stand alone graphics independent of computer system form factor
US9087161B1 (en) * 2004-06-28 2015-07-21 Nvidia Corporation Asymmetrical scaling multiple GPU graphics system for implementing cooperative graphics instruction execution
US7663635B2 (en) * 2005-05-27 2010-02-16 Ati Technologies, Inc. Multiple video processor unit (VPU) memory mapping
US10026140B2 (en) 2005-06-10 2018-07-17 Nvidia Corporation Using a scalable graphics system to enable a general-purpose multi-user computer system
US8893016B2 (en) * 2005-06-10 2014-11-18 Nvidia Corporation Using a graphics system to enable a multi-user computer system
US7659898B2 (en) * 2005-08-08 2010-02-09 Via Technologies, Inc. Multi-execution resource graphics processor
US8144149B2 (en) * 2005-10-14 2012-03-27 Via Technologies, Inc. System and method for dynamically load balancing multiple shader stages in a shared pool of processing units
US8775704B2 (en) 2006-04-05 2014-07-08 Nvidia Corporation Method and system for communication between a secondary processor and an auxiliary display subsystem of a notebook
GB2440758B (en) * 2006-08-08 2011-03-30 Advanced Risc Mach Ltd Interconnect logic for a data processing apparatus
JP4945485B2 (ja) * 2007-05-25 2012-06-06 株式会社リコー 画像形成装置
CN101903867B (zh) * 2007-12-17 2012-12-12 大陆-特韦斯贸易合伙股份公司及两合公司 存储器映射系统、请求控制器、多处理配置、中央中断请求控制器、用于控制存储器访问的装置、方法
US8736617B2 (en) * 2008-08-04 2014-05-27 Nvidia Corporation Hybrid graphic display
US9075559B2 (en) * 2009-02-27 2015-07-07 Nvidia Corporation Multiple graphics processing unit system and method
US9135675B2 (en) * 2009-06-15 2015-09-15 Nvidia Corporation Multiple graphics processing unit display synchronization system and method
US8766989B2 (en) * 2009-07-29 2014-07-01 Nvidia Corporation Method and system for dynamically adding and removing display modes coordinated across multiple graphics processing units
US9111325B2 (en) * 2009-12-31 2015-08-18 Nvidia Corporation Shared buffer techniques for heterogeneous hybrid graphics
US8780122B2 (en) * 2009-09-16 2014-07-15 Nvidia Corporation Techniques for transferring graphics data from system memory to a discrete GPU
CN103984669A (zh) 2013-02-07 2014-08-13 辉达公司 一种用于图像处理的系统和方法
US9818379B2 (en) 2013-08-08 2017-11-14 Nvidia Corporation Pixel data transmission over multiple pixel interfaces
CN106293496B (zh) * 2015-05-25 2019-05-31 深圳市中兴微电子技术有限公司 一种提高ram存取效率的方法及装置
GB2540227B (en) * 2015-12-21 2018-01-17 Imagination Tech Ltd Allocation of tiles to processing engines in a graphics processing system
US11225216B1 (en) 2021-01-19 2022-01-18 GM Global Technology Operations LLC Blanket airbag with integrated seat belt system
US20240202132A1 (en) * 2022-12-14 2024-06-20 Ati Technologies Ulc Multi-address space collectives engine

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JPH0731662B2 (ja) * 1986-07-15 1995-04-10 富士通株式会社 マルチプロセッサシステム
US5131080A (en) 1987-08-18 1992-07-14 Hewlett-Packard Company Graphics frame buffer with RGB pixel cache
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US5838334A (en) 1994-11-16 1998-11-17 Dye; Thomas A. Memory and graphics controller which performs pointer-based display list video refresh operations
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US6057851A (en) 1995-10-06 2000-05-02 International Business Machines Corp. Computer graphics system having efficient texture mapping with perspective correction
US5657479A (en) 1995-12-04 1997-08-12 Silicon Graphics, Inc. Hierarchical display list processing in graphics data retrieval system
US5917505A (en) 1995-12-19 1999-06-29 Cirrus Logic, Inc. Method and apparatus for prefetching a next instruction using display list processing in a graphics processor
JP3232236B2 (ja) * 1996-04-05 2001-11-26 インターナショナル・ビジネス・マシーンズ・コーポレーション グラフィック処理システム
US6125368A (en) * 1997-02-28 2000-09-26 Oracle Corporation Fault-tolerant timestamp generation for multi-node parallel databases
US5999183A (en) * 1997-07-10 1999-12-07 Silicon Engineering, Inc. Apparatus for creating a scalable graphics system with efficient memory and bandwidth usage
US6232974B1 (en) * 1997-07-30 2001-05-15 Microsoft Corporation Decision-theoretic regulation for allocating computational resources among components of multimedia content to improve fidelity
US6108007A (en) 1997-10-09 2000-08-22 Silicon Graphics, Inc. Method, system, and computer program product for increasing interpolation precision using multi-channel texture mapping
US6106468A (en) 1999-04-05 2000-08-22 Agilent Technologies, Inc. Ultrasound system employing a unified memory
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JP2002278053A (ja) * 2001-03-16 2002-09-27 Fuji Photo Film Co Ltd ポジ型フォトレジスト組成物

Also Published As

Publication number Publication date
US7009614B2 (en) 2006-03-07
US20020145609A1 (en) 2002-10-10
US20050190192A1 (en) 2005-09-01
US6919894B2 (en) 2005-07-19
US6657632B2 (en) 2003-12-02
JP2002319032A (ja) 2002-10-31
US20040021670A1 (en) 2004-02-05

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