JP4054006B2 - 低密度パリティチェック(ldpc)によるldpcデコーダコードのエンコーディング - Google Patents
低密度パリティチェック(ldpc)によるldpcデコーダコードのエンコーディング Download PDFInfo
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- JP4054006B2 JP4054006B2 JP2004197849A JP2004197849A JP4054006B2 JP 4054006 B2 JP4054006 B2 JP 4054006B2 JP 2004197849 A JP2004197849 A JP 2004197849A JP 2004197849 A JP2004197849 A JP 2004197849A JP 4054006 B2 JP4054006 B2 JP 4054006B2
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- signal
- ldpc
- receiver
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- parity check
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
Description
ここで、Bは低位三角行列である。
a00i0+a01i1+…+a0,k-1ik-1+p0=0→p0を解き、
a10i0+a11i1+…+a1,k-1ik-1+b10p0+p1=0→p1を解き、
p2,p3,…,pn-k-1に対して同様である。
エンコーディングは先の行列乗算を実行することにより達成することができる。このエンコーディングプロセスはLDPCデコーダ101に対して適用することができる。説明のために、LDPCは信頼伝搬(belief propagation)によりデコードされることを仮定する。
ここで、νiはi番目のチェックノードに接続されたエッジ数である。一般性を失うことなく、eνiは非情報ビット(パリティチェックビット)に対応するビットノードに接続されたエッジであることを仮定する。
Claims (13)
- 低密度パリティチェック(LDPC)コード化信号を受信機において発生させる方法において、
LDPCコード化信号を受信機で受信し、受信機はLDPCデコーダを含むことと、
前記LDPCデコーダにより前記LDPC信号をデコードしてデコード化信号を出力することと、
受信機により入力信号を受信することと、
前記デコーダにより前記入力信号をエンコードしてエンコード化信号を出力することとを含み、
前記エンコードすることは、
前記デコード化信号の最初のk個の情報ビットに基づいて受信ベクトルを組み立てることと、
前記受信ベクトルで前記デコーダを初期化し、前記受信ベクトルはnの長さを有し、n−kビットが論理0値またはヌル値に関係するチャネルビットの最尤比の最大値にしたがって初期化されることと、
バイナリベクトルへの硬判定を実行することによりパリティビットを計算し、バイナリベクトルを合計することとを含む方法。 - 前記入力信号が前記デコード化信号であり、前記エンコード化信号が前記受信LDPC信号との信号干渉相殺に対して使用される請求項1記載の方法。
- デコードすることとエンコードすることは同時に実行される請求項1記載の方法。
- 前記LDPC信号は衛星リンクを通して受信される請求項1記載の方法。
- 前記LDPCコード化信号は、8−PSK(位相シフトキーイング)、16−QAM(直角位相振幅変調)、16−APSK(振幅位相シフトキーイング)、32−APSKおよびQPSK(直角位相シフトキーイング)のうちの1つを含む信号配列にしたがって変調される請求項1記載の方法。
- 低密度パリティチェック(LDPC)コード化信号を受信機において発生させる命令が記録されているコンピュータ読み取り可能な媒体において、
前記命令は実行時に、1つ以上のプロセッサに請求項1記載の方法を実行させるように配列されている媒体。 - 低密度パリティチェック(LDPC)コード化信号を受信する受信機装置において、
LDPCコード化信号を受信機で受信する手段と、
前記LDPC信号をデコードしてデコード化信号を出力する手段と、
受信機により入力信号を受信する手段とを具備し、
前記デコード手段は、
前記デコード化信号の最初のk個の情報ビットに基づいて受信ベクトルを組み立てることと、
前記受信ベクトルで前記デコード手段を初期化し、前記受信ベクトルはnの長さを有し、n−kビットが論理0値またはヌル値に関係するチャネルビットの最尤比の最大値にしたがって初期化されることと、
バイナリベクトルへの硬判定を実行することによりパリティビットを計算し、バイナリベクトルを合計することとにより、
前記入力信号をエンコードして、エンコード化信号を出力する装置。 - 前記入力信号が前記デコード化信号であり、前記エンコード化信号が前記受信LDPC信号との信号干渉相殺に対して使用される請求項7記載の装置。
- 前記デコード手段はデコードとエンコードを同時に実行する請求項7記載の装置。
- 前記デコード手段は、前記デコード化信号の最初のk個の情報ビットに基づいて受信ベクトルを組み立て、前記受信ベクトルで初期化される請求項7記載の装置。
- 前記受信ベクトルはnの長さを有し、n−kビットが論理0値に関係するチャネルビットの最尤比の最大値にしたがって初期化される請求項10記載の装置。
- 前記LDPC信号は衛星リンクを通して受信される請求項7記載の装置。
- 前記LDPCコード化信号は、8−PSK(位相シフトキーイング)、16−QAM(直角位相振幅変調)、16−APSK(振幅位相シフトキーイング)、32−APSKおよびQPSK(直角位相シフトキーイング)のうちの1つを含む信号配列にしたがって変調される請求項7記載の装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48498803P | 2003-07-03 | 2003-07-03 |
Publications (2)
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JP2005051756A JP2005051756A (ja) | 2005-02-24 |
JP4054006B2 true JP4054006B2 (ja) | 2008-02-27 |
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JP2004197849A Expired - Fee Related JP4054006B2 (ja) | 2003-07-03 | 2004-07-05 | 低密度パリティチェック(ldpc)によるldpcデコーダコードのエンコーディング |
Country Status (7)
Country | Link |
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US (2) | US7430396B2 (ja) |
EP (1) | EP1494360A3 (ja) |
JP (1) | JP4054006B2 (ja) |
KR (1) | KR100634940B1 (ja) |
CN (1) | CN1578201B (ja) |
CA (1) | CA2472827C (ja) |
HK (1) | HK1072840A1 (ja) |
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KR100691303B1 (ko) | 2005-05-25 | 2007-03-12 | 한국전자통신연구원 | 위성통신시스템에서 오차에 강인한 bpsk/qpsk블라인드 변조 분류 장치 및 그 방법 |
US7844877B2 (en) | 2005-11-15 | 2010-11-30 | Ramot At Tel Aviv University Ltd. | Method and device for multi phase error-correction |
KR101208509B1 (ko) * | 2006-01-20 | 2012-12-05 | 엘지전자 주식회사 | 디지털 방송 시스템 및 처리 방법 |
KR100933139B1 (ko) * | 2006-02-22 | 2009-12-21 | 삼성전자주식회사 | 통신 시스템에서 신호 수신 장치 및 방법 |
US7934146B2 (en) * | 2006-10-18 | 2011-04-26 | Nokia Corporation | Method, apparatus and computer program product providing for data block encoding and decoding |
US20100122143A1 (en) | 2007-03-27 | 2010-05-13 | Hughes Network Systems, Llc | Method and system for providing low density parity check (ldpc) coding for scrambled coded multiple access (scma) |
US7958429B2 (en) * | 2007-07-02 | 2011-06-07 | Broadcom Corporation | Distributed processing LDPC (low density parity check) decoder |
CN100462986C (zh) * | 2007-09-13 | 2009-02-18 | 南京大学 | 基于可编程门阵列的低密度奇偶校验编解码硬件仿真系统 |
US8832518B2 (en) * | 2008-02-21 | 2014-09-09 | Ramot At Tel Aviv University Ltd. | Method and device for multi phase error-correction |
US9252813B2 (en) | 2009-05-27 | 2016-02-02 | Novelsat Ltd. | Iterative decoding of LDPC codes with iteration scheduling |
WO2011092532A1 (en) | 2010-01-28 | 2011-08-04 | Sandisk Il Ltd. | Sliding-window error correction |
US8402341B2 (en) * | 2010-02-18 | 2013-03-19 | Mustafa Eroz | Method and system for providing low density parity check (LDPC) encoding and decoding |
US8782489B2 (en) | 2010-02-18 | 2014-07-15 | Hughes Network Systems, Llc | Method and system for providing Low Density Parity Check (LDPC) encoding and decoding |
JP5648852B2 (ja) * | 2011-05-27 | 2015-01-07 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
JP5664919B2 (ja) * | 2011-06-15 | 2015-02-04 | ソニー株式会社 | データ処理装置、及び、データ処理方法 |
WO2013147776A1 (en) * | 2012-03-28 | 2013-10-03 | Intel Corporation | Conserving computing resources during error correction |
US8972834B2 (en) | 2012-08-28 | 2015-03-03 | Hughes Network Systems, Llc | System and method for communicating with low density parity check codes |
US9264182B2 (en) | 2012-09-13 | 2016-02-16 | Novelsat Ltd. | Iterative receiver loop |
US9294131B2 (en) | 2013-02-10 | 2016-03-22 | Hughes Network Systems, Llc | Apparatus and method for improved modulation and coding schemes for broadband satellite communications systems |
US9246634B2 (en) | 2013-02-10 | 2016-01-26 | Hughes Network Systems, Llc | Apparatus and method for improved modulation and coding schemes for broadband satellite communications systems |
US8887024B2 (en) | 2013-02-10 | 2014-11-11 | Hughes Network Systems, Llc | Apparatus and method for improved modulation and coding schemes for broadband satellite communications systems |
WO2014145217A1 (en) | 2013-03-15 | 2014-09-18 | Hughes Network Systems, Llc | Low density parity check (ldpc) encoding and decoding for small terminal applications |
CN111245442B (zh) | 2014-03-19 | 2023-06-30 | 三星电子株式会社 | 发送设备及其交织方法 |
US10075187B2 (en) * | 2015-03-15 | 2018-09-11 | Qualcomm Incorporated | MCS/PMI/RI selection and coding/interleaving mechanism for bursty interference and puncturing handling |
CN106997777B (zh) * | 2015-09-18 | 2021-01-05 | 爱思开海力士有限公司 | 具有改进的硬解码吞吐量的vss ldpc解码器 |
KR102616481B1 (ko) | 2016-04-04 | 2023-12-21 | 삼성전자주식회사 | 수신 장치 및 그의 신호 처리 방법 |
US11223372B2 (en) | 2019-11-27 | 2022-01-11 | Hughes Network Systems, Llc | Communication throughput despite periodic blockages |
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- 2004-07-01 US US10/883,338 patent/US7430396B2/en active Active
- 2004-07-02 EP EP04254014A patent/EP1494360A3/en not_active Ceased
- 2004-07-02 CN CN2004100552732A patent/CN1578201B/zh not_active Expired - Fee Related
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- 2004-07-02 KR KR1020040051592A patent/KR100634940B1/ko active IP Right Grant
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Publication number | Publication date |
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KR20050004121A (ko) | 2005-01-12 |
US20050003756A1 (en) | 2005-01-06 |
HK1072840A1 (en) | 2005-09-09 |
CN1578201B (zh) | 2010-05-26 |
US20080313523A1 (en) | 2008-12-18 |
CA2472827A1 (en) | 2005-01-03 |
JP2005051756A (ja) | 2005-02-24 |
US7430396B2 (en) | 2008-09-30 |
EP1494360A3 (en) | 2007-03-07 |
CN1578201A (zh) | 2005-02-09 |
EP1494360A2 (en) | 2005-01-05 |
CA2472827C (en) | 2008-04-08 |
US8326213B2 (en) | 2012-12-04 |
KR100634940B1 (ko) | 2006-10-17 |
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