JP4053228B2 - 配線縮退故障を検出するためのeccコードメカニズム - Google Patents
配線縮退故障を検出するためのeccコードメカニズム Download PDFInfo
- Publication number
- JP4053228B2 JP4053228B2 JP2000327211A JP2000327211A JP4053228B2 JP 4053228 B2 JP4053228 B2 JP 4053228B2 JP 2000327211 A JP2000327211 A JP 2000327211A JP 2000327211 A JP2000327211 A JP 2000327211A JP 4053228 B2 JP4053228 B2 JP 4053228B2
- Authority
- JP
- Japan
- Prior art keywords
- counter value
- bits
- data
- message
- ecc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1816—Testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Error Detection And Correction (AREA)
- Monitoring And Testing Of Transmission In General (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Detection And Correction Of Errors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/438063 | 1999-11-10 | ||
| US09/438,063 US6473877B1 (en) | 1999-11-10 | 1999-11-10 | ECC code mechanism to detect wire stuck-at faults |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001211085A JP2001211085A (ja) | 2001-08-03 |
| JP2001211085A5 JP2001211085A5 (enExample) | 2005-06-30 |
| JP4053228B2 true JP4053228B2 (ja) | 2008-02-27 |
Family
ID=23739054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000327211A Expired - Fee Related JP4053228B2 (ja) | 1999-11-10 | 2000-10-26 | 配線縮退故障を検出するためのeccコードメカニズム |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US6473877B1 (enExample) |
| EP (1) | EP1100205A3 (enExample) |
| JP (1) | JP4053228B2 (enExample) |
Families Citing this family (63)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6473877B1 (en) | 1999-11-10 | 2002-10-29 | Hewlett-Packard Company | ECC code mechanism to detect wire stuck-at faults |
| EP1394559A1 (de) * | 2002-08-27 | 2004-03-03 | Siemens Aktiengesellschaft | Verfahren und Anordnung zur Erkennung und Behebung von Leitungsdefekten |
| US7096414B2 (en) * | 2003-08-04 | 2006-08-22 | Hewlett-Packard Development Company, L.P. | In-line wire error correction |
| JP3935149B2 (ja) * | 2004-01-16 | 2007-06-20 | 株式会社東芝 | 半導体集積回路 |
| KR100643288B1 (ko) | 2004-11-16 | 2006-11-10 | 삼성전자주식회사 | 플래시 메모리의 데이터 처리 장치 및 방법 |
| KR100643287B1 (ko) * | 2004-11-19 | 2006-11-10 | 삼성전자주식회사 | 플래시 메모리의 데이터 처리 장치 및 방법 |
| JP4529714B2 (ja) * | 2005-02-09 | 2010-08-25 | 日本電気株式会社 | Dll回路サンプリングタイミング調整システム及びその方法並びにそれに用いる送受信装置 |
| US9288089B2 (en) | 2010-04-30 | 2016-03-15 | Ecole Polytechnique Federale De Lausanne (Epfl) | Orthogonal differential vector signaling |
| US9985634B2 (en) | 2010-05-20 | 2018-05-29 | Kandou Labs, S.A. | Data-driven voltage regulator |
| US9564994B2 (en) * | 2010-05-20 | 2017-02-07 | Kandou Labs, S.A. | Fault tolerant chip-to-chip communication with advanced voltage |
| US9077386B1 (en) | 2010-05-20 | 2015-07-07 | Kandou Labs, S.A. | Methods and systems for selection of unions of vector signaling codes for power and pin efficient chip-to-chip communication |
| US9288082B1 (en) | 2010-05-20 | 2016-03-15 | Kandou Labs, S.A. | Circuits for efficient detection of vector signaling codes for chip-to-chip communication using sums of differences |
| US9246713B2 (en) | 2010-05-20 | 2016-01-26 | Kandou Labs, S.A. | Vector signaling with reduced receiver complexity |
| US8593305B1 (en) | 2011-07-05 | 2013-11-26 | Kandou Labs, S.A. | Efficient processing and detection of balanced codes |
| US9479369B1 (en) | 2010-05-20 | 2016-10-25 | Kandou Labs, S.A. | Vector signaling codes with high pin-efficiency for chip-to-chip communication and storage |
| US9596109B2 (en) | 2010-05-20 | 2017-03-14 | Kandou Labs, S.A. | Methods and systems for high bandwidth communications interface |
| US9251873B1 (en) | 2010-05-20 | 2016-02-02 | Kandou Labs, S.A. | Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications |
| WO2011151469A1 (en) | 2010-06-04 | 2011-12-08 | Ecole Polytechnique Federale De Lausanne | Error control coding for orthogonal differential vector signaling |
| FR2964222A1 (fr) * | 2010-08-25 | 2012-03-02 | Inst Telecom Telecom Bretagne | Dispositif d'apprentissage et de decodage de messages, mettant en œuvre un reseau de neurones, procedes d'apprentissage et de decodage et programmes d'ordinateur correspondants. |
| US9268683B1 (en) | 2012-05-14 | 2016-02-23 | Kandou Labs, S.A. | Storage method and apparatus for random access memory using codeword storage |
| WO2014113727A1 (en) | 2013-01-17 | 2014-07-24 | Kandou Labs, S.A. | Methods and systems for chip-to-chip communication with reduced simultaneous switching noise |
| WO2014124450A1 (en) | 2013-02-11 | 2014-08-14 | Kandou Labs, S.A. | Methods and systems for high bandwidth chip-to-chip communications interface |
| WO2014172377A1 (en) | 2013-04-16 | 2014-10-23 | Kandou Labs, S.A. | Methods and systems for high bandwidth communications interface |
| WO2014210074A1 (en) | 2013-06-25 | 2014-12-31 | Kandou Labs SA | Vector signaling with reduced receiver complexity |
| KR102098247B1 (ko) * | 2013-11-25 | 2020-04-08 | 삼성전자 주식회사 | 메모리 시스템에서 데이터를 인코딩 및 디코딩하기 위한 방법 및 장치 |
| US9806761B1 (en) | 2014-01-31 | 2017-10-31 | Kandou Labs, S.A. | Methods and systems for reduction of nearest-neighbor crosstalk |
| JP6317474B2 (ja) | 2014-02-02 | 2018-04-25 | カンドウ ラボズ ソシエテ アノニム | 制約isi比を用いる低電力チップ間通信の方法および装置 |
| KR102240544B1 (ko) | 2014-02-28 | 2021-04-19 | 칸도우 랩스 에스에이 | 클록 임베디드 벡터 시그널링 코드 |
| US9509437B2 (en) | 2014-05-13 | 2016-11-29 | Kandou Labs, S.A. | Vector signaling code with improved noise margin |
| US9148087B1 (en) | 2014-05-16 | 2015-09-29 | Kandou Labs, S.A. | Symmetric is linear equalization circuit with increased gain |
| US9852806B2 (en) | 2014-06-20 | 2017-12-26 | Kandou Labs, S.A. | System for generating a test pattern to detect and isolate stuck faults for an interface using transition coding |
| US9112550B1 (en) | 2014-06-25 | 2015-08-18 | Kandou Labs, SA | Multilevel driver for high speed chip-to-chip communications |
| US9900186B2 (en) | 2014-07-10 | 2018-02-20 | Kandou Labs, S.A. | Vector signaling codes with increased signal to noise characteristics |
| US9432082B2 (en) | 2014-07-17 | 2016-08-30 | Kandou Labs, S.A. | Bus reversable orthogonal differential vector signaling codes |
| KR101943048B1 (ko) | 2014-07-21 | 2019-01-28 | 칸도우 랩스 에스에이 | 다분기 데이터 전송 |
| US9461862B2 (en) | 2014-08-01 | 2016-10-04 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
| US9674014B2 (en) | 2014-10-22 | 2017-06-06 | Kandou Labs, S.A. | Method and apparatus for high speed chip-to-chip communications |
| EP3700154B1 (en) | 2015-06-26 | 2024-10-02 | Kandou Labs, S.A. | High speed communications system |
| US9557760B1 (en) | 2015-10-28 | 2017-01-31 | Kandou Labs, S.A. | Enhanced phase interpolation circuit |
| US9577815B1 (en) | 2015-10-29 | 2017-02-21 | Kandou Labs, S.A. | Clock data alignment system for vector signaling code communications link |
| US10055372B2 (en) | 2015-11-25 | 2018-08-21 | Kandou Labs, S.A. | Orthogonal differential vector signaling codes with embedded clock |
| WO2017132292A1 (en) | 2016-01-25 | 2017-08-03 | Kandou Labs, S.A. | Voltage sampler driver with enhanced high-frequency gain |
| US10003454B2 (en) | 2016-04-22 | 2018-06-19 | Kandou Labs, S.A. | Sampler with low input kickback |
| CN115085727A (zh) | 2016-04-22 | 2022-09-20 | 康杜实验室公司 | 高性能锁相环 |
| US10153591B2 (en) | 2016-04-28 | 2018-12-11 | Kandou Labs, S.A. | Skew-resistant multi-wire channel |
| CN109313622B (zh) | 2016-04-28 | 2022-04-15 | 康杜实验室公司 | 用于密集路由线组的向量信令码 |
| WO2017190102A1 (en) | 2016-04-28 | 2017-11-02 | Kandou Labs, S.A. | Low power multilevel driver |
| US9906358B1 (en) | 2016-08-31 | 2018-02-27 | Kandou Labs, S.A. | Lock detector for phase lock loop |
| US10411922B2 (en) | 2016-09-16 | 2019-09-10 | Kandou Labs, S.A. | Data-driven phase detector element for phase locked loops |
| US10200188B2 (en) | 2016-10-21 | 2019-02-05 | Kandou Labs, S.A. | Quadrature and duty cycle error correction in matrix phase lock loop |
| US10372665B2 (en) | 2016-10-24 | 2019-08-06 | Kandou Labs, S.A. | Multiphase data receiver with distributed DFE |
| US10200218B2 (en) | 2016-10-24 | 2019-02-05 | Kandou Labs, S.A. | Multi-stage sampler with increased gain |
| JP2018084947A (ja) | 2016-11-24 | 2018-05-31 | ルネサスエレクトロニクス株式会社 | 入出力システム、入力装置、入出力システムの制御方法 |
| EP3610576B1 (en) | 2017-04-14 | 2022-12-28 | Kandou Labs, S.A. | Pipelined forward error correction for vector signaling code channel |
| US10116468B1 (en) | 2017-06-28 | 2018-10-30 | Kandou Labs, S.A. | Low power chip-to-chip bidirectional communications |
| US10686583B2 (en) | 2017-07-04 | 2020-06-16 | Kandou Labs, S.A. | Method for measuring and correcting multi-wire skew |
| US10693587B2 (en) | 2017-07-10 | 2020-06-23 | Kandou Labs, S.A. | Multi-wire permuted forward error correction |
| US10203226B1 (en) | 2017-08-11 | 2019-02-12 | Kandou Labs, S.A. | Phase interpolation circuit |
| US10908995B2 (en) | 2017-09-29 | 2021-02-02 | Nvidia Corporation | Securing against errors in an error correcting code (ECC) implemented in an automotive system |
| US10326623B1 (en) | 2017-12-08 | 2019-06-18 | Kandou Labs, S.A. | Methods and systems for providing multi-stage distributed decision feedback equalization |
| US10554380B2 (en) | 2018-01-26 | 2020-02-04 | Kandou Labs, S.A. | Dynamically weighted exclusive or gate having weighted output segments for phase detection and phase interpolation |
| US11356197B1 (en) | 2021-03-19 | 2022-06-07 | Kandou Labs SA | Error-tolerant forward error correction ordered set message decoder |
| CN116757158B (zh) * | 2023-08-11 | 2024-01-23 | 深圳致赢科技有限公司 | 基于半导体存储的数据管理方法 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4701909A (en) * | 1986-07-24 | 1987-10-20 | American Telephone And Telegraph Company, At&T Bell Laboratories | Collision detection technique for an optical passive star local area network using CSMA/CD |
| US4965883A (en) * | 1988-08-24 | 1990-10-23 | Digital Equipment Corporation | Method and apparatus for transmitting and receiving characters using a balanced weight error correcting code |
| DE69228108T2 (de) * | 1991-10-29 | 1999-05-20 | Nippon Hoso Kyokai, Tokio/Tokyo | Verfahren und Vorrichtung zum Empfang von Informationssignalen |
| US6170073B1 (en) * | 1996-03-29 | 2001-01-02 | Nokia Mobile Phones (Uk) Limited | Method and apparatus for error detection in digital communications |
| US5996110A (en) * | 1996-12-16 | 1999-11-30 | Motorola, Inc. | Method and apparatus for decoding a data packet |
| US6084535A (en) * | 1997-01-30 | 2000-07-04 | Mitel Semiconductor Americas Inc. | System and method for generating many ones codes with hamming distance after precoding |
| US5892464A (en) * | 1997-03-19 | 1999-04-06 | Ericsson Inc. | Message encoding technique for communication systems |
| US6473877B1 (en) | 1999-11-10 | 2002-10-29 | Hewlett-Packard Company | ECC code mechanism to detect wire stuck-at faults |
-
1999
- 1999-11-10 US US09/438,063 patent/US6473877B1/en not_active Expired - Fee Related
-
2000
- 2000-10-26 JP JP2000327211A patent/JP4053228B2/ja not_active Expired - Fee Related
- 2000-11-07 EP EP00309866A patent/EP1100205A3/en not_active Ceased
-
2002
- 2002-09-17 US US10/245,260 patent/US6910169B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP1100205A2 (en) | 2001-05-16 |
| JP2001211085A (ja) | 2001-08-03 |
| EP1100205A3 (en) | 2001-10-10 |
| US6910169B2 (en) | 2005-06-21 |
| US20030066006A1 (en) | 2003-04-03 |
| US6473877B1 (en) | 2002-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4053228B2 (ja) | 配線縮退故障を検出するためのeccコードメカニズム | |
| US7137057B2 (en) | Method and apparatus for performing error correction code (ECC) conversion | |
| US8230292B2 (en) | Method and apparatus for correcting and detecting multiple spotty-byte errors within a byte occurred in a limited number of bytes | |
| US6041430A (en) | Error detection and correction code for data and check code fields | |
| US6675349B1 (en) | Error correction coding of data blocks with included parity bits | |
| US6694478B1 (en) | Low delay channel codes for correcting bursts of lost packets | |
| US9787329B2 (en) | Efficient coding with single-error correction and double-error detection capabilities | |
| US8745461B2 (en) | Method and apparatus for N+1 packet level mesh protection | |
| US8769373B2 (en) | Method of identifying and protecting the integrity of a set of source data | |
| US20050188292A1 (en) | Method and apparatus for encoding special uncorrectable errors in an error correction code | |
| CA2493610A1 (en) | Multi-dimensional data protection and mirroring method for micro level data | |
| JPH0812612B2 (ja) | 誤り訂正方法及び装置 | |
| JPS6346615B2 (enExample) | ||
| US20050149834A1 (en) | (18, 9) Error correction code for double error correction and triple error detection | |
| US20120110409A1 (en) | Error-correcting encoding method with total parity bits, and method for detecting multiple errors | |
| CN100417071C (zh) | 一种单向广播文件传输中的前向纠错方法 | |
| US7055086B2 (en) | Method and apparatus for protecting parts of a packet in a wireless network | |
| CN109753369B (zh) | 一种寄存器及内存中顺序数组的数据编码及校验方法 | |
| Subhasri et al. | VLSI design of parity check code with hamming code for error detection and correction | |
| EP3477478B1 (en) | Memory architecture including response manager for error correction circuit | |
| Sabbry et al. | Hamming code: An analysis of its reliability and efficiency in computer networks | |
| Wolf et al. | The single burst error detection performance of binary cyclic codes | |
| US5943348A (en) | Method to check for burst limiting in error correcting systems | |
| CN120185774A (zh) | 一种数据传输方法、系统、设备、介质及计算机程序产品 | |
| Iwasaki | Analysis and proposal of signature circuits for LSI testing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041018 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20041018 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060516 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060523 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20060823 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20060828 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061121 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20061219 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20070314 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20070319 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070618 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20071106 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20071205 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101214 Year of fee payment: 3 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| LAPS | Cancellation because of no payment of annual fees |