JP4052238B2 - Package for surface mount electronic components - Google Patents

Package for surface mount electronic components Download PDF

Info

Publication number
JP4052238B2
JP4052238B2 JP2003416214A JP2003416214A JP4052238B2 JP 4052238 B2 JP4052238 B2 JP 4052238B2 JP 2003416214 A JP2003416214 A JP 2003416214A JP 2003416214 A JP2003416214 A JP 2003416214A JP 4052238 B2 JP4052238 B2 JP 4052238B2
Authority
JP
Japan
Prior art keywords
side wall
lead frame
bottom plate
semiconductor element
cut portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003416214A
Other languages
Japanese (ja)
Other versions
JP2005175354A (en
Inventor
博 中井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2003416214A priority Critical patent/JP4052238B2/en
Publication of JP2005175354A publication Critical patent/JP2005175354A/en
Application granted granted Critical
Publication of JP4052238B2 publication Critical patent/JP4052238B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は電子部品を密封収納してなる半導体装置用パッケージの構造に関するものである。   The present invention relates to a structure of a package for a semiconductor device in which electronic components are hermetically stored.

従来の表面実装型電子部品用パッケージとしては、アルミナからなる半導体容器１０２の中央部に設けられた凹部底面には、メタライズ部１０２ａが形成されている。半導体素子１０１は、メタライズ部１０２ａ上にダイボンド材１０３で固着されている。リードフレーム１０５は、一端が絶縁性樹脂１０９を介して半導体素子１０１上まで延設されている。電極部１０４とリードフレーム１０５とは、半導体素子１０１上で金属細線１０６により配線接続されている。半導体容器１０２と封止キャップ１０７とは、リードフレーム１０５を挟んで、低融点ガラスからなる封止材８で密閉封止しているものがあった（例えば、特許文献１参照）。図３は、前記特許文献１に記載された従来の表面実装型電子部品用パッケージを示すものである。   As a conventional surface mount electronic component package, a metallized portion 102a is formed on the bottom surface of a recess provided in the central portion of a semiconductor container 102 made of alumina. The semiconductor element 101 is fixed to the metallized portion 102 a with a die bond material 103. One end of the lead frame 105 extends to the semiconductor element 101 via an insulating resin 109. The electrode portion 104 and the lead frame 105 are connected by a thin metal wire 106 on the semiconductor element 101. In some cases, the semiconductor container 102 and the sealing cap 107 are hermetically sealed with a sealing material 8 made of low-melting glass with the lead frame 105 interposed therebetween (for example, see Patent Document 1). FIG. 3 shows a conventional surface-mount type electronic component package described in Patent Document 1. In FIG.

図３において、１０１は半導体素子、１０２はアルミナからなる半導体容器、１０２ａは半導体容器１０２に形成されたメタライズ部、１０３は半導体素子１０１を半導体容器１０２のメタライズ部１０２ａに固定するＡｕ−Ｓｉまたは導電性樹脂等からなるダイボンド材、１０４は半導体素子１０１の表面上に形成された電極部であり、１０５は鉄−ニッケルからなる４２アロイのリードフレームであり、１０６は電極部１０４とリードフレーム１０５とを電気的に接続するＡｌまたはＡｕ等の金属細線、１０７はアルミナからなる封止キャップとしてのセラミックキャップ、１０８は半導体容器１０２とセラミックキャップ１０７とをリードフレーム１０５を挟んで密閉するための低融点ガラスからなる封止材であり、１０９は半導体素子１０１の表面上にまで延設されたリードフレーム１０５と半導体素子１０１表面との間に設けられた絶縁体としての絶縁性樹脂である。   In FIG. 3, 101 is a semiconductor element, 102 is a semiconductor container made of alumina, 102 a is a metallized portion formed in the semiconductor container 102, and 103 is Au—Si or conductive material that fixes the semiconductor element 101 to the metallized part 102 a of the semiconductor container 102. A die bond material made of a conductive resin, 104 is an electrode portion formed on the surface of the semiconductor element 101, 105 is a 42 alloy lead frame made of iron-nickel, and 106 is an electrode portion 104 and a lead frame 105. A thin metal wire such as Al or Au for electrically connecting the electrodes, 107 a ceramic cap as a sealing cap made of alumina, and 108 a low melting point for sealing the semiconductor container 102 and the ceramic cap 107 with the lead frame 105 interposed therebetween. A sealing material made of glass, and 109 is a semiconductor element. Until on the 101 surface of an insulating resin as an insulator provided between the extending leadframe 105 and the semiconductor element 101 surface.

ダイボンド材１０３により半導体容器１０２のメタライズ部１０２ａに固着された半導体素子１０１の表面に、絶縁性樹脂１０９を一定幅で塗布形成し、絶縁性樹脂１０９上にリードフレーム１０５を配置する。そこで、熱処置を施し、絶縁性樹脂１０９によりリードフレーム１０５を半導体素子１０１上に絶縁固着し、リードフレーム１０５を半導体素子１０１表面上まで延設し、半導体素子１０１の表面上領域で電極部１０４とリードフレーム１０５とを金属細線１０６で配線接続する配線領域の小型化を図ることで、半導体パッケージおよび半導体装置を小型化していた。
特開平０５−１６０３２８号公報 An insulating resin 109 is applied and formed with a certain width on the surface of the semiconductor element 101 fixed to the metallized portion 102 a of the semiconductor container 102 by the die bond material 103, and the lead frame 105 is disposed on the insulating resin 109. Therefore, heat treatment is performed, the lead frame 105 is insulated and fixed on the semiconductor element 101 by the insulating resin 109, the lead frame 105 is extended to the surface of the semiconductor element 101, and the electrode portion 104 is formed in the region on the surface of the semiconductor element 101. The semiconductor package and the semiconductor device have been miniaturized by reducing the size of the wiring region in which the lead frame 105 and the lead frame 105 are connected by the thin metal wire 106.
JP 05-160328 A

しかしながら、前記従来の構成では、リードフレーム１０５と半導体素子１０１が絶縁性樹脂１０９を介して絶縁固着する構成となり、半導体装置を回路基板に実装する際の衝撃や回路基板たわみなどによる機械的な力がリードフレーム１０５に加わると半導体素子１０１にクラックなどが発生する。また、鉄−ニッケル合金の４２アロイからなるリードフレーム１０５とアルミナからなる半導体容器１０２とは熱膨張係数が異なり、半導体装置を回路基板に実装するなどの際に加わる熱で相反する力が働くという問題があり、半導体素子１０１にクラックなどが発生したり、その歪みにより半導体素子１０１の電気特性の低下を招くという課題を有していた。   However, in the conventional configuration, the lead frame 105 and the semiconductor element 101 are insulatively fixed via the insulating resin 109, and mechanical force due to impact or deflection of the circuit substrate when the semiconductor device is mounted on the circuit substrate. Is applied to the lead frame 105, a crack or the like occurs in the semiconductor element 101. Further, the lead frame 105 made of 42 alloy of iron-nickel alloy and the semiconductor container 102 made of alumina have different coefficients of thermal expansion, and conflicting forces are exerted by heat applied when a semiconductor device is mounted on a circuit board. There is a problem, and there is a problem that a crack or the like occurs in the semiconductor element 101 or the electrical characteristics of the semiconductor element 101 are deteriorated due to the distortion.

本発明は、前記従来の課題を解決するもので、リードフレーム１０５に加わる機械的な力や半導体装置に加わる熱の影響による特性低下を抑えた表面実装型電子部品用パッケージを提供することを目的とする。   SUMMARY OF THE INVENTION The present invention solves the above-described conventional problems, and an object thereof is to provide a surface mount electronic component package that suppresses deterioration in characteristics due to the mechanical force applied to the lead frame 105 and the effect of heat applied to the semiconductor device. And

前記従来の課題を解決するために、本発明の表面実装型電子部品用パッケージは、底板と、少なくとも一箇所に切込み部を有する側壁と、切込み部に挿通された接続端子と、蓋体とからなり、底板の主面周縁に側壁が接合され、底板と、側壁と、接続端子とが切込み部で封止用ガラスにより封止されてなる基体の、内側に位置する接続端子の終端の幅が切込み部の間口よりも広いことを特徴とする。






In order to solve the above-described conventional problems, a surface mount electronic component package according to the present invention includes a bottom plate, a side wall having a cut portion at at least one place, a connection terminal inserted through the cut portion, and a lid. The width of the terminal end of the connection terminal located on the inner side of the base body in which the side wall is joined to the peripheral edge of the main surface of the bottom plate, and the bottom plate, the side wall, and the connection terminal are sealed with the sealing glass at the cut portion Is wider than the entrance of the notch .






本構成によって、リードフレームに加わる機械的な力や構成材料の熱膨張係数の差から生じる相反する力が半導体素子に直接伝搬することがなく、さらに、封止用ガラスによる封着部の貫通孔よりも大きな終端を持ったリードフレームを装着することができる。   With this configuration, the mechanical force applied to the lead frame and the conflicting force generated by the difference in the thermal expansion coefficients of the constituent materials are not directly propagated to the semiconductor element, and the sealing glass through-hole is further sealed. A lead frame having a larger end can be attached.

以上のように、本発明の表面実装型電子部品用パッケージによれば、リードフレームに加わる機械的な力や構成材料の相違による熱膨張差による相反する力が半導体素子に直接伝搬することがない。さらに、封止用ガラスによる封着部の貫通孔よりも大きな終端を持ったリードフレームを装着することができる。   As described above, according to the surface mount electronic component package of the present invention, the opposing force due to the difference in thermal expansion due to the mechanical force applied to the lead frame or the difference in the constituent materials does not propagate directly to the semiconductor element. . Furthermore, it is possible to mount a lead frame having a larger end than the through-hole of the sealing portion made of sealing glass.

以下本発明の実施の形態について、図面を参照しながら説明する。    Embodiments of the present invention will be described below with reference to the drawings.

（実施の形態１）
図１（ａ）は、本発明の実施の形態１における表面実装型電子部品用パッケージの斜視図であり、図１（ｂ）は図１（ａ）のＸ−Ｘ’線に沿った断面図である。 (Embodiment 1)
FIG. 1A is a perspective view of a surface mount electronic component package according to Embodiment 1 of the present invention, and FIG. 1B is a cross-sectional view taken along the line XX ′ of FIG. It is.

図１（ａ）、図１（ｂ） において、１は半導体素子、２は底板、３は側壁、４はダイボンド材、５は接続端子として例えばリードフレーム、６は金属細線、７は蓋体、８は封止材、９は封止用ガラスである。   1 (a) and 1 (b), 1 is a semiconductor element, 2 is a bottom plate, 3 is a side wall, 4 is a die bond material, 5 is a connection terminal such as a lead frame, 6 is a thin metal wire, 7 is a lid, 8 is a sealing material, 9 is glass for sealing.

詳細な構成を下記に説明する。半導体素子１は本実施の形態による中空内部を有する表面実装型電子部品用パッケージに収納される。特に外部環境からの保護を必要とする半導体素子１の収納に適する。底板２はコバールや４２アロイなどからなり、主面１０の周縁にコバールや４２アロイなどからなる少なくとも１箇所に切込み部１１を有した側壁３に金錫合金や銀銅合金などからなる封止材８により固着されている。切込み部１１にリードフレーム５が挿通され、封止用ガラス９により底板２および側壁３ならびにリードフレーム５が封着され基体１２が形成される。基体１２の開放口側に金錫合金や樹脂などからなる接着材８により蓋体７が封止され表面実装型電子部品用パッケージを構成している。これによれば、半導体装置を回路基板に実装する際の衝撃や回路基板たわみなどによりリードフレーム５に加わる機械的な力が半導体素子１に直接伝搬することがない。さらに、底板２と側壁３とを別体に構成することで、例えば、底板２を薄く、側壁３を厚くする構成をとることも可能であり、これによれば、底板２と側壁３ならびに側壁３とリードフレーム５との接着面積を大きく確保でき、且つ低背化に有利となる。   A detailed configuration will be described below. The semiconductor element 1 is housed in a surface mount electronic component package having a hollow interior according to the present embodiment. It is particularly suitable for housing the semiconductor element 1 that requires protection from the external environment. The bottom plate 2 is made of Kovar, 42 alloy or the like, and a sealing material made of gold-tin alloy, silver-copper alloy or the like on the side wall 3 having a cut portion 11 in at least one place made of Kovar, 42 alloy or the like on the periphery of the main surface 10. 8 is fixed. The lead frame 5 is inserted into the cut portion 11, and the base plate 2, the side wall 3, and the lead frame 5 are sealed by the sealing glass 9 to form the base 12. A lid 7 is sealed on the opening side of the base 12 with an adhesive 8 made of a gold-tin alloy, resin, or the like to constitute a surface mount electronic component package. According to this, the mechanical force applied to the lead frame 5 due to impact or deflection of the circuit board when the semiconductor device is mounted on the circuit board does not directly propagate to the semiconductor element 1. Further, by configuring the bottom plate 2 and the side wall 3 separately, for example, it is possible to adopt a configuration in which the bottom plate 2 is thin and the side wall 3 is thick. A large bonding area between the lead frame 5 and the lead frame 5 can be secured, and this is advantageous in reducing the height.

（実施の形態２）
図２は、本発明の実施の形態２における表面実装型電子部品用パッケージの工程フローに沿った斜視図である。 (Embodiment 2)
FIG. 2 is a perspective view along the process flow of the surface mount electronic component package according to the second embodiment of the present invention.

図２において、１は半導体素子、２は底板、３は側壁、４はダイボンド材、５はリードフレーム、６は金属細線、７は蓋体、８は封止材、９は封止用ガラスである。   In FIG. 2, 1 is a semiconductor element, 2 is a bottom plate, 3 is a side wall, 4 is a die bond material, 5 is a lead frame, 6 is a thin metal wire, 7 is a lid, 8 is a sealing material, and 9 is a sealing glass. is there.

詳細な構成を下記に説明する。コバールや４２アロイなどからなる切込み部１１を有した側壁３の切込み部１１にリードフレーム５を挿通し、コバールや４２アロイなどからなる底板２の主面１０の周縁に金錫合金や銀銅合金などからなる封止材８例えば銀銅合金を用いた場合、還元雰囲気で８００℃から８５０℃加熱し固着する（図２（ａ））。これによれば、切込み部１１の切込み形状よりも大きな終端を持ったリードフレーム５を装着することができる。次に切込み部１１に封止用ガラス９を装填し窒素雰囲気で９００℃から１０００℃加熱し、底板２および側壁３ならびにリードフレーム５を封着する（図２（ｂ））。これにより、基体１２が形成される。次に底板２の主面１０の所定位置に金錫合金や金シリカ合金などからなるダイボンド材４を介して半導体素子１を搭載する（図２（ｃ））。次に半導体素子１とリードフレーム５とを金やアルミニュウムなどからなる金属細線６により導通接続する（図２（ｄ））。次に基体１２の開放口側に金錫合金や樹脂などからなる封止材８を介して蓋体７を封止する（図２（ｅ））。これにより表面実装型電子部品用パッケージを構成している。これによれば、リードフレーム５を挿通する貫通孔を、底板２の主面１０と側壁３とを封止材８を介して接着する構成にすることにより、切込み部１１の切込み形状よりも大きな終端を持ったリードフレーム５を装着することができる。さらに、リードフレーム５の終端形状に制限がなく用途に応じた形状とすることが可能である。   A detailed configuration will be described below. The lead frame 5 is inserted into the cut portion 11 of the side wall 3 having the cut portion 11 made of Kovar, 42 alloy or the like, and a gold-tin alloy or silver-copper alloy is formed on the periphery of the main surface 10 of the bottom plate 2 made of Kovar, 42 alloy or the like. When a sealing material 8 such as a silver-copper alloy is used, it is fixed by heating at 800 to 850 ° C. in a reducing atmosphere (FIG. 2A). According to this, the lead frame 5 having a larger end than the cut shape of the cut portion 11 can be mounted. Next, the sealing glass 9 is loaded into the cut portion 11 and heated at 900 ° C. to 1000 ° C. in a nitrogen atmosphere to seal the bottom plate 2, the side wall 3 and the lead frame 5 (FIG. 2B). Thereby, the base 12 is formed. Next, the semiconductor element 1 is mounted on a predetermined position of the main surface 10 of the bottom plate 2 through a die bond material 4 made of a gold-tin alloy or a gold-silica alloy (FIG. 2C). Next, the semiconductor element 1 and the lead frame 5 are conductively connected by a thin metal wire 6 made of gold or aluminum (FIG. 2D). Next, the lid body 7 is sealed on the opening 12 side of the base 12 through a sealing material 8 made of gold-tin alloy or resin (FIG. 2E). Thus, a surface mount electronic component package is configured. According to this, the through hole through which the lead frame 5 is inserted has a configuration in which the main surface 10 and the side wall 3 of the bottom plate 2 are bonded via the sealing material 8, so that it is larger than the cut shape of the cut portion 11. A lead frame 5 having a terminal end can be attached. Furthermore, there is no restriction | limiting in the termination | terminus shape of the lead frame 5, It can be set as the shape according to a use.

なお、本実施の形態において、リードフレームを用いて説明したが、リード線などを用いても良い。   In the present embodiment, the lead frame is used for description, but a lead wire or the like may be used.

電子部品を密封収納してなる半導体装置用パッケージとして有用であり、特に高気密性が要求される高信頼のパッケージに適する。   It is useful as a package for a semiconductor device in which electronic components are hermetically stored, and is particularly suitable for a highly reliable package that requires high airtightness.

本発明の実施の形態１における、（ａ）は表面実装型電子部品用パッケージの斜視図、（ｂ）は（ａ）のＸ−Ｘ’線に沿った断面図In Embodiment 1 of the present invention, (a) is a perspective view of a surface mount electronic component package, (b) is a cross-sectional view taken along line X-X 'of (a). 本発明の実施の形態２における表面実装型電子部品用パッケージの工程フローに沿った斜視図The perspective view along the process flow of the package for surface mount type electronic components in Embodiment 2 of this invention 従来の表面実装型電子部品用パッケージ断面図Cross-sectional view of a conventional surface mount electronic component package

符号の説明Explanation of symbols

１ 半導体素子
２ 底板
３ 側壁
４ ダイボンド材
５ リードフレーム
６ 金属細線
７ 蓋体
８ 封止材
９ 封止用ガラス
１０ 主面
１１ 切込み部
１２ 基体
１０１ 半導体素子
１０２ 半導体容器
１０３ ダイボンド材
１０６ 金属細線
１０７ 封止キャップ
１０８ 封止材 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Bottom plate 3 Side wall 4 Die bond material 5 Lead frame 6 Metal thin wire 7 Lid body 8 Sealing material 9 Sealing glass 10 Main surface 11 Cutting part 12 Base 101 Semiconductor element 102 Semiconductor container 103 Die bond material 106 Metal thin wire 107 Sealing Stop cap 108 Sealing material

Claims (2)

底板と、少なくとも一箇所に切込み部を有する側壁と、前記切込み部に挿通された接続端子と、蓋体とからなり、前記底板の主面周縁に前記側壁が接合され、前記底板と、前記側壁と、前記接続端子とが前記切込み部で封止用ガラスにより封止されてなる基体の、内側に位置する前記接続端子の終端の幅が前記切込み部の間口よりも広いことを特徴とする表面実装型電子部品用パッケージ。 A bottom plate, a side wall having a cut portion at at least one place, a connection terminal inserted through the cut portion, and a lid, the side wall being joined to a peripheral edge of a main surface of the bottom plate, the bottom plate, and the side wall And a surface of the base body, in which the connection terminal is sealed with a sealing glass at the cut portion, and the width of the terminal end of the connection terminal located inside is wider than the opening of the cut portion. Package for mounted electronic components. 少なくとも一箇所に切込み部を有した側壁の切込み部に該切込みの間口よりも幅が広い終端を有する接続端子を挿通する工程と、底板の主面周縁に前記側壁を接合する工程と、前記切込み部に封止用ガラスを装填し前記底板および前記側壁ならびに前記接続端子を封止する工程と、前記側壁の開放口に蓋体を封止する工程を有することを特徴とする表面実装型電子部品用パッケージの製造方法。 A step of inserting a connection terminal having an end wider than the front end of the cut into the cut portion of the side wall having a cut portion in at least one place, a step of joining the side wall to the peripheral edge of the main surface of the bottom plate, and the cut A surface-mount type electronic component comprising: a step of filling a sealing glass in a portion to seal the bottom plate, the side wall, and the connection terminal; and a step of sealing a lid to an opening of the side wall Package manufacturing method.
JP2003416214A 2003-12-15 2003-12-15 Package for surface mount electronic components Expired - Fee Related JP4052238B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003416214A JP4052238B2 (en) 2003-12-15 2003-12-15 Package for surface mount electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003416214A JP4052238B2 (en) 2003-12-15 2003-12-15 Package for surface mount electronic components

Publications (2)

Publication Number Publication Date
JP2005175354A JP2005175354A (en) 2005-06-30
JP4052238B2 true JP4052238B2 (en) 2008-02-27

Family

ID=34735464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003416214A Expired - Fee Related JP4052238B2 (en) 2003-12-15 2003-12-15 Package for surface mount electronic components

Country Status (1)

Country Link
JP (1) JP4052238B2 (en)

Also Published As

Publication number Publication date
JP2005175354A (en) 2005-06-30

Similar Documents

Publication Publication Date Title
JP2001196488A (en) Electronic component device and manufacturing method thereof
JP2009232150A (en) Piezoelectric device, and method of manufacturing piezoelectric device
JP2002110833A (en) Semiconductor device and method of manufacturing the same
US8476755B2 (en) High frequency ceramic package and fabrication method for the same
JP4052238B2 (en) Package for surface mount electronic components
JP2007095956A (en) Package for housing electronic component
JP2020120195A (en) MEMS oscillator
JP2006033413A (en) Piezoelectric vibration device
JP4144036B2 (en) Electronic component package and piezoelectric vibration device using the electronic component package
JP2007324957A (en) Piezoelectric vibrator
JP2962939B2 (en) Package for storing semiconductor elements
JP2870501B2 (en) Semiconductor device
JP3527902B2 (en) Semiconductor element storage package and semiconductor device
JP2728585B2 (en) Package for storing semiconductor elements
JP6849558B2 (en) Electronic component storage packages and electronic devices
JPH11163184A (en) Optical semiconductor device housing package
JP3051225B2 (en) Package for integrated circuit
JP2003297453A (en) Surface-mounted gastight terminal and crystal resonator using the same
JP2002305262A (en) Package for packaging semiconductor device
JP2005317599A (en) Substrate for mounting electronic component and electronic device
JP4753539B2 (en) Electronic component mounting substrate and electronic device using the same
JPS6043660B2 (en) semiconductor equipment
JP4290833B2 (en) Package for storing semiconductor elements
JP2021101457A (en) Ceramic circuit board and electronic apparatus
JP2006238242A (en) Piezoelectric apparatus

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051215

RD01 Notification of change of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7421

Effective date: 20060112

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070803

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070821

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071005

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071113

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071126

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101214

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101214

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101214

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111214

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111214

Year of fee payment: 4

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121214

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees