JP4048527B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention can be expected stable operation relates to an effective method for manufacturing a highly reliable semiconductor element.
[0002]
[Prior art]
In general, when an LSI equipped with a logic circuit or a memory circuit is manufactured, the rate at which inter-element current leakage occurs or an element that does not operate stably such as including an element with a defective transistor operation is manufactured is quite high.
[0003]
In order to reduce such a defect rate, there is no solution that should be taken care of, and it is important to make detailed countermeasures one by one, for example, between the source and drain and the gate. One of the problems is that current leakage and current leakage generated between the source and drain and the substrate must be reduced.
[0004]
4 and 5 are fragmentary cutaway side views showing a semiconductor element at a process point for explaining a process of manufacturing a conventional semiconductor element. Hereinafter, the manufacturing process will be described with reference to these drawings. explain. Here, for the sake of simplicity, structures other than the main structure for explaining the prior art, such as a gate insulating film, a source region and a drain region formed by doping impurities, are omitted.
[0005]
Refer to FIG. 4A (1)
By applying a normal technique, an element isolation region 2 made of STI (shallow trench isolation) is formed on the Si substrate 1.
[0006]
(2)
By applying a normal technique, the Si gate electrode 3 is formed, and the side wall 4 covering the side surface is formed.
[0007]
Refer to FIG. 4B (3)
By applying the sputtering method, the Co film 5 is formed and then a primary heat treatment is performed to form a CoSi compound film on the exposed Si surface.
[0008]
Refer to FIG. 5A (4)
The Co film that has not reacted with Si is removed.
[0009]
Refer to FIG. 5B (5)
Second heat treatment to be performed CoSi compound source electrode 5S made of CoSi _2, the drain electrode 5D, a gate electrode 5G.
[0010]
In the semiconductor element manufactured by the above manufacturing process, for example, a leakage current is generated between the element isolation region 2 and the gate electrode 5G at the contact point indicated by the symbols A ₁ and A ₂ for the drain electrode 5D. There is a problem of flowing.
[0011]
[Problems to be solved by the invention]
In the present invention, when a semiconductor element is manufactured, a manufacturing process in which simple modifications are made to the shapes of the source electrode and the drain electrode is added to obtain a semiconductor element that operates stably and has high reliability.
[0012]
[Means for Solving the Problems]
In the method of manufacturing a semiconductor element according to the present invention includes the steps of forming a transition metal layer on a substrate that Si surface is exposed to the source electrode formation region and a drain electrode forming region, then the Performing a silicidation process on the transition metal film to form a source electrode and a drain electrode; and then performing a thinning process on the source electrode and the drain electrode so that the edges of the source electrode and the drain electrode are separated from the element isolation region and at least And a step of separating from a gate having a gate electrode whose side surface is covered with an insulating film .
[0013]
By adopting the above means, current leakage that occurs between the source and drain electrodes and the element isolation region or between the source and drain electrodes and the gate electrode can be suppressed, and normal transistor operation is achieved. Thus, a semiconductor element capable of performing the above can be manufactured with a high manufacturing yield.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1
FIG. 1 and FIG. 2 are side sectional views showing a main part of the semiconductor element at the main points for explaining the first embodiment. Hereinafter, explanation will be given with reference to these drawings. The steps until the Co film is formed on the entire surface are the same as those in the conventional technique described with reference to FIGS.
[0015]
See FIG. 1A (1)
Although the Co film 15 is formed on the entire surface by applying the sputtering method, the film thickness needs to be particularly thick, for example, about 1.5 times the thickness of the conventional example described above. Therefore, it is preferable to set the thickness to about 15 [nm].
[0016]
Here, 11 denotes a Si substrate, 12 denotes an element isolation region made of STI embedded with SiO ₂ , 13 denotes a Si gate electrode, and 14 denotes a side wall made of SiO ₂ .
[0017]
Refer to FIG. 1 (B) (2)
A primary heat treatment is performed at a temperature of 500 [° C.] for a time of 30 [seconds] to react the Co film 15 and the exposed Si to form a CoSi compound film (monosilicidation process).
[0018]
(3)
By applying a wet etching method using ammonia + hydrogen peroxide + water or sulfuric acid + hydrogen peroxide + water as an etchant, the unreacted portion of the Co film 15 is removed.
[0019]
The CoSi compound film becomes a pattern of the source electrode 15S, the drain electrode 15D, and the gate electrode 15G, though not completely yet through the process of removing the unreacted portion.
[0020]
Refer to FIG. 2 (A) (4)
By applying a dry etching method using Ar ions, uniform ion etching is performed to thin the source electrode 15S, the drain electrode 15D, and the gate electrode 15G made of a CoSi compound (thinning process).
[0021]
Through this process, the source electrode 15S, the drain electrode 15D, and the gate electrode 15G are not only thinned but also narrowed as a planar pattern. Therefore, the source electrode 15S and the drain electrode 15D are reduced. Are separated from the element isolation region 12 and the side wall 14 to generate a gap.
[0022]
Refer to FIG. 2 (B) (5)
A secondary heat treatment is performed at a temperature of 800 ° C. for a time of 2 minutes, and the CoSi compound constituting the source electrode 15S, the drain electrode 15D, and the gate electrode 15G is changed to CoSi ₂ to complete (large silicidation). processing).
[0023]
100 sample elements were manufactured by taking the steps of the first embodiment described above, and when the defective elements were inspected, the number was 0, but 100 sample elements were obtained by the conventional technique described with reference to FIGS. 4 and 5. When it was fabricated and the defective element was inspected, it was one.
[0024]
In the first embodiment, the source electrode 15S, the drain electrode 15D, and the gate electrode 15G are thinned by applying a dry etching method using Ar ions. For this, another method is used. Can do. Further, depending on the electrode material, there is a case where the monosilicidation process is not necessary, and in this case, only the large silicidation process is required, and the process is performed before the thinning process.
[0025]
Embodiment 2
When the second embodiment is compared with the first embodiment, only the method of thinning the source electrode 15S, the drain electrode 15D, and the gate electrode 15G is different, and the process will be described mainly.
[0026]
In the first embodiment, after the step (2) described with reference to FIG. 1B is completed, as shown in FIG. 3, a nitric acid-based mixed solution (nitric acid + hydrofluoric acid, 0. The source electrode 15S, the drain electrode 15D, and the gate electrode 15G made of a CoSi compound are thinned by immersing the whole in a container 16 filled with 5 [%]).
[0027]
Through this process, the source electrode 15S, the drain electrode 15D, and the gate electrode 15G are not only thinned but also narrowed as a planar pattern as in the first embodiment. The source electrode 15S and the drain electrode 15D are separated from the element isolation region 12 or the side wall 14, and a gap is generated between them.
[0028]
When 100 sample elements were produced by taking the steps of the second embodiment described above and the defective elements were inspected, the number was 0 as in the first embodiment.
[0029]
In each of the above embodiments, Co was used to form an electrode made of CoSi ₂ , but Co was replaced with Ni or Ti, and the present invention was carried out. As well as good results.
[0030]
Here, an outline of the case where Co is replaced with Ni will be described. In this case, it is easy to understand with reference to FIG. 1 and FIG. 2 describing the first embodiment.
(1)
Instead of the Co film, a Ni film having a thickness of about 15 nm is formed on the entire surface.
(2)
Heat treatment is performed at a temperature of 400 [° C.] for a time of 30 [seconds].
By this heat treatment, a monosilicide film made of NiSi is obtained.
(3)
As in the case of the Co film, unnecessary portions are removed by etching.
(4)
As in the first embodiment, uniform ion etching using Ar ions is performed to thin the source electrode, drain electrode, and gate electrode made of a NiSi compound (thinning process).
(5)
Thereafter, it is completed through the same process as in the first embodiment.
[0031]
【The invention's effect】
In the method of manufacturing a semiconductor element according to the present invention includes the steps of forming a transition metal layer on a substrate that Si surface is exposed to the source electrode formation region and a drain electrode forming region, then the Performing a silicidation process on the transition metal film to form a source electrode and a drain electrode; and then performing a thinning process on the source electrode and the drain electrode so that the edges of the source electrode and the drain electrode are separated from the element isolation region and at least And a step of separating from a gate having a gate electrode whose side surface is covered with an insulating film.
[0032]
By adopting the above configuration, current leakage that occurs between the source and drain electrodes and the element isolation region or between the source and drain electrodes and the gate electrode can be suppressed, and normal transistor operation is achieved. Thus, a semiconductor element capable of performing the above can be manufactured with a high manufacturing yield.
[Brief description of the drawings]
FIG. 1 is a cutaway side view showing a main part of a semiconductor element in a process key point for explaining a first embodiment;
FIG. 2 is a cutaway side view of a main part showing a semiconductor element in a process key point for explaining the first embodiment;
FIG. 3 is a cutaway side view of a main part showing a semiconductor element and a manufacturing apparatus at process points for explaining a second embodiment;
FIG. 4 is a cutaway side view showing a main part of a semiconductor element at a process point for explaining a process of manufacturing a conventional semiconductor element.
FIG. 5 is a cut-away side view of a main part showing a semiconductor element at a process point for explaining a process of manufacturing a conventional semiconductor element.
[Explanation of symbols]
11 Si substrate 12 side wall 15 Co film 15S source electrode 15D drain electrode 15G gate electrode made of the element isolation region 13 Si gate electrode 14 SiO ₂ consisting of embedded STI of SiO ₂

Claims (1)

Forming a transition metal film on a substrate on which a Si surface is exposed in the source electrode formation planned region and the drain electrode formation planned region;
Next, a step of forming a source electrode and a drain electrode by performing silicidation treatment of the transition metal film,
Next, performing a thinning process on the source electrode and the drain electrode to separate an edge of the source electrode and the drain electrode from an inter-element isolation region and a gate having a gate electrode having at least a side surface covered with an insulating film;
A method for manufacturing a semiconductor device, comprising:

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