JP4046029B2 - Method for manufacturing transistor - Google Patents

Method for manufacturing transistor Download PDF

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Publication number
JP4046029B2
JP4046029B2 JP2003194242A JP2003194242A JP4046029B2 JP 4046029 B2 JP4046029 B2 JP 4046029B2 JP 2003194242 A JP2003194242 A JP 2003194242A JP 2003194242 A JP2003194242 A JP 2003194242A JP 4046029 B2 JP4046029 B2 JP 4046029B2
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insulating film
film
semiconductor film
forming
transistor
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JP2005032857A (en
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一夫 湯田坂
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2003194242A priority Critical patent/JP4046029B2/en
Priority to US10/859,126 priority patent/US20050020000A1/en
Priority to TW093116470A priority patent/TWI239652B/en
Priority to CNB2004100592640A priority patent/CN100452436C/en
Priority to KR1020040047939A priority patent/KR100704253B1/en
Publication of JP2005032857A publication Critical patent/JP2005032857A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1292Multistep manufacturing methods using liquid deposition, e.g. printing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、トランジスタの製造技術に関する。
【0002】
【従来の技術】
半導体装置の製造過程において、その膜表面を平坦化することは、この上に形成される配線等の断線や短絡を防止する上で極めて重要である。特にトランジスタでは、ゲート絶縁膜の膜厚均一性が電気的特性に大きく影響するため、このゲート絶縁膜をより平坦に形成する技術が求められている。
従来、トランジスタのゲート絶縁膜は主にCVD法により形成されていた(特許文献1,2参照)。
【0003】
【特許文献1】
特開平8−181325号公報
【特許文献2】
特開平10−144929号公報
【0004】
【発明が解決しようとする課題】
しかしながら、従来のトランジスタでは、ゲート耐圧が十分にとれず、又、リーク電流が多くなる等の課題があった。これは、主に基板表面の凹凸に対するCVD膜の被覆性に起因する。例えばトップゲート型のトランジスタでは、ゲート絶縁膜はパターニングされたシリコン膜(半導体膜)の上に形成されるため、基板上には少なくともこの半導体膜自体の膜厚に起因した段差が形成される。また、半導体膜のパターニング工程では、その下地絶縁膜である酸化シリコンや窒化シリコンも一部エッチングされるため、基板上には更にこのエッチング量に応じた段差が形成される。そして、これらは重畳してより大きな段差となる。このような段差部分にCVD法でゲート絶縁膜を形成すると、半導体膜の上端部や側端部にゲート絶縁膜の薄い部分ができ、ゲート耐圧の低下やリーク電流の増加等の問題を惹起する。
【0005】
また、CVD法ではパーティクル等の異物が生じることがあり、これにより、更にゲート耐圧の低下やリーク電流の増加を招いたり、或いはゲート電極とソース又はドレインとのショート欠陥となることがあった。
本発明は、上記の課題を解決するためになされたものであって、電気的特性に優れ、信頼性の高いトランジスタを製造できるようにしたトランジスタの製造方法、及びこのトランジスタを備えた電気光学装置,電子機器を提供することを目的とする。
【0006】
【課題を解決するための手段】
上記の目的を達成するために、本発明のトランジスタの製造方法は、基板上に半導体膜を形成する工程と、前記半導体膜を島状にパターニングする工程と、前記半導体膜の上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜の上にゲート電極を形成する工程とを備え、前記ゲート絶縁膜の形成工程は、前記ゲート絶縁膜の少なくとも一部を構成する第1の絶縁膜を塗布法により形成する工程を含み、前記半導体膜のパターニング工程では、前記第1の絶縁膜の形成工程で使用する塗布液の物性、塗布条件及び必要とされる前記第1の絶縁膜の膜厚に応じて前記半導体膜のパターンサイズを設定することを特徴とする。
【0007】
本方法では第1の絶縁膜を塗布膜としたため、半導体膜自身の膜厚による段差や、パターニング工程において削られた下地絶縁膜による段差等をこの第1の絶縁膜により平坦化することができる。これにより、ゲート絶縁膜の膜厚の均一性が高まり、高耐圧でリーク電流の少ないトランジスタが得られる。また、塗布法では、パーティクル等の異物が生じることがないため、トランジスタの信頼性も高まる。
【0008】
なお、第1の絶縁膜の形成工程では、スピンコート法,ディップコート法,ロールコート法,カーテンコート法,スプレー法,液滴吐出法(インクジェット法)等、種々の塗布方法を用いることができるが、特にスピンコート法では、遠心力により液膜が基板面内に広がるため、より平坦な膜が形成され易い。
また、塗布液としては、第1の絶縁膜の原料やその前駆体、或いは、熱処理により第1の絶縁膜に転化可能な種々の液体材料を用いることができる。具体的には、ポリシラザンやSOG(Spin On Glass)等をキシレン等の溶剤に溶かしたものを塗布液として用い、これを熱処理により酸化シリコンに転化させることで、高品質なゲート絶縁膜を形成することができる。特にポリシラザンでは、他のものに比べてクラック耐性が高く、残留不純物の少ない絶縁膜を形成できる。なお、ポリシラザンの熱処理はWET O2雰囲気(水蒸気を含んだ酸素雰囲気)下で行なうことが望ましい。これにより、分極の原因となる絶縁膜中の窒素成分を少なくすることができ、トランジスタの電気的特性が安定する。
【0009】
ところで、第1の絶縁膜の形成工程では、基板の凹凸によって、塗布液の流動抵抗にばらつきが生じることがある。例えば、半導体膜の形成された領域は他の領域に比べて塗布液の流動抵抗が相対的に大きくなり、この部分の膜面に盛り上がりが生じる場合がある。この盛り上がりの大きさは、塗布膜の膜厚(即ち、第1の絶縁膜の膜厚),塗布液の物性(粘度等),塗布条件だけでなく、この塗布膜が形成される半導体膜の大きさによっても変わる。つまり、ゲート絶縁膜の膜厚均一性は、第1の絶縁膜の形成工程だけでなく、前工程である半導体膜のパターニング工程とも密接に関連しており、均一な膜を得るためには、半導体膜のパターニング工程において予め、後工程で用いる塗布液の物性,塗布条件,及び必要とされる第1の絶縁膜の膜厚に応じて、そのパターンサイズを最適に設定しておくことが望ましい。
【0010】
具体的な手順としては、まず、トランジスタの要求性能に応じて半導体膜の全体サイズやゲート絶縁膜の膜厚を決める。次に、このゲート絶縁膜の膜厚に応じて、必要となる第1の絶縁膜の膜厚を決め、この膜厚が得られるように塗布液の物性(粘度等)及び塗布条件を決める。これらの条件が決まれば、例えば実験データ等から、塗布膜の膜面に盛り上がりが生じない、或いは、盛り上がりができてもそれが許容されるような半導体膜の最大サイズが決まるため、このサイズ範囲内で半導体膜のパターンサイズを設定すればよい。例えば、半導体膜の全体サイズが上記最大サイズよりも大きくなる場合には、半導体膜を複数に分割して形成すればよい。このようにトランジスタをマルチゲート構造として個々の半導体膜のサイズを小さくする(即ち、上記最大サイズ以下とする)ことで、この上に形成されるゲート絶縁膜をより平坦化することができる。
【0011】
また、ゲート絶縁膜の形成工程では、上記第1の絶縁膜の形成工程前に、上記半導体膜を表面酸化することで、ゲート絶縁膜の一部を構成する第2の絶縁膜を形成する工程を設けることが望ましい。トランジスタでは、ゲート絶縁膜の膜質や膜厚の均一性の他に、ゲート絶縁膜の界面特性がトランジスタの電気的特性に大きく影響する。このため、半導体膜との界面に、塗布膜である第1の絶縁膜よりも良好な界面特性が得られる表面酸化膜を設けることで、トランジスタの高性能化を図ることができる。
【0012】
この第2の絶縁膜の形成方法としては、例えば酸素含有ガスを処理ガスとして半導体膜の表面をプラズマ処理する方法が挙げられる。また、この代わりに、オゾンガス雰囲気下で半導体膜を加熱してもよい。この方法では、加熱された半導体膜の近傍でオゾンが分解し、酸素ラジカルが発生する。そして、活性状態の酸素ラジカルにより半導体膜の表面が酸化され、酸化膜が形成される。このため、プラズマを用いる方法よりも、膜面のダメージが少なく高品質な界面が得られるとともに、装置の簡素化と処理時間の短縮化を図ることができる。
【0013】
また、上記ゲート絶縁膜の形成工程では、上記半導体膜との界面又はゲート電極との界面に、ゲート絶縁膜の一部を構成する第3の絶縁膜を蒸着法により形成する工程を設けてもよい。これによっても、良好な界面特性が得られる。なお、この第3の絶縁膜は、半導体膜との界面及びゲート電極との界面のいずれか一方のみに形成してもよいが、双方に形成することも可能である。
また、本発明の電気光学装置は、上述の方法により製造されたトランジスタを備えたことを特徴とする。また、本発明の電子機器はこの電気光学装置を備えたことを特徴とする。これにより、高性能な電気光学装置及び電子機器を提供することができる。
【0014】
【発明の実施の形態】
以下、図面を参照しながら本発明の電気光学装置の一例としての液晶装置について説明する。なお、以下の全ての図面においては、図面を見やすくするため、各構成要素の膜厚や寸法の比率などは適宜異ならせてある。
【0015】
図1に示すように、本実施形態の液晶装置1は、アクティブマトリクス基板10と、対向基板20と、基板10,20の間に保持される光変調層としての液晶層40とを備えている。
【0016】
図1(a)はアクティブマトリクス基板10の要部平面構造を示す図である。
基板10には、ガラスやプラスチック等からなる基板本体10Aの上に、それぞれX方向,Y方向に複数の走査線33,信号線34が設けられており、これらの配線33,34によって区画されたそれぞれの画素には画素電極14が配置されている。また、各画素には、画素電極14の通電制御を行なうための複数(本実施形態では2つ)のTFT(薄膜トランジスタ)30が設けられている。すなわち、走査線33と信号線34との交差部近傍には、信号線34に沿って2つの島状の半導体膜31が設けられており、両半導体膜31に被さるように共通のゲート電極33aが配置されている。このゲート電極33aは、走査線33から前段の走査線側に向けて分岐する形で設けられている。これらの半導体膜31のゲート電極33aと対向する領域はチャネル部として機能し、このチャネル部を挟んで左右に対向する位置がそれぞれソース部,ドレイン部となる。また、各半導体膜31のソース部はコンタクトホール12aを介して信号線34に導電接続され、ドレイン部はコンタクトホール12b,13aを介して画素電極14に導電接続されている。
【0017】
図1(b)は図1(a)のA−A′断面の構造を示す図である。
本実施形態のTFT30はトップゲート型の構造を有し、本体となる基板10Aの下層側から順に、半導体膜31,ゲート絶縁膜32,ゲート電極33aが積層されている。すなわち、下地絶縁膜11の上に島状に設けられた半導体膜31の上に、基板全面を覆うようにゲート絶縁膜32が設けられ、このゲート絶縁膜32上に、半導体膜31と対向してゲート電極33aが設けられている。また、基板10Aの上には、ゲート絶縁膜32及びゲート電極33aを覆うように層間絶縁膜12が設けられ、この絶縁膜12の上に信号線34及び中間層35が設けられている。この絶縁膜12には、半導体膜31のソース部31bに通じるコンタクトホール12aと、ドレイン部31cに通じるコンタクトホール12bとが設けられており、これらのコンタクトホール12a,12bを介して信号線34,中間層35がそれぞれ上記ソース部31b,ドレイン部31cに導電接続されている。さらに、基板10Aの上には、層間絶縁膜12,信号線34,中間層35を覆うように層間絶縁膜13が設けられ、この絶縁膜13の上に画素電極14が設けられている。そして、上述のように構成された基板には、更に画素電極14,層間絶縁膜13を覆うように、ポリイミド等からなる配向膜15が設けられている。
【0018】
一方、対向基板20には、ガラスやプラスチック等の透光性基板からなる基板本体20Aの上に、ITO等からなる透光性の共通電極24が設けられ、更にこの電極24上にポリイミド等からなる配向膜25が設けられている。
【0019】
ところで、上述のゲート絶縁膜32は、島状の半導体膜31の表面を覆う絶縁膜32aと、この上に積層された絶縁膜32bとの2層構造からなる。絶縁膜32aは例えばPECVD法やスパッタ法等の蒸着法によって酸化シリコンや窒化シリコン等を形成することで得られる。或いは、半導体膜31の表面を酸化してもよい。この方法としては、例えば酸素含有ガスを処理ガスとして半導体膜31の表面をプラズマ処理する方法や、酸素含有ガス雰囲気下で半導体膜に紫外線を照射する方法等が挙げられる。これらの方法ではいずれも半導体膜31との間で良好な界面を形成でき、トランジスタの高性能化に寄与する。なお、本実施形態では、絶縁膜32aの形成方法として、紫外線照射により表面酸化する方法を採用している。
【0020】
一方、絶縁膜32bは、この絶縁膜の原料やその前駆体、或いは、熱処理により絶縁膜に転化可能な材料を溶剤に溶かしたものを塗布液として用い、これを基板上に塗布することで形成されている。
この塗布液としては、例えばポリシラザン(Si−N結合を有する高分子の総称である)を用いることができる。ポリシラザンは、キシレンなどの液体に混合して基板上に塗布され、水蒸気または酸素を含む雰囲気で熱処理することで酸化シリコンに転化する。ポリシラザンのひとつは、[SiH2NH](nは正の整数)であり、ポリペルヒドロシラザンと言われる。この製品は、東燃(株)より「東燃ポリシラザン」の製品名で市販されている。なお、[SiH2NH]中のHがアルキル基(例えばメチル基、エチル基など)で置換されると、有機ポリシラザンとなり、無機ポリシラザンとは区別されることがある。
【0021】
また、塗布された後に熱処理することで絶縁膜となる液体として、SOG(Spin On Glass)を用いることもできる。このSOGは、シロキサン結合を基本構造とするポリマーで、アルキル基を有する有機SOGとアルキル基を持たない無機SOGがあり、アルコールなどが溶媒として使用される。SOG膜は平坦化を目的としてLSIの層間絶縁膜に使用されている。有機SOG膜は酸素プラズマ処理に対してエッチングされ易く、無機SOG膜は数百nmの膜厚でもクラックが発生し易すいなどの問題がある。このため、単層で層間絶縁膜などに使用されることは殆どなく、CVD絶縁膜の上層の平坦化層として利用される。この点、ポリシラザンはクラック耐性が高く、また耐酸素プラズマ性があり、単層でもある程度厚い絶縁膜として使用可能である。また、ポリシラザンは、他の材料に比べて残留不純物の少ない良質な絶縁膜を形成することができる。したがって、本例では、ポリシラザンをキシレンに混合したものを塗布液として用いる。
【0022】
また、塗布方法としては、スピンコート法、ディップコート法、ロールコート法、カーテンコート法、スプレー法、あるいは液滴吐出法(インクジェット法)等、種々の方法を用いることができる。特にスピンコート法では、遠心力によって塗布液が基板面内に引き伸ばされて形成されるため、より均一な膜が形成されやすい。このため、本例では、塗布法としてスピンコート法を用いる。
このようにゲート絶縁膜32の一部を塗布法により形成した場合、塗布液の流動性により、絶縁膜32bは基板表面の凹凸をならす形で平坦に形成され、半導体膜31の形成領域におけるゲート絶縁膜32の膜厚均一性は、CVD法で形成した従来のものに比べて高くなる。
【0023】
しかし、塗布法では、基板表面の凹凸によって塗布液の流動抵抗が変わるため、膜厚に若干の不均一性が生じる場合がある。つまり、絶縁膜32bは半導体膜31のパターニングによって生じた段差をならすように形成されるため、図8(a)に示すように、段差となる半導体膜31の形成領域E1では塗布膜Mの膜厚L2は、半導体膜31の非形成領域E2における塗布膜Mの膜厚L1よりも薄くなり、その分、塗布液の流動抵抗が相対的に大きくなる。このため、両領域E1,E2の流動抵抗差が大きい場合や、段差面が広い場合には、図8(b)に示すように、半導体膜31の形成領域E1において絶縁膜32bの膜面に大きな盛り上がりgが生じ、トランジスタの動作に支障が生じる。よって、このような絶縁膜32bの膜厚不均一性を一定範囲内に留める必要があるが、この膜面の盛り上がりの大きさは、各領域E1,E2に形成される塗布膜Mの膜厚差(L1−L2)や塗布液の物性(粘度等)や塗布条件だけでなく、半導体膜31のサイズWによっても変わるため、半導体膜31のパターニング工程では、後工程である絶縁膜32bの形成工程で用いる塗布液の物性,塗布条件,及び必要とされる絶縁膜32bの膜厚に応じて、そのパターンサイズを最適に設定する必要がある。
【0024】
具体的な製造手順としては、図2に示すように、まず、基板全面に半導体膜を形成し(ステップS1;半導体膜の形成工程)、次に、この半導体膜をパターニングして、それぞれの画素に島状の半導体膜を形成する(半導体膜のパターニング工程)。
【0025】
この際、まず、トランジスタの要求性能に基づいて1画素内に配置される半導体膜の全体サイズやゲート絶縁膜の膜厚を決定する(ステップS2)。次に、このゲート絶縁膜膜厚に応じて、必要となる絶縁膜32bの膜厚を決め、この膜厚が得られるように塗布液の物性及び塗布条件を決定する(ステップS3)。このような条件が決まれば、例えば実験データ等から、塗布膜の膜面に盛り上がりが生じない、或いは、盛り上がりができてもそれが許容されるような半導体膜の最大サイズが決まる。そして、例えば上述の半導体膜の全体サイズが最大サイズ以下の大きさであれば、この全体サイズをそのまま半導体膜のパターンサイズとし、全体サイズが上記最大サイズよりも大きくなる場合には、1画素内に半導体膜を複数に分割して形成し、個々の半導体膜のパターンサイズを小さくする。このようにして1画素内に配置する半導体膜の数及びパターンサイズを決定した(ステップS5)、ステップS1で形成された半導体膜を実際にパターニングする(ステップS6)。
【0026】
この後、ステップS6でパターニングされた半導体膜31の表面を酸化して絶縁膜32aを形成し(ステップS7;第2の絶縁膜の形成工程)、更に、この絶縁膜32aの上に塗布法により絶縁膜32bを形成する(ステップS8;第1の絶縁膜の形成工程)。そして、このようにして形成されたゲート絶縁膜32の上にゲート電極33aをパターン形成する(ステップS9;ゲート電極の形成工程)ことで、トランジスタが製造される。
【0027】
以下、これらの工程を図3〜図6を参照しながら詳細に説明する。
まず、図3に示すように、ガラス等からなる基板本体10Aの上に、TEOS(テトラエトキシシラン)や酸素ガスなどを原料としてプラズマCVD法により、シリコン酸化膜からなる下地絶縁膜11を形成する。なお、下地絶縁膜として、シリコン酸化膜の他に、シリコン窒化膜やシリコン酸化窒化膜を設けてもよい。この下地絶縁膜11は、基板10Aの表面状態を整えるとともに、基板10A内の不純物による半導体膜31の汚染を防止することを目的としているが、これを省略することもできる。
【0028】
次に、プラズマCVD法等を用いて、下地絶縁膜11の上にアモルファスシリコン膜からなる半導体膜を形成する。この半導体膜としては、アモルファスシリコン膜に限定されず、微結晶半導体膜などのアモルファス構造を含む半導体膜であればよい。また、アモルファスシリコンゲルマニウム膜などの非晶質構造を含む化合物半導体膜でもよい。続いて、この半導体膜に対してレーザアニール法や、急速加熱法(ランプアニール法や熱アニール法など)などの結晶化工程を行ない、半導体膜をポリシリコン膜に結晶化する(半導体膜の形成工程)。レーザアニール法では、例えばエキシマレーザでビームの長寸が400mmのラインビームを用い、その出力強度は例えば400mJ/cmとする。なお、YAGレーザの第2高調波或いは第3高調波を用いてもよい。ラインビームについては、その短寸方向におけるレーザ強度のピーク値の90%に相当する部分が各領域毎に重なるようにラインビームを走査するのがよい。
【0029】
次に、図4に示すように、この半導体膜310を所望のサイズにパターニングする(半導体膜のパターニング工程)。この際、次工程である絶縁膜32bの形成工程において平坦性のよい膜を形成するために、前述の手順に従って、半導体膜310のパターンサイズを一定範囲内に制限する。例えば本例では、絶縁膜32bにおいて所望の膜厚を得るために、塗布液の粘度,表面張力、及び、スピンコートの回転数,回転時間を決定し、この条件に基づいて、許容される半導体膜の最大サイズを決定する。具体的には、半導体膜31の一辺のサイズW1,W2をそれぞれ50μm以下とし、これに応じて、1画素内に2つの半導体膜31をパターン形成している。このように1画素内に半導体膜を複数に分割して形成することで、個々の半導体膜31のサイズを小さくしながら、全体としてトランジスタの要求性能を満たすことができる。
【0030】
次に、図5,図6に基づいて、図4に示した一方の半導体膜31を用いてトランジスタを製造する方法について説明する。なお、図5,図6は、図4の一部分を取り出して異なる縮尺で示す図であり、各工程における基板10の一部分を、図1(b)に示した液晶表示装置の断面図に対応させて示している。
【0031】
半導体膜310のパターニングが終了すると、図5(a)に示すように、酸素含有ガス雰囲気下で、基板にUV光を照射し、基板表面に存在する汚染物(有機物など)を分解除去する。ここで、照射するUV光は、波長254nmにピーク強度を有する低圧水銀ランプや、波長172nmにピーク強度を有するエキシマランプを用いる。この波長領域の光は、酸素分子(O)をオゾン(O)に分解し、更に、このオゾンを酸素ラジカル(O)に分解するため、このように生成された活性度の高いオゾンや酸素ラジカルを利用することで、基板表面に付着した有機物を効率的に除去できる。
【0032】
次に、図5(b)に示すように、基板を200℃〜500℃に加熱するとともに、酸素含有ガス雰囲気下で基板にUV光を照射し、基板上に酸素ラジカル(O)を発生させる。そして、酸素ラジカルにより、半導体膜31の表面を酸化し、シリコン酸化膜(第2の絶縁膜)32aを形成する(第2の絶縁膜の形成工程)。照射するUV光は、波長254nm以下のピークを有するものが用いられる。前述したように、この波長領域の光は酸素分子(O)をオゾン(O)に分解し、更にこのオゾンを酸素ラジカル(O)に分解する。また、波長175nm以下の光は、酸素分子(O)を直接分解し、酸素ラジカル(O)を生成する。そして、高温に加熱された基板表面に、このような活性状態の酸素ラジカルが生成されることで、半導体膜31の表面が酸化され、絶縁膜32aが形成される。
【0033】
ここで、上記UV光を発する光源としては、上記波長成分を有する光を発することが可能なものであればよく、例えば、低圧水銀ランプのように複数の線スペクトルを有するもの、エキシマランプやエキシマレーザなどの単色スペクトルを有するもの、キセノンフラッシュランプなどの連続スペクトルを有するものが用いられる。エキシマレーザとしては、例えば、中心波長248nmのフッ化クリプトンレーザ、中心波長193nmのフッ化アルゴンレーザなどがある。
また、基板の加熱は、ホットプレートなどの抵抗加熱方式でもよく、照射する光のエネルギーを用いた加熱でもよい。光のエネルギーを用いて基板を加熱する場合、基板の加熱に適した波長成分を有する光が好ましい。照射する光のエネルギーを用いて基板の加熱を行なうことにより、エネルギー利用の効率化が図られる。すなわち、酸素ラジカルの生成に使われなかった光のエネルギーを、基板の加熱のために効率的に利用することができる。また、抵抗加熱などを用いた他の加熱手段が不要となり、装置の簡素化が図られる。なお、抵抗加熱方式と光エネルギー加熱方式とを組み合わせて基板を加熱してもよい。
【0034】
このプロセスでは、プラズマを用いることなく酸素ラジカルを発生させるため、膜面のダメージが少なく、半導体膜31との間で高品質な界面を形成することができる。また、この方法では、プラズマによって酸素ラジカルを発生させる場合に比べて装置構成を簡素化できる他、基板が配置される空間を真空圧にする必要がないため、処理時間を短縮できる利点もある。
【0035】
次に、図5(c)に示すように、絶縁膜32a上にシリコン酸化膜(第1の絶縁膜)32bを形成する(第1の絶縁膜の形成工程)。この絶縁膜32bは、ポリシラザンをキシレンに混合した塗布液を基板上にスピンコートした後、熱処理することにより形成される。この際、塗布液の物性(粘度や表面張力)やスピンコートの条件については、前述のパターニング工程で予め決定されたものを用いる。例えば、キシレン中にポリシラザンを10%混合した塗布液を回転数1500rpmでスピンコートし、処理温度を100℃として5分間、プリベークを行なう。この後更に、処理温度を350℃としてWET O2雰囲気下で260分間、熱処理を行なう。これにより、膜厚150nmの酸化シリコン膜が形成される。このように熱処理をWET O2雰囲気下で行なうことで、分極の原因となる絶縁膜中の窒素成分を少なくすることができる。
【0036】
次に、図6(a)に示すように、絶縁膜32bの上に、ドープドシリコン,シリサイド膜や、アルミニウム(Al),タンタル(Ta),モリブデン(Mo),チタン(Ti),タングステン(W),銅(Cu),クロム(Cr)などの金属或いはこれらの金属を含む合金からなるゲート電極形成用導電膜を形成し、続いて、この導電膜をパターニングして走査線33及びゲート電極33aを形成する(ゲート電極の形成工程)。なお、ゲート電極33aは単層の導電膜で形成してもよく、積層構造としてもよい。
次に、このゲート電極33aをマスクとして不純物元素をドープする。これにより、半導体膜31にソース部31bとドレイン部31cがゲート電極33aに対して自己整合的に形成される。そして、ゲート電極33aで覆われ、不純物がドープされなかった領域がチャネル部31aとなる。
【0037】
次に、図6(b)に示すように、ゲート絶縁膜32及びゲート電極33aを覆うように、層間絶縁膜12を形成する。この層間絶縁膜12としては、例えばシリコン酸化窒化膜やシリコン酸化膜等のシリコンを含む絶縁膜を用いることができる。
【0038】
続いて、図6(c)に示すように、層間絶縁膜12を一部開口して、半導体膜31のソース部31b及びドレイン部31cに対応する位置にそれぞれコンタクトホール12a,12bを形成する。次に、このコンタクトホール12a、12bの内壁を覆うように、アルミニウム膜、クロム膜やタンタル膜などの金属膜を形成し、パターニングによりソース電極(信号線)34及びドレイン電極(中間層)35を形成する。
以上の工程により、トランジスタ30が製造される。
【0039】
このように本実施形態では、絶縁膜32bを塗布膜としたため、半導体膜のパターニング工程で生じた基板上の凹凸を、この絶縁膜32bによって平坦化することができる。これにより、ゲート絶縁膜32の膜厚均一性が高まり、高耐圧でリーク電流の少ないトランジスタが得られる。特に本実施形態では、塗布膜の平坦性に対する半導体膜31のサイズの影響を考慮して、予め半導体膜のパターニング工程でパターンサイズを一定範囲内に制限しているため、絶縁膜32bの膜厚をより均一にすることができる。
また、本実施形態ではゲート絶縁膜32を、塗布膜としての絶縁膜32bと、半導体膜31の表面酸化膜である絶縁膜32aとの積層膜としているため、半導体膜31との間で良好な界面特性が得られる。
【0040】
[電子機器]
次に、本発明の液晶装置を備えた電子機器の具体例について説明する。
図7は、ワープロ、パソコンなどの携帯型情報処理装置の一例を示した斜視図である。図8において、符号1200は情報処理装置、符号1202はキーボードなどの入力部、符号1204は情報処理装置本体、符号1206は上述の液晶装置を用いた表示部を示している。
図7に示す電子機器は、上記実施形態の液晶装置を用いた表示部を備えているので、確実なスイッチングにより高品質な表示が可能となる。
【0041】
なお、本発明は上述の実施形態に限定されるものではなく、本発明の趣旨を逸脱しない範囲で種々変形して実施することができる。
例えば、上記実施形態では、ゲート絶縁膜32を半導体膜31の表面酸化膜32aと塗布膜である絶縁膜32bとの2層構造としたが、これを3層以上の多層膜とすることもできる。例えば、蒸着法等により、ゲート電極33aとの界面に第3の絶縁膜を形成することで、トランジスタの電気的特性を更に安定させることができる。勿論、第1の絶縁膜32bのみで良好な界面特性が得られる場合には、第2の絶縁膜32aや上述の第3の絶縁膜を省略して、ゲート絶縁膜32を絶縁膜32bのみの単層構造とすることも可能である。
【0042】
また、図4では、半導体膜を1画素内で2つに分割して形成した例を示したが、この代わりに、半導体膜を3つ或いはそれ以上に分割してもよい。勿論、図2のステップS2で決定された半導体膜の全体サイズが十分小さい場合には、半導体膜を分割せずに単独で設けることも可能である。
また、上記実施形態では電気光学装置として液晶装置を例に挙げて説明したが、これ以外にも、例えば有機EL表示装置や電気泳動表示装置等の種々のデバイスに対して本発明を適用することができる。
【図面の簡単な説明】
【図1】 本発明の一実施形態に係る液晶装置の要部構造を示す図。
【図2】 トランジスタの製造手順を説明するためのフロー。
【図3】 本発明のトランジスタの製造方法を説明するための工程図。
【図4】 図3に続く工程図。
【図5】 図4に続く工程図。
【図6】 図5に続く工程図。
【図7】 本発明の電子機器の一例を示す図。
【図8】 ゲート絶縁膜の膜厚均一性に対する半導体膜のサイズの影響を説明するための図。
【符号の説明】
1・・・液晶装置(電気光学装置)、10A…基板、31…半導体膜、32・・・ゲート絶縁膜、32a・・・第2の絶縁膜、32b・・・第1の絶縁膜、33a・・・ゲート電極、1200・・・電子機器
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a transistor manufacturing technique.
[0002]
[Prior art]
In the manufacturing process of a semiconductor device, it is extremely important to flatten the surface of the film in order to prevent disconnection or short circuit of wirings formed thereon. In particular, in a transistor, since the uniformity of the thickness of the gate insulating film greatly affects the electrical characteristics, a technique for forming the gate insulating film more flatly is required.
Conventionally, a gate insulating film of a transistor has been mainly formed by a CVD method (see Patent Documents 1 and 2).
[0003]
[Patent Document 1]
JP-A-8-181325
[Patent Document 2]
JP 10-144929 A
[0004]
[Problems to be solved by the invention]
However, conventional transistors have problems such as insufficient gate breakdown voltage and increased leakage current. This is mainly due to the coverage of the CVD film with respect to the unevenness of the substrate surface. For example, in a top-gate transistor, since the gate insulating film is formed on a patterned silicon film (semiconductor film), a step due to at least the thickness of the semiconductor film itself is formed on the substrate. In the patterning process of the semiconductor film, silicon oxide and silicon nitride, which are the underlying insulating films, are also partially etched, so that a step corresponding to the etching amount is further formed on the substrate. These are superposed to form a larger step. If a gate insulating film is formed on such a step portion by CVD, a thin portion of the gate insulating film is formed at the upper end portion or side end portion of the semiconductor film, causing problems such as a decrease in gate breakdown voltage and an increase in leakage current. .
[0005]
In addition, foreign substances such as particles may be generated in the CVD method, which may cause a further decrease in gate breakdown voltage, an increase in leakage current, or a short defect between the gate electrode and the source or drain.
The present invention has been made to solve the above-described problems, and a transistor manufacturing method capable of manufacturing a transistor having excellent electrical characteristics and high reliability, and an electro-optical device including the transistor The purpose is to provide electronic equipment.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, a transistor manufacturing method of the present invention includes a step of forming a semiconductor film on a substrate, a step of patterning the semiconductor film into an island shape, and a gate insulating film on the semiconductor film. And a step of forming a gate electrode on the gate insulating film, wherein the step of forming the gate insulating film comprises applying a first insulating film constituting at least a part of the gate insulating film. In the patterning step of the semiconductor film, the physical properties of the coating liquid used in the first insulating film forming step, the coating conditions, and the required film thickness of the first insulating film are included. Accordingly, the pattern size of the semiconductor film is set accordingly.
[0007]
In this method, since the first insulating film is the coating film, a step due to the film thickness of the semiconductor film itself, a step due to the base insulating film removed in the patterning step, or the like can be planarized by the first insulating film. . Thereby, the uniformity of the film thickness of the gate insulating film is increased, and a transistor with a high breakdown voltage and a small leakage current is obtained. Further, in the coating method, foreign matters such as particles are not generated, so that the reliability of the transistor is increased.
[0008]
Note that in the first insulating film formation step, various coating methods such as a spin coating method, a dip coating method, a roll coating method, a curtain coating method, a spray method, and a droplet discharge method (inkjet method) can be used. However, in the spin coating method in particular, since the liquid film spreads in the substrate surface by centrifugal force, a flatter film can be easily formed.
As the coating solution, a raw material for the first insulating film, a precursor thereof, or various liquid materials that can be converted into the first insulating film by heat treatment can be used. Specifically, a high-quality gate insulating film is formed by using a solution obtained by dissolving polysilazane, SOG (Spin On Glass) or the like in a solvent such as xylene as a coating liquid, and converting it into silicon oxide by heat treatment. be able to. In particular, polysilazane can form an insulating film having higher resistance to cracking and less residual impurities than other materials. The heat treatment of polysilazane is WET O 2 It is desirable to carry out in an atmosphere (oxygen atmosphere containing water vapor). Accordingly, the nitrogen component in the insulating film that causes polarization can be reduced, and the electrical characteristics of the transistor are stabilized.
[0009]
By the way, in the formation process of the first insulating film, the flow resistance of the coating liquid may vary due to the unevenness of the substrate. For example, in the region where the semiconductor film is formed, the flow resistance of the coating liquid is relatively larger than in other regions, and the film surface of this portion may be raised. The size of the swell is not only the thickness of the coating film (that is, the thickness of the first insulating film), the physical properties of the coating liquid (viscosity, etc.), the coating conditions, but also the semiconductor film on which the coating film is formed. It depends on the size. In other words, the film thickness uniformity of the gate insulating film is closely related not only to the process of forming the first insulating film but also to the patterning process of the semiconductor film as the previous process. In the patterning process of the semiconductor film, it is desirable that the pattern size is optimally set in advance according to the physical properties of the coating liquid used in the subsequent process, the coating conditions, and the required thickness of the first insulating film. .
[0010]
As a specific procedure, first, the overall size of the semiconductor film and the film thickness of the gate insulating film are determined according to the required performance of the transistor. Next, the required thickness of the first insulating film is determined according to the thickness of the gate insulating film, and the physical properties (viscosity, etc.) of the coating solution and the coating conditions are determined so as to obtain this thickness. If these conditions are determined, the maximum size of the semiconductor film is determined from, for example, experimental data, so that the film surface of the coating film does not swell or is allowed to swell. In this case, the pattern size of the semiconductor film may be set. For example, when the entire size of the semiconductor film is larger than the maximum size, the semiconductor film may be divided into a plurality of parts. In this manner, by making the transistor a multi-gate structure and reducing the size of each semiconductor film (that is, not more than the above maximum size), the gate insulating film formed thereon can be further planarized.
[0011]
In the step of forming the gate insulating film, a step of forming a second insulating film constituting a part of the gate insulating film by subjecting the semiconductor film to surface oxidation before the step of forming the first insulating film. It is desirable to provide In the transistor, in addition to the film quality and film thickness uniformity of the gate insulating film, the interface characteristics of the gate insulating film greatly affect the electrical characteristics of the transistor. Therefore, by providing a surface oxide film that provides better interface characteristics than the first insulating film, which is a coating film, at the interface with the semiconductor film, high performance of the transistor can be achieved.
[0012]
As a method for forming the second insulating film, for example, there is a method in which the surface of the semiconductor film is plasma-treated using an oxygen-containing gas as a processing gas. Alternatively, the semiconductor film may be heated in an ozone gas atmosphere. In this method, ozone is decomposed in the vicinity of the heated semiconductor film, and oxygen radicals are generated. Then, the surface of the semiconductor film is oxidized by oxygen radicals in an active state, and an oxide film is formed. For this reason, it is possible to obtain a high quality interface with less damage on the film surface than the method using plasma, and to simplify the apparatus and shorten the processing time.
[0013]
Further, the step of forming the gate insulating film may include a step of forming a third insulating film constituting a part of the gate insulating film by an evaporation method at an interface with the semiconductor film or an interface with the gate electrode. Good. This also provides good interface characteristics. Note that the third insulating film may be formed only on either the interface with the semiconductor film or the interface with the gate electrode, but can also be formed on both.
According to another aspect of the invention, an electro-optical device includes the transistor manufactured by the above-described method. The electronic apparatus according to the present invention includes the electro-optical device. Thereby, a high-performance electro-optical device and electronic apparatus can be provided.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a liquid crystal device as an example of the electro-optical device of the invention will be described with reference to the drawings. In all the drawings below, the film thicknesses and dimensional ratios of the constituent elements are appropriately changed in order to make the drawings easy to see.
[0015]
As shown in FIG. 1, the liquid crystal device 1 of this embodiment includes an active matrix substrate 10, a counter substrate 20, and a liquid crystal layer 40 as a light modulation layer held between the substrates 10 and 20. .
[0016]
FIG. 1A is a diagram illustrating a planar structure of a main part of the active matrix substrate 10.
The substrate 10 is provided with a plurality of scanning lines 33 and signal lines 34 in the X direction and the Y direction on a substrate body 10A made of glass, plastic, or the like, and is partitioned by these wirings 33 and 34. A pixel electrode 14 is disposed in each pixel. Each pixel is provided with a plurality (two in this embodiment) of TFTs (thin film transistors) 30 for performing energization control of the pixel electrode 14. That is, in the vicinity of the intersection of the scanning line 33 and the signal line 34, two island-shaped semiconductor films 31 are provided along the signal line 34, and a common gate electrode 33 a is provided so as to cover both the semiconductor films 31. Is arranged. The gate electrode 33a is provided so as to branch from the scanning line 33 toward the preceding scanning line side. The region of the semiconductor film 31 facing the gate electrode 33a functions as a channel portion, and the positions facing left and right across the channel portion are a source portion and a drain portion, respectively. The source portion of each semiconductor film 31 is conductively connected to the signal line 34 via the contact hole 12a, and the drain portion is conductively connected to the pixel electrode 14 via the contact holes 12b and 13a.
[0017]
FIG.1 (b) is a figure which shows the structure of the AA 'cross section of Fig.1 (a).
The TFT 30 of this embodiment has a top gate type structure, and a semiconductor film 31, a gate insulating film 32, and a gate electrode 33a are stacked in this order from the lower layer side of the substrate 10A serving as a main body. That is, a gate insulating film 32 is provided on the semiconductor film 31 provided in an island shape on the base insulating film 11 so as to cover the entire surface of the substrate, and is opposed to the semiconductor film 31 on the gate insulating film 32. A gate electrode 33a is provided. An interlayer insulating film 12 is provided on the substrate 10A so as to cover the gate insulating film 32 and the gate electrode 33a, and a signal line 34 and an intermediate layer 35 are provided on the insulating film 12. The insulating film 12 is provided with a contact hole 12a that communicates with the source part 31b of the semiconductor film 31 and a contact hole 12b that communicates with the drain part 31c, and the signal lines 34, The intermediate layer 35 is electrically connected to the source part 31b and the drain part 31c, respectively. Further, an interlayer insulating film 13 is provided on the substrate 10A so as to cover the interlayer insulating film 12, the signal line 34, and the intermediate layer 35, and the pixel electrode 14 is provided on the insulating film 13. The substrate configured as described above is further provided with an alignment film 15 made of polyimide or the like so as to cover the pixel electrode 14 and the interlayer insulating film 13.
[0018]
On the other hand, the counter substrate 20 is provided with a translucent common electrode 24 made of ITO or the like on a substrate body 20A made of a translucent substrate such as glass or plastic. An alignment film 25 is provided.
[0019]
By the way, the gate insulating film 32 described above has a two-layer structure of an insulating film 32a covering the surface of the island-shaped semiconductor film 31 and an insulating film 32b stacked thereon. The insulating film 32a is obtained by forming silicon oxide, silicon nitride, or the like by a vapor deposition method such as PECVD method or sputtering method. Alternatively, the surface of the semiconductor film 31 may be oxidized. Examples of this method include a method in which the surface of the semiconductor film 31 is subjected to plasma processing using an oxygen-containing gas as a processing gas, and a method in which the semiconductor film is irradiated with ultraviolet rays in an oxygen-containing gas atmosphere. In any of these methods, a good interface can be formed with the semiconductor film 31, which contributes to higher performance of the transistor. In the present embodiment, as a method of forming the insulating film 32a, a method of surface oxidation by ultraviolet irradiation is employed.
[0020]
On the other hand, the insulating film 32b is formed by applying a raw material of this insulating film, a precursor thereof, or a material in which a material that can be converted into an insulating film by heat treatment is dissolved in a solvent, and applying this onto a substrate. Has been.
As this coating solution, for example, polysilazane (which is a general term for polymers having Si—N bonds) can be used. Polysilazane is mixed with a liquid such as xylene and applied onto the substrate, and converted to silicon oxide by heat treatment in an atmosphere containing water vapor or oxygen. One of the polysilazanes is [SiH 2 NH] n (N is a positive integer) and is called polyperhydrosilazane. This product is commercially available from Tonen Corporation under the product name “Tonen Polysilazane”. In addition, [SiH 2 NH] n When H in the inside is substituted with an alkyl group (for example, a methyl group, an ethyl group, etc.), it becomes an organic polysilazane and may be distinguished from an inorganic polysilazane.
[0021]
Further, SOG (Spin On Glass) can also be used as a liquid that becomes an insulating film by heat treatment after being applied. This SOG is a polymer having a siloxane bond as a basic structure, and includes an organic SOG having an alkyl group and an inorganic SOG having no alkyl group, and alcohol or the like is used as a solvent. The SOG film is used as an interlayer insulating film of LSI for the purpose of planarization. The organic SOG film is easily etched with respect to the oxygen plasma treatment, and the inorganic SOG film has a problem that cracks are easily generated even with a film thickness of several hundred nm. For this reason, it is rarely used as an interlayer insulating film or the like in a single layer, and is used as a planarizing layer on the upper layer of the CVD insulating film. In this respect, polysilazane has high crack resistance and oxygen plasma resistance, and even a single layer can be used as a thick insulating film to some extent. Polysilazane can form a high-quality insulating film with fewer residual impurities than other materials. Therefore, in this example, a mixture of polysilazane and xylene is used as the coating solution.
[0022]
As a coating method, various methods such as a spin coating method, a dip coating method, a roll coating method, a curtain coating method, a spray method, or a droplet discharge method (ink jet method) can be used. In particular, in the spin coating method, since the coating liquid is formed by being stretched in the substrate surface by centrifugal force, a more uniform film is easily formed. For this reason, in this example, a spin coat method is used as a coating method.
When a part of the gate insulating film 32 is formed by the coating method in this way, the insulating film 32b is formed flat so as to level the unevenness of the substrate surface due to the fluidity of the coating solution, and the gate in the region where the semiconductor film 31 is formed. The film thickness uniformity of the insulating film 32 is higher than the conventional film formed by the CVD method.
[0023]
However, in the coating method, since the flow resistance of the coating solution changes depending on the unevenness of the substrate surface, there may be some unevenness in the film thickness. That is, since the insulating film 32b is formed so as to have a level difference caused by the patterning of the semiconductor film 31, as shown in FIG. 8A, the film of the coating film M is formed in the formation region E1 of the semiconductor film 31 that becomes the level difference. The thickness L2 is thinner than the film thickness L1 of the coating film M in the non-formation region E2 of the semiconductor film 31, and the flow resistance of the coating liquid is relatively increased accordingly. Therefore, when the difference in flow resistance between the regions E1 and E2 is large or when the step surface is wide, as shown in FIG. 8B, the film surface of the insulating film 32b is formed in the formation region E1 of the semiconductor film 31. A large swell g occurs, which hinders the operation of the transistor. Therefore, it is necessary to keep the film thickness non-uniformity of the insulating film 32b within a certain range. The bulge of the film surface is the film thickness of the coating film M formed in each region E1, E2. In addition to the difference (L1-L2), the physical properties of the coating liquid (viscosity, etc.), the coating conditions, and the size W of the semiconductor film 31, the insulating film 32b, which is a subsequent process, is formed in the patterning process of the semiconductor film 31. The pattern size must be optimally set according to the physical properties of the coating liquid used in the process, coating conditions, and the required film thickness of the insulating film 32b.
[0024]
As a specific manufacturing procedure, as shown in FIG. 2, first, a semiconductor film is formed on the entire surface of the substrate (step S1; semiconductor film forming step), and then this semiconductor film is patterned to form each pixel. An island-shaped semiconductor film is formed on the substrate (semiconductor film patterning step).
[0025]
At this time, first, the overall size of the semiconductor film disposed in one pixel and the thickness of the gate insulating film are determined based on the required performance of the transistor (step S2). Next, the required thickness of the insulating film 32b is determined according to the thickness of the gate insulating film, and the physical properties and coating conditions of the coating solution are determined so as to obtain this thickness (step S3). If such conditions are determined, for example, experimental data or the like determines the maximum size of the semiconductor film that does not swell on the film surface of the coating film, or is allowed to be swelled. For example, if the overall size of the semiconductor film is not larger than the maximum size, this overall size is used as the pattern size of the semiconductor film as it is, and when the overall size is larger than the maximum size, it is within one pixel. The semiconductor film is divided into a plurality of parts to reduce the pattern size of each semiconductor film. Thus, the number and pattern size of the semiconductor films arranged in one pixel are determined (step S5), and the semiconductor film formed in step S1 is actually patterned (step S6).
[0026]
Thereafter, the surface of the semiconductor film 31 patterned in step S6 is oxidized to form an insulating film 32a (step S7; second insulating film forming step). Further, a coating method is applied on the insulating film 32a. The insulating film 32b is formed (step S8; first insulating film forming step). Then, a transistor is manufactured by patterning the gate electrode 33a on the gate insulating film 32 thus formed (step S9; gate electrode forming step).
[0027]
Hereinafter, these steps will be described in detail with reference to FIGS.
First, as shown in FIG. 3, a base insulating film 11 made of a silicon oxide film is formed on a substrate body 10A made of glass or the like by plasma CVD using TEOS (tetraethoxysilane) or oxygen gas as a raw material. . In addition to the silicon oxide film, a silicon nitride film or a silicon oxynitride film may be provided as the base insulating film. The base insulating film 11 is intended to condition the surface state of the substrate 10A and prevent contamination of the semiconductor film 31 due to impurities in the substrate 10A, but this may be omitted.
[0028]
Next, a semiconductor film made of an amorphous silicon film is formed on the base insulating film 11 using a plasma CVD method or the like. The semiconductor film is not limited to an amorphous silicon film, and may be a semiconductor film including an amorphous structure such as a microcrystalline semiconductor film. Alternatively, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. Subsequently, the semiconductor film is subjected to a crystallization process such as a laser annealing method or a rapid heating method (such as a lamp annealing method or a thermal annealing method) to crystallize the semiconductor film into a polysilicon film (formation of a semiconductor film). Process). In the laser annealing method, for example, a line beam having a long beam length of 400 mm is used with an excimer laser, and the output intensity is, for example, 400 mJ / cm. 2 And Note that the second harmonic or the third harmonic of the YAG laser may be used. With respect to the line beam, it is preferable to scan the line beam so that a portion corresponding to 90% of the peak value of the laser intensity in the short dimension direction overlaps each region.
[0029]
Next, as shown in FIG. 4, the semiconductor film 310 is patterned to a desired size (semiconductor film patterning step). At this time, in order to form a film with good flatness in the formation process of the insulating film 32b as the next process, the pattern size of the semiconductor film 310 is limited within a certain range in accordance with the above-described procedure. For example, in this example, in order to obtain a desired film thickness in the insulating film 32b, the viscosity of the coating liquid, the surface tension, the rotation speed of the spin coat, and the rotation time are determined, and an allowable semiconductor is determined based on these conditions. Determine the maximum size of the membrane. Specifically, the sizes W1 and W2 of one side of the semiconductor film 31 are set to 50 μm or less, and according to this, two semiconductor films 31 are patterned in one pixel. Thus, by forming the semiconductor film into a plurality of parts in one pixel, the required performance of the transistor can be satisfied as a whole while reducing the size of each semiconductor film 31.
[0030]
Next, a method for manufacturing a transistor using one of the semiconductor films 31 shown in FIG. 4 will be described with reference to FIGS. 5 and 6 are diagrams showing a part of FIG. 4 taken out to a different scale, and a part of the substrate 10 in each step corresponds to the cross-sectional view of the liquid crystal display device shown in FIG. It shows.
[0031]
When the patterning of the semiconductor film 310 is completed, as shown in FIG. 5A, the substrate is irradiated with UV light in an oxygen-containing gas atmosphere to decompose and remove contaminants (such as organic substances) present on the substrate surface. Here, as the UV light to be irradiated, a low-pressure mercury lamp having a peak intensity at a wavelength of 254 nm or an excimer lamp having a peak intensity at a wavelength of 172 nm is used. The light in this wavelength range is oxygen molecules (O 2 ) Ozone (O 3 ), And this ozone is further converted into oxygen radicals (O * Therefore, organic substances adhering to the substrate surface can be efficiently removed by using the highly active ozone and oxygen radicals generated in this manner.
[0032]
Next, as shown in FIG. 5B, the substrate is heated to 200 ° C. to 500 ° C., and the substrate is irradiated with UV light in an oxygen-containing gas atmosphere, and oxygen radicals (O * ). Then, the surface of the semiconductor film 31 is oxidized by oxygen radicals to form a silicon oxide film (second insulating film) 32a (second insulating film forming step). The UV light to be irradiated has a peak with a wavelength of 254 nm or less. As described above, light in this wavelength region is oxygen molecules (O 2 ) Ozone (O 3 ) And this ozone is further converted into oxygen radicals (O * ). In addition, light having a wavelength of 175 nm or less emits oxygen molecules (O 2 ) Directly, and oxygen radicals (O * ) Is generated. Then, such active oxygen radicals are generated on the surface of the substrate heated to a high temperature, whereby the surface of the semiconductor film 31 is oxidized and an insulating film 32a is formed.
[0033]
Here, the light source that emits the UV light may be any light source that can emit light having the above-described wavelength component. For example, a light source having a plurality of line spectra such as a low-pressure mercury lamp, an excimer lamp, or an excimer lamp. Those having a monochromatic spectrum such as a laser and those having a continuous spectrum such as a xenon flash lamp are used. Examples of the excimer laser include a krypton fluoride laser having a central wavelength of 248 nm and an argon fluoride laser having a central wavelength of 193 nm.
In addition, the substrate may be heated by a resistance heating method such as a hot plate, or may be heating using the energy of light to be irradiated. When the substrate is heated using light energy, light having a wavelength component suitable for heating the substrate is preferable. By using the energy of the irradiated light to heat the substrate, the efficiency of energy utilization can be improved. That is, the energy of light that has not been used to generate oxygen radicals can be efficiently used for heating the substrate. Further, other heating means using resistance heating or the like is not required, and the apparatus can be simplified. Note that the substrate may be heated by combining the resistance heating method and the light energy heating method.
[0034]
In this process, since oxygen radicals are generated without using plasma, the film surface is less damaged, and a high-quality interface with the semiconductor film 31 can be formed. In addition, this method can simplify the apparatus configuration as compared with the case where oxygen radicals are generated by plasma, and has an advantage that the processing time can be shortened because the space in which the substrate is disposed does not need to be set to a vacuum pressure.
[0035]
Next, as shown in FIG. 5C, a silicon oxide film (first insulating film) 32b is formed on the insulating film 32a (first insulating film forming step). The insulating film 32b is formed by spin-coating a coating solution in which polysilazane is mixed with xylene on a substrate and then performing heat treatment. At this time, the physical properties (viscosity and surface tension) of the coating solution and the conditions for spin coating are those previously determined in the patterning step described above. For example, a coating solution obtained by mixing 10% polysilazane in xylene is spin-coated at a rotation speed of 1500 rpm, and prebaking is performed at a processing temperature of 100 ° C. for 5 minutes. After this, the processing temperature is set to 350 ° C. and WET O 2 Heat treatment is performed in an atmosphere for 260 minutes. Thereby, a silicon oxide film having a thickness of 150 nm is formed. In this way heat treatment WET O 2 By performing in an atmosphere, the nitrogen component in the insulating film that causes polarization can be reduced.
[0036]
Next, as shown in FIG. 6A, on the insulating film 32b, doped silicon, a silicide film, aluminum (Al), tantalum (Ta), molybdenum (Mo), titanium (Ti), tungsten ( W), copper (Cu), chromium (Cr), etc., or a gate electrode forming conductive film made of an alloy containing these metals is formed, and then the conductive film is patterned to scan lines 33 and gate electrodes. 33a is formed (step of forming a gate electrode). Note that the gate electrode 33a may be formed using a single-layer conductive film or a stacked structure.
Next, an impurity element is doped using the gate electrode 33a as a mask. As a result, the source part 31b and the drain part 31c are formed in the semiconductor film 31 in a self-aligned manner with respect to the gate electrode 33a. A region covered with the gate electrode 33a and not doped with impurities becomes the channel portion 31a.
[0037]
Next, as shown in FIG. 6B, the interlayer insulating film 12 is formed so as to cover the gate insulating film 32 and the gate electrode 33a. As the interlayer insulating film 12, for example, an insulating film containing silicon such as a silicon oxynitride film or a silicon oxide film can be used.
[0038]
Subsequently, as shown in FIG. 6C, a part of the interlayer insulating film 12 is opened, and contact holes 12a and 12b are formed at positions corresponding to the source part 31b and the drain part 31c of the semiconductor film 31, respectively. Next, a metal film such as an aluminum film, a chromium film or a tantalum film is formed so as to cover the inner walls of the contact holes 12a and 12b, and a source electrode (signal line) 34 and a drain electrode (intermediate layer) 35 are formed by patterning. Form.
Through the above steps, the transistor 30 is manufactured.
[0039]
Thus, in this embodiment, since the insulating film 32b is a coating film, the unevenness on the substrate generated in the semiconductor film patterning step can be planarized by the insulating film 32b. Thereby, the film thickness uniformity of the gate insulating film 32 is increased, and a transistor having a high breakdown voltage and a small leakage current is obtained. In particular, in the present embodiment, in consideration of the influence of the size of the semiconductor film 31 on the flatness of the coating film, the pattern size is limited within a certain range in the semiconductor film patterning process in advance. Can be made more uniform.
In this embodiment, since the gate insulating film 32 is a laminated film of the insulating film 32 b as the coating film and the insulating film 32 a that is the surface oxide film of the semiconductor film 31, the gate insulating film 32 is excellent between the semiconductor film 31. Interfacial properties are obtained.
[0040]
[Electronics]
Next, specific examples of an electronic device including the liquid crystal device of the present invention will be described.
FIG. 7 is a perspective view showing an example of a portable information processing apparatus such as a word processor or a personal computer. In FIG. 8, reference numeral 1200 denotes an information processing apparatus, reference numeral 1202 denotes an input unit such as a keyboard, reference numeral 1204 denotes an information processing apparatus body, and reference numeral 1206 denotes a display unit using the above-described liquid crystal device.
Since the electronic device shown in FIG. 7 includes a display unit using the liquid crystal device of the above embodiment, high-quality display is possible by reliable switching.
[0041]
In addition, this invention is not limited to the above-mentioned embodiment, It can implement in various deformation | transformation in the range which does not deviate from the meaning of this invention.
For example, in the above embodiment, the gate insulating film 32 has a two-layer structure of the surface oxide film 32a of the semiconductor film 31 and the insulating film 32b that is a coating film, but this may be a multilayer film of three or more layers. . For example, the third insulating film is formed at the interface with the gate electrode 33a by vapor deposition or the like, whereby the electrical characteristics of the transistor can be further stabilized. Of course, when good interface characteristics can be obtained only by the first insulating film 32b, the second insulating film 32a and the third insulating film described above are omitted, and the gate insulating film 32 is made of only the insulating film 32b. A single-layer structure is also possible.
[0042]
4 shows an example in which the semiconductor film is divided into two parts within one pixel, the semiconductor film may be divided into three or more instead. Of course, when the entire size of the semiconductor film determined in step S2 in FIG. 2 is sufficiently small, the semiconductor film can be provided alone without being divided.
In the above embodiment, the liquid crystal device has been described as an example of the electro-optical device. However, the present invention is applied to various devices such as an organic EL display device and an electrophoretic display device. Can do.
[Brief description of the drawings]
FIG. 1 is a diagram showing a main structure of a liquid crystal device according to an embodiment of the invention.
FIG. 2 is a flowchart for explaining a manufacturing procedure of a transistor.
FIG. 3 is a process diagram for describing a method for manufacturing a transistor of the present invention.
FIG. 4 is a process diagram following FIG. 3;
FIG. 5 is a process diagram following FIG. 4;
FIG. 6 is a process diagram following FIG. 5;
FIG. 7 illustrates an example of an electronic device of the invention.
FIG. 8 is a diagram for explaining the influence of the size of a semiconductor film on the film thickness uniformity of a gate insulating film;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device (electro-optical device), 10A ... Substrate, 31 ... Semiconductor film, 32 ... Gate insulating film, 32a ... Second insulating film, 32b ... First insulating film, 33a ... Gate electrodes, 1200 ... Electronic equipment

Claims (9)

基板上に半導体膜を形成する工程と、前記半導体膜を島状にパターニングする工程と、前記半導体膜の上にゲート絶縁膜を形成する工程と、前記ゲート絶縁膜の上にゲート電極を形成する工程とを備え、
前記ゲート絶縁膜の形成工程は、前記ゲート絶縁膜の少なくとも一部を構成する第1の絶縁膜を塗布法により形成する工程を含み、前記半導体膜のパターニング工程では、前記第1の絶縁膜の形成工程で使用する塗布液の物性、塗布条件及び必要とされる前記第1の絶縁膜の膜厚に応じて前記半導体膜のパターンサイズを設定することを特徴とするトランジスタの製造方法。
Forming a semiconductor film on the substrate; patterning the semiconductor film in an island shape; forming a gate insulating film on the semiconductor film; and forming a gate electrode on the gate insulating film. A process,
The step of forming the gate insulating film includes a step of forming a first insulating film constituting at least a part of the gate insulating film by a coating method. In the patterning step of the semiconductor film, the step of forming the first insulating film A method for manufacturing a transistor, characterized in that a pattern size of the semiconductor film is set in accordance with physical properties of a coating liquid used in a forming step, coating conditions, and a required thickness of the first insulating film.
上記半導体のパターニング工程では、上記第1の絶縁膜の形成工程で使用する塗布液の物性,塗布条件,及び必要とされる第1の絶縁膜の膜厚に応じて、許容される半導体膜の最大サイズを決定するとともに、半導体膜の全体サイズをトランジスタの要求性能に基づいて求め、この全体サイズが上記最大サイズよりも大きくなる場合には、上記半導体膜を複数に分割して形成し、個々の半導体膜のサイズを上記最大サイズ以下とすることを特徴とする請求項1記載のトランジスタの製造方法。  In the semiconductor patterning step, an allowable semiconductor film is formed according to the physical properties of the coating liquid used in the first insulating film forming step, the coating conditions, and the required thickness of the first insulating film. In addition to determining the maximum size, the total size of the semiconductor film is obtained based on the required performance of the transistor. If the total size is larger than the maximum size, the semiconductor film is divided into a plurality of parts, 2. The method of manufacturing a transistor according to claim 1, wherein the size of the semiconductor film is not more than the maximum size. 前記第1の絶縁膜の形成工程は、スピンコート法により行なわれることを特徴とする請求項1又は2に記載のトランジスタの製造方法。  3. The method for manufacturing a transistor according to claim 1, wherein the step of forming the first insulating film is performed by a spin coating method. 前記第1の絶縁膜の形成工程は、前記半導体膜上にポリシラザンを塗布し、これを熱処理により酸化シリコンに転化させることにより行なわれることを特徴とする請求項1〜3のいずれかの項に記載のトランジスタの製造方法。  4. The method according to claim 1, wherein the forming step of the first insulating film is performed by applying polysilazane on the semiconductor film and converting it into silicon oxide by heat treatment. The manufacturing method of the transistor of description. 前記熱処理はWET O2雰囲気下で行なわれることを特徴とする請求項4に記載のトランジスタの製造方法。The method for manufacturing a transistor according to claim 4, wherein the heat treatment is performed in a WET O 2 atmosphere. 前記ゲート絶縁膜の形成工程は、前記第1の絶縁膜の形成工程前に前記半導体膜を表面酸化することで前記ゲート絶縁膜の一部を構成する第2の絶縁膜を形成する工程を含むことを特徴とする請求項1〜5のいずれかの項に記載のトランジスタの製造方法。  The step of forming the gate insulating film includes a step of forming a second insulating film constituting a part of the gate insulating film by subjecting the semiconductor film to surface oxidation before the step of forming the first insulating film. The method for producing a transistor according to claim 1, wherein: 前記第2の絶縁膜の形成工程は、酸素含有ガスを処理ガスとして前記半導体膜の表面をプラズマ処理することにより行なわれることを特徴とする請求項6に記載のトランジスタの製造方法。  The method for manufacturing a transistor according to claim 6, wherein the forming step of the second insulating film is performed by performing plasma processing on a surface of the semiconductor film using an oxygen-containing gas as a processing gas. 前記第2の絶縁膜の形成工程は、酸素含有ガス雰囲気下で前記半導体膜に紫外線を照射することにより行なわれることを特徴とする請求項6に記載のトランジスタの製造方法。  7. The method for manufacturing a transistor according to claim 6, wherein the step of forming the second insulating film is performed by irradiating the semiconductor film with ultraviolet rays in an oxygen-containing gas atmosphere. 前記ゲート絶縁膜の形成工程は、前記半導体膜との界面又は前記ゲート電極との界面に、前記ゲート絶縁膜の一部を構成する第2の絶縁膜を蒸着法により形成する工程を含むことを特徴とする請求項1〜5のいずれかの項に記載のトランジスタの製造方法。  The step of forming the gate insulating film includes a step of forming a second insulating film constituting a part of the gate insulating film by an evaporation method at an interface with the semiconductor film or an interface with the gate electrode. The method for producing a transistor according to claim 1, wherein the transistor is a transistor.
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