JP4025372B2 - Semiconductor device - Google Patents

Abstract

A semiconductor process for a laminated package that contains a semiconductor chip on which at least a CPU and flash memory are formed and one or more semiconductor chips on which at least DRAMs are formed. The process comprises the steps of: patterning conductive layers formed on the tape carriers so that leads may protrude into device holes on one side and connected to the through holes in tape carriers on the other side; sealing the semiconductor chips with a resin after the leads are bonded to the terminals of the chips for electrical connections; stacking the tape carriers with their through holes aligned and filling conductor in the through holes for electrical connections; and forming external terminals connected with the through holes on one end.

Description

【０１３４】
図２７、図２８に示すように、チップＭＦ、ＡＤに共通の接続端子は、チップＭＦ、ＡＤのほぼ同じ位置に配置されている。これにより、テープキャリア２ａ、２ｂのリード５ａ、５ｂの引き回しが容易になり、リード長が短縮できるので、チップＭＦ、ＡＤのデータ転送を高速化することができる。また、必要なスルーホール８ａ、８ｂの数を最小限にすることができるので、テープキャリア２ａ、２ｂの外径寸法を縮小してパッケージサイズを小型化することができる。
【０１３５】
特に限定はされないが、本実施の形態の積層型ＴＣＰを構成する各部材は、次のような材料および寸法で構成されている。
【０１３６】
テープキャリア２ａ、２ｂは、厚さ７５μｍのポリイミド樹脂フィルムで構成されている。リード５ａ、５ｂは厚さ１８μｍのＣｕ（銅）箔で構成され、それらの一端部（インナーリード部）の表面には、Ａｕ（金）またはＳｎ（錫）のメッキが施されている。接着剤１０はポリイミド樹脂で構成され、その膜厚は１２μｍである。ソルダーレジスト７はエポキシ樹脂で構成され、その膜厚は２０μｍである。外部接続端子である半田バンプ９とスルーホール８ａ、８ｂ内の半田１１は鉛（Ｐｂ）−錫（Ｓｎ）合金で構成されている。チップＭＦおよびチップＡＤは厚さ５０μｍの単結晶シリコンで構成されており、それらの主面を保護するポッティング樹脂６はエポキシ樹脂で構成されている。チップＭＦおよびチップＡＤの主面に形成されたバンプ電極４はＡｕで構成され、その高さは２０μｍである。すなわち、この積層型ＴＣＰは、チップＭＦとバンプ電極４の合計の厚さがテープキャリア２ａの厚さよりも薄く、チップＡＤとバンプ電極４の合計の厚さがテープキャリア２ｂの厚さよりも薄く構成されているので、半田バンプ９を除いた部分の積層方向の厚さが２１８μｍという超薄型のパッケージになっている。
【０１３７】
次に、本実施の形態の積層型ＴＣＰの製造方法を図２９〜図３７を用いて説明する。なお、図２９〜図３３の（ａ）はＴＣＰ１Ｂの断面図、（ｂ）はＴＣＰ１Ａの断面図である。
【０１３８】
まず、図２９に示すように、ポリイミド樹脂フィルムからなるテープキャリア２ａ、２ｂを用意し、それらを打ち抜いてテープキャリア２ａにデバイスホール３ａとスルーホール８ａとを形成し、テープキャリア２ｂにデバイスホール３ｂとスルーホール８ｂとを形成する。なお、これらのテープキャリア２ａ、２ｂは、リールに巻かれた長尺のフィルムになっているが、図にはその一部分（ＴＣＰ１Ａ、１Ｂ各１個分）のみを示す。
【０１３９】
次に、図３０に示すように、テープキャリア２ａ、２ｂのそれぞれの一面にＣｕ箔をラミネートした後、このＣｕ箔をウェットエッチングしてテープキャリア２ａにリード５ａを形成し、テープキャリア２ｂにリード５ｂを形成する。また同時に、スルーホール８ａの一端部にＣｕ箔ホール１２ａを形成し、スルーホール８ｂの一端部にＣｕ箔ホール１２ｂを形成する。後の工程でスルーホール８ａ、８ｂの内部に充填する半田（１１）とリード５ａ、５ｂとの接触面積を確保してスルーホール断線を防止するため、Ｃｕ箔ホール１２ａの径はスルーホール８ａよりも小さくし、Ｃｕ箔ホール１２ｂの径はスルーホール８ｂよりも小さくする。また、Ｃｕ箔はポリイミド樹脂製のテープキャリア２ａ、２ｂに比べて熱膨張係数が小さく、寸法安定性が高いので、Ｃｕ箔ホール１２ａ、１２ｂの径をスルーホール８ａ、８ｂよりも小さくしておくと、後の工程でスルーホール８ａ、８ｂを利用してテープキャリア２ａとテープキャリア２ｂとを重ね合わす際の位置決めを高精度に行うことができる。
【０１４０】
次に、図３１に示すように、テープキャリア２ａのデバイスホール３ａ内に突出するリード５ａの一端部（インナーリード部）の表面と、テープキャリア２ｂのデバイスホール３ｂ内に突出するリード５ｂの一端部（インナーリード部）の表面とに電解メッキ法でＡｕまたはＳｎのメッキを施した後、テープキャリア２ａの下面にソルダーレジスト７を被着し、テープキャリア２ｂの下面に接着剤１０を被着する。
【０１４１】
次に、図３２に示すように、チップＭＦの接続端子に形成しておいたバンプ電極４とテープキャリア２ａのリード５ａをギャングボンディング方式で一括して接続する。また、チップＡＤの接続端子に形成しておいたバンプ電極４とテープキャリア２ｂのリード５ｂをギャングボンディング方式で一括して接続する。チップＭＦおよびチップＡＤは、あらかじめウエハ状態で裏面を研磨した後、スピンエッチング法で厚さを５０μｍまで薄くしておく。バンプ電極４は、スタッドバンプボンディング法を用い、ウエハプロセスの最終工程で形成する。リード５ａ、５ｂのインナーリード部にはＡｕまたはＳｎのメッキが施されているので、リード５ａとバンプ電極４およびリード５ｂとバンプ電極４は、Ａｕ−Ａｕ接合またはＡｕ−Ｓｎ共晶接合により接合される。リード５ａ、５ｂとバンプ電極４との接合は、ギャングボンディング方式に代えてシングルポイントボンディング方式で行ってもよい。
【０１４２】
次に、図３３に示すように、樹脂ポッティング用のディスペンサを使用してチップＭＦの主面およびテープキャリア２ａとデバイスホール３ａとの隙間にポッティング樹脂６を被着する。同様に、チップＡＤの主面およびテープキャリア２ｂとデバイスホール３ｂとの隙間にポッティング樹脂６を被着する。
【０１４３】
次に、切断金型を使用して長尺のテープキャリア２ａ、２ｂを個片化した後、個々のテープキャリア２ａ、２ｂをソケットに装着してエージング検査に付し、良品を選別する。テープキャリア２ａ、２ｂのエージングは、テープキャリア２ａ、２ｂの各一部に形成しておいたテスト用のパッドにソケットのピンを当てて行う。ここまでの工程で、チップＭＦを封止したＴＣＰ１ＡおよびチップＡＤを封止したＴＣＰ１Ｂが略完成する。
【０１４４】
次に、図３４に示すように、向かい合ったスルーホール８ａ、８ｂの位置が正確に一致するようにテープキャリア２ａ、２ｂを重ね合わせて加熱圧着し、接着剤１０で両者を接合することにより、ＴＣＰ１Ａ、１Ｂをワンパッケージ化する。前述したように、チップＭＦはテープキャリア２ａよりも薄く、チップＡＤはテープキャリア２ｂよりも薄いので、ＴＣＰ１ＡとＴＣＰ１Ｂを密に接合することができる。スルーホール８ａとスルーホール８ｂとの位置決めには、前述したＣｕ箔ホール１２ａ、１２ｂを利用する。あるいは、テープキャリア２ａ、２ｂの各一部に形成しておいたテスト用のパッドを利用してもよい。
【０１４５】
次に、図３５に示すように、鉛（Ｐｂ）−錫（Ｓｎ）合金からなる半田ペーストをスルーホール８ａ、８ｂの内部にスクリーン印刷法で埋め込んだ後、この半田ペーストをリフローして半田１１を形成する。
【０１４６】
その後、テープキャリア２ａのスルーホール８ａの一端部に半田バンプ９を形成することにより、前記図１、図２に示す積層型ＴＣＰが完成する。半田バンプ９は、テープキャリア２ａの半田バンプ形成面を上向きにした状態で、あらかじめ形成しておいた半田ボールをスルーホール８ａの上に位置決めし、その後、この半田ボールをリフローして形成する。あるいは、ガラス基板の表面に並べた半田バンプをスルーホール８ａの表面に転写して形成してもよい。半田バンプ９は、スルーホール８ａ、８ｂの内部に充填した半田１１よりも低融点の鉛（Ｐｂ）−錫（Ｓｎ）合金で構成する。
【０１４７】
このようにして製造された積層型ＴＣＰをプリント配線基板に実装するには、図３６に示すように、上記半田バンプ９をプリント配線基板１４の電極１５上に位置決めし、その後、半田バンプ９をリフローすればよい。
【０１４８】
本実施の形態の積層型ＴＣＰは、チップＭＦ、ＡＤから発生した熱が主に半田バンプ９を通じて基板に逃げるので、ＴＣＰ１Ａ、１Ｂを積層する場合は、発熱量がより多いチップを下側（基板に近い側）に配置する。上記の例では、フラッシュメモリ搭載マイクロコンピュータを形成したチップＭＦの方がＤＲＡＭオンチップロジックを形成したチップＡＤに比べて機能ブロックの数が多く、発熱量も多いので、チップＡＤの下側にチップＭＦが配置されている。また、接続端子数が多いチップを下側（基板側）に配置することにより、チップの接続端子と外部接続端子とを接続する配線の引き回しが容易になる。
【０１４９】
また、このように発熱量が大きい、システムオンチップ化を図った積層型モジュールにおいては、チップＡＤに形成されるＤＲＡＭのメモリセルは、積層型キャパシタ（ＳＴＣ）構造を採用することが好ましい。積層型キャパシタ構造は、プレーナ型キャパシタ構造に比べて熱的リーク電流が少なく、熱的信頼性が高いからである。さらに、積層型キャパシタ構造は、リフレッシュサイクルを長くすることができるので、発熱量を抑えることも可能である。
【０１５０】
チップの発熱量が非常に多い場合は、図３７に示すように、積層型ＴＣＰの上部にＡｌのような熱伝導率の高い金属で構成した放熱フィン１６を取り付けてもよい。この場合は、チップＡＤの上部（放熱フィン１６に近い側）に発熱量が多いチップＭＦを配置する。
【０１５１】
次に、本発明のパッケージの他の実施の形態について説明する。
【０１５２】
前述した製造方法では、ＴＣＰ１ＡとＴＣＰ１Ｂを重ね合わせた後、向かい合ったスルーホール８ａ、８ｂの内部に半田１１を埋め込んだ（図３４、３５参照）が、次のような方法でＴＣＰ１Ａ、１Ｂをワンパッケージ化してもよい。
【０１５３】
まず、図３８に示すように、前述した方法に従ってＴＣＰ１ＡとＴＣＰ１Ｂを個別に形成する。次に、図３９に示すように、ＴＣＰ１Ａのスルーホール８ａの内部に半田ペースト１１ｐを埋め込み、ＴＣＰ１Ｂのスルーホール８ｂの内部に半田ペースト１１ｐを埋め込む。半田ペースト１１ｐの埋め込みには、スクリーン印刷法を用いる。
【０１５４】
次に、図４０に示すように、テープキャリア２ａ、２ｂを重ね合わせて加熱圧着し、接着剤１０で両者を接合すると共に、半田ペースト１１ｐをリフローしてスルーホール８ａ、８ｂの内部に半田１１を形成する。その後の工程は、前記の製造方法と同じである。
【０１５５】
この製造方法は、ＴＣＰ１ＡとＴＣＰ１Ｂが半田ペースト１１ｐの粘着力で仮付けされるため、重ね合わせたＴＣＰ１Ａ、１Ｂを加熱炉などに搬送して両者を加熱圧着するまでの間、向かい合ったスルーホール８ａ、８ｂの位置ずれを防止することができる。
【０１５６】
スルーホール８ａ、８ｂの他の形成方法として、テープキャリア２ａ、２ｂを重ね合わせてＴＣＰ１Ａ、１Ｂをワンパッケージ化した後、ドリルを使ってテープキャリア２ａ、２ｂに孔を形成し、次いで孔の内部に無電解メッキ法で導電層を形成してもよい。
【０１５７】
また、チップＭＦ、ＡＤの封止は、前記のポッティング方式に代えてトランスファモールド方式で行うこともできる。この場合は、まず図４１に示すように、前述した方法に従ってチップＭＦのバンプ電極４とテープキャリア２ａのリード５ａを電気的に接続し、チップＡＤのバンプ電極４とテープキャリア２ｂのリード５ｂを電気的に接続する。
【０１５８】
次に、図４２に示すように、チップＭＦ、ＡＤをモールド樹脂１７で封止する。チップＭＦ、ＡＤを封止するには、テープキャリア２ａ、２ｂをそれぞれモールド金型に装着し、複数個のチップＭＦ、ＡＤをそれぞれ多連で一括して封止する。モールド樹脂１７には、エポキシ系の樹脂を使用する。
【０１５９】
図示の例では、チップＭＦ、ＡＤの全面をモールド樹脂１７で被覆しているが、チップＭＦ、ＡＤの裏面をモールド樹脂１７から露出させる構造にしてもよい。その場合、通常のトランスファモールド方式ではなく、シート状に加工した樹脂をテープキャリア２ａ、２ｂの上面に当てて加熱圧着することにより、チップＭＦ、ＡＤの主面および側面に樹脂を流し込むこともできる。ただし、この方式では、テープキャリア２ａ、２ｂの上面から樹脂がはみ出すことがないよう、樹脂の流し込み量を高精度に制御する必要がある。
【０１６０】
なお、本発明のパッケージは、チップＭＦ、ＡＤを封止するモールド樹脂１７の厚みが極めて薄いので、チップＭＦ、ＡＤの裏面をモールド樹脂１７から露出させる場合や、チップＭＦ、ＡＤの全面をモールド樹脂１７で被覆する構造で、チップＭＦ、ＡＤの主面と裏面とでモールド樹脂１７の厚さに偏りがある場合には、チップＭＦ、ＡＤとモールド樹脂１７の熱膨張係数に差があるとＴＣＰ１Ａ、１Ｂに反りが発生し、チップクラックや基板実装時の接続不良を引き起こす。従って、モールド樹脂１７は熱膨張係数が低く、チップＭＦ、ＡＤの熱膨張係数に近い材料を選定する必要がある。
【０１６１】
次に、切断金型を使用してテープキャリア２ａ、２ｂを個片化し、個々のＴＣＰ１Ａ、１Ｂをエージング検査に付して良品を選別した後、図４３に示すように、向かい合ったスルーホール８ａ、８ｂの位置が正確に一致するようにテープキャリア２ａ、２ｂを重ね合わせて加熱圧着し、接着剤１０で両者を接合する。その後、前述した方法に従ってスルーホール８ａ、８ｂの内部に半田１１を形成し、さらにテープキャリア２ａのスルーホール８ａの一端部に半田バンプ９を形成することにより、積層型ＴＣＰが完成する。あるいは、図４４に示すように、ＴＣＰ１Ａのスルーホール８ａの内部とＴＣＰ１Ｂのスルーホール８ｂの内部にそれぞれ半田１１を充填した後にＴＣＰ１Ａ、１Ｂを積層してワンパッケージ化してもよい。
【０１６２】
チップＭＦとチップＡＤは、両者を同時に一括してモールド樹脂１７で封止してもよい。この場合は、まず図４５に示すように、前述した方法に従ってチップＭＦのバンプ電極４とテープキャリア２ａのリード５ａを電気的に接続し、チップＡＤのバンプ電極４とテープキャリア２ｂのリード５ｂを電気的に接続した後、テープキャリア２ａ、２ｂを重ね合わせて加熱圧着し、接着剤１０で両者を接合する。次に、図４６に示すように、チップＭＦ、ＡＤをモールド樹脂１７で同時に封止した後、図４７に示すように、前述した方法に従ってスルーホール８ａ、８ｂの内部に半田１１を形成し、さらにテープキャリア２ａのスルーホール８ａの一端部に半田バンプ９を形成する。
【０１６３】
チップＭＦ、ＡＤをモールド樹脂１７で封止する上記の方式によれば、チップＭＦ、ＡＤをポッティング樹脂６で封止する方式に比べて、封止部の外径寸法精度が向上するため、寸法安定性の高い均一な形状の積層型ＴＣＰを製造することができる。また、複数個のチップＭＦ、ＡＤを多連で一括して封止することにより、封止時間を短縮することができる。さらに、モールド樹脂１７の厚みをテープキャリア２ａ、２ｂと同じにすることにより、ＴＣＰ１ＡとＴＣＰ１Ｂの間に隙間ができないので、ＴＣＰ１ＡとＴＣＰ１Ｂの間に水分が溜まるなどの不具合を防止することができ、信頼性の高い積層型ＴＣＰを製造することができる。
【０１６４】
本発明の積層型ＴＣＰは、半田バンプ９で外部接続端子を構成する方式に代えて、リード５ａ、５ｂで外部接続端子を構成することもできる。この積層型ＴＣＰの製造方法を図４８〜図５３を用いて説明する。
【０１６５】
まず、図４８に示すように、ポリイミド樹脂フィルムからなるテープキャリア２ａ、２ｂを打ち抜いてテープキャリア２ａにデバイスホール３ａを形成し、テープキャリア２ｂにデバイスホール３ｂを形成する。これらのテープキャリア２ａ、２ｂには、前記のようなスルーホール８ａ、８ｂは形成しない。
【０１６６】
次に、図４９に示すように、前述した方法に従ってテープキャリア２ａにリード５ａを形成すると共に、テープキャリア２ｂにリード５ｂを形成し、それらの一端部（インナーリード部）の表面にＡｕまたはＳｎのメッキを施した後、テープキャリア２ａの一面にソルダーレジスト７を被着し、テープキャリア２ｂの一面に接着剤１０を被着する。リード５ａ、５ｂは、それらの他端部（アウターリード部）が外部接続端子として利用できるような長さに形成する。
【０１６７】
次に、図５０に示すように、前述した方法に従ってチップＭＦのバンプ電極４とテープキャリア２ａのリード５ａを電気的に接続し、チップＡＤのバンプ電極４とテープキャリア２ｂのリード５ｂを電気的に接続した後、チップＭＦ、ＡＤをポッティング樹脂６で封止する。続いて、テープキャリア２ａ、２ｂを個片化し、個々のＴＣＰ１Ａ、１Ｂをエージング検査に付して良品を選別する。
【０１６８】
次に、図５１に示すように、前述した方法に従ってテープキャリア２ａ、２ｂを重ね合わせて接合することにより、ＴＣＰ１Ａ、１Ｂをワンパッケージ化した後、図５２に示すように、リード５ａ、５ｂの他端部（アウターリード部）を支持しているテープキャリア２ａ、２ｂを切断除去する。
【０１６９】
次に、リード５ａ、５ｂの他端部（アウターリード部）の表面に半田メッキを施した後、図５３に示すように、リード５ａ、５ｂの他端部（アウターリード部）をリード成形金型を使ってガルウィング状に成形する。リード５ａ、５ｂは、同じ金型を使って同時に成形する。
【０１７０】
このようにして製造された積層型ＴＣＰをプリント配線基板に実装するには、図５４に示すように、上記リード５ａ、５ｂの他端部（アウターリード部）をプリント配線基板１４の電極１５上に重ね合わせた後、半田メッキをリフローする。その際、２つのチップＭＦ、ＡＤの共通する接続端子に接続されたリード５ａ、５ｂは、プリント配線基板１４の同じ電極１５に接続する。すなわち、この積層型ＴＣＰは、２つのチップＭＦ、ＡＤの共通する接続端子をリード５ａ、５ｂを通じて電気的に接続し、このリード５ａ、５ｂを介して外部（プリント配線基板）に共通に引き出す構造になっている。
【０１７１】
図示の積層型ＴＣＰは、チップＭＦ、ＡＤの主面を上に向けて配置しているが、下に向けて配置してもよい。また、チップＭＦ、ＡＤをポッティング樹脂６で封止しているが、図５５に示すように、チップＭＦ、ＡＤをモールド樹脂１７で封止してもよい。
【０１７２】
外部接続端子をリード５ａ、５ｂで構成する上記の積層型ＴＣＰによれば、外部接続端子を半田バンプ９で構成する前記の積層型ＴＣＰに比べて、製造工程を簡略化することができるので、積層型ＴＣＰの製造コストを低減することができる。また、テープキャリア２ａ、２ｂにスルーホール５ａ、５ｂを設けなくともよいので、リード５ａ、５ｂの引き回しが容易になると共に、テープキャリア２ａ、２ｂの製造コストを低減することもできる。
【０１７３】
さらに、テープキャリア２ａのリード５ａとテープキャリア２ｂのリード５ｂを同じ金型で同時に成形することにより、外部接続端子の形成に要する時間を短縮することができる。また、リード５ａ、５ｂの他端部（アウターリード部）をプリント配線基板１４の電極１５上に重ね合わせて接続することにより、プリント配線基板１４の表面に占める電極１５の面積を小さくすることができると共に、積層型ＴＣＰの実装（リード５ａ、５ｂと電極１５の接続）を１回で行うことができる。
【０１７４】
外部接続端子を構成する上記リード５ａ、５ｂは、２つの金型を使って個別に成形してもよい。この場合も、図５６（チップＭＦ、ＡＤをポッティング樹脂６で封止した構造）および図５７（チップＭＦ、ＡＤをモールド樹脂１７で封止した構造）に示すように、２つのチップＭＦ、ＡＤの共通する接続端子に接続されたリード５ａ、５ｂをプリント配線基板１４の同じ電極１５に接続する。
【０１７５】
図５８に示す積層型ＴＣＰは、下層のＴＣＰ１Ａに形成したリード５ａの他端部（アウターリード部）をガルウィング状に成形して外部接続端子を構成し、ＴＣＰ１ＡとＴＣＰ１Ｂとの電気的な接続は、テープキャリア２ａ、２ｂに形成したスルーホール８ａ、８ｂの内部に埋め込んだ半田１１を通じて行っている。
【０１７６】
ガルウィング状に成形したリードで外部接続端子を構成する上記の構造は、積層型ＴＣＰとプリント配線基板との熱膨張係数差に起因して両者の接続部に加わる応力がフレキシブルなリードの変形によって吸収・緩和されるため、半田バンプで外部接続端子を構成する構造に比べて、基板との接続信頼性が高い。
【０１７７】
本発明のパッケージは、図５９に示すように、ＴＣＰ１ＡとＴＣＰ１Ｂをワンパッケージ化せず、個別にプリント配線基板１４に実装することもできる。この場合は、ＴＣＰ１Ａ、１Ｂをワンパッケージ化した積層型ＴＣＰに比べて実装密度は低下するが、ＴＣＰ１Ａ、１Ｂを積層してワンパッケージ化する工程が不要となるので、パッケージの製造コストを低減することができる。
【０１７８】
本発明の積層型ＴＣＰは、半田バンプ９やリード５ａ、５ｂで外部接続端子を構成する方式に代えて、図６０に示すように、ＰＧＡ(Pin Grid Array)型パッケージで使用されるピン１８で外部接続端子を構成することもできる。ピン１８の表面にはＳｎ（錫）などのメッキが施され、スルーホール８ａ、８ｂの内部においてリード５ａおよび／またはリード５ｂと電気的に接続される。
【０１７９】
また、本発明の積層型ＴＣＰは、異方導電性フィルムを使ってチップＭＦとリード５ａおよびチップＡＤとリード５ｂを接続することもできる。
【０１８０】
異方導電性フィルムを使って積層型ＴＣＰを製造するには、まず、図６１に示すように、前述した方法に従ってテープキャリア２ａにデバイスホール３ａ、スルーホール８ａおよびリード５ａを形成し、テープキャリア２ｂにデバイスホール３ｂ、スルーホール８ａおよびリード５ｂを形成した後、テープキャリア２ａの一面にソルダーレジスト７を被着し、テープキャリア２ｂの一面に接着剤１０を被着する。
【０１８１】
次に、図６２に示すように、あらかじめテープキャリア２ａのデバイスホール３ａとほぼ同じ寸法に裁断しておいた異方導電性フィルム１９ａをデバイスホール３ａの内部に突出するリード５ａの一端部（インナーリード部）の上に位置決めする。同様に、あらかじめテープキャリア２ｂのデバイスホール３ｂとほぼ同じ寸法に裁断しておいた異方導電性フィルムを１９ｂをデバイスホール３ｂの内部に突出するリード５ｂの一端部（インナーリード部）の上に位置決めする。
【０１８２】
次に、図６３に示すように、バンプ電極４が形成されたチップＭＦの主面を下向きにして異方導電性フィルム１９ａの上に位置決めした後、異方導電性フィルム１９ａを加熱加圧することにより、異方導電性フィルム１９ａ中の導電粒子を介してバンプ電極４とリード５ａを電気的に接続する。同様に、バンプ電極４が形成されたチップＡＤの主面を下向きにして異方導電性フィルム１９ｂの上に位置決めした後、異方導電性フィルム１９ｂを加熱加圧することにより、異方導電性フィルム１９ｂ中の導電粒子を介してバンプ電極４とリード５ｂを電気的に接続する。続いて、テープキャリア２ａ、２ｂを個片化し、個々のＴＣＰ１Ａ、１Ｂをエージング検査に付して良品を選別する。
【０１８３】
次に、図６４に示すように、前述した方法に従ってテープキャリア２ａ、２ｂを重ね合わせてＴＣＰ１Ａ、１Ｂをワンパッケージ化した後、図６５に示すように、スルーホール８ａ、８ｂの内部に半田１１を充填し、さらにスルーホール８ａの一端部に半田バンプ９を形成する。
【０１８４】
上述した本発明の各種積層型ＴＣＰは、チップＭＦとチップＡＤを組み合わせる場合だけでなく、前述したチップＭＦＡ＋チップＤ、チップＭＦＡ＋チップＡＤ、チップＭＦ＋チップＤなどの構成例にも適用できることは勿論である。また、本発明の積層型ＴＣＰは、３個以上のチップを積層する場合にも適用することができる。
【０１８５】
図６６に示す積層型ＴＣＰは、マイクロコンピュータとフラッシュメモリを形成したチップＭＦをＴＣＰ１Ａに封止すると共に、ＤＲＡＭのみを形成した２個のチップＤ₁、Ｄ₂を２個のＴＣＰ１Ｃ、ＴＣＰ１Ｄに封止し、これら３個のＴＣＰ１Ａ、１Ｃ、１Ｄを上下方向に重ね合わせて一体に接合した積層型ＴＣＰ構造を有している。
【０１８６】
最下層のＴＣＰ１Ａに封止されたチップＭＦは、テープキャリア２ａのデバイスホール３ａ内にその主面（素子形成面）を上に向けて配置されており、その主面の周辺部に形成されたバンプ電極４を介して、テープキャリア２ａの一面に形成されたリード５ａの一端（インナーリード部）と電気的に接続されている。チップＭＦは、モールド樹脂１７で封止されている。テープキャリア２ａの一面に形成されたリード５ａは、図６７に示すようなパターンを有している。
【０１８７】
ＴＣＰ１Ａの上部には、チップＤ₁を封止したＴＣＰ１Ｃが積層されており、さらにその上部にはチップＤ₂を封止したＴＣＰ１Ｄが積層されている。ＴＣＰ１Ｃに封止されたチップＤ₁は、テープキャリア２ｃの中央部に開孔されたデバイスホール３ｃ内にその主面を上に向けて配置されており、その主面の中央部に形成されたバンプ電極４を介して、テープキャリア２ｃの一面に形成されたリード５ｃの一端（インナーリード部）と電気的に接続されている。同様に、ＴＣＰ１Ｄに封止されたチップＤ₂は、テープキャリア２ｄの中央部に開孔されたデバイスホール３ｄ内にその主面を上に向けて配置されており、その主面の中央部に形成されたバンプ電極４を介して、テープキャリア２ｄの一面に形成されたリード５ｄの一端（インナーリード部）と電気的に接続されている。これらのチップＤ₁、Ｄ₂もモールド樹脂１７で封止されている。テープキャリア２ｃの一面に形成されたリード５ｃは、図６８に示すようなパターンを有しており、テープキャリア２ｄの一面に形成されたリード５ｄは、図６９に示すようなパターンを有している。
【０１８８】
この積層型ＴＣＰは、上記３つのチップＭＦ、Ｄ₁、Ｄ₂の共通する（すなわち同一機能を有する）接続端子（ピン）をテープキャリア２ａ、２ｃ、２ｄの同じ位置に配置されたスルーホール８ａ、８ｃ、８ｄを通じて電気的に接続し、テープキャリア２ａに形成されたリード５ａの他端部（アウターリード部）を通じて外部（プリント配線基板）に共通に引き出す構造になっている。外部接続端子は、リードの他、前述した半田バンプやピンなどで構成できることは勿論である。
【０１８９】
図６７には、チップＭＦに形成された接続端子の番号（１〜１４４）とテープキャリア２ａに形成されたスルーホール８ａの番号（１〜１４４）とが付してある。また、図６８には、チップＤ₁に形成された接続端子の番号（１〜４６）とテープキャリア２ｃに形成されたスルーホール８ｃの番号（１〜１４４）とが付してあり、図６９には、チップＤ₂に形成された接続端子の番号（１〜４６）とテープキャリア２ｄに形成されたスルーホール８ｄの番号（１〜１４４）とが付してある。テープキャリア２ａ、２ｃ、２ｄの同じ位置に配置されたスルーホール８ａ、８ｃ、８ｄには、同じ番号が付してある。
【０１９０】
チップＤ₁、Ｄ₂の面積がいずれもチップＭＦの面積の半分以下である場合は、図７０に示すように、チップＤ₁、Ｄ₂を横に並べて配置し、チップＤ₁、Ｄ₂の共通する接続端子を共通のリード５ｅで接続することができる。このようにすると、２個のチップＭＦ、ＡＤを搭載した前記の積層型ＴＣＰと同様、超薄型のパッケージを実現することができる。
【０１９１】
本発明のパッケージは、上記した構造に限定されるものではなく、その細部に種々の設計変更を加えることができる。例えば図７１に示すように、ＴＣＰ１Ａに封止されたチップＭＦとテープキャリア２ａに形成されたリード５ａをＡｕのワイヤ２０で電気的に接続する構造を採用することもできる。
【０１９２】
また、積層型ＴＣＰ構造以外にも、例えば図７２に示すように、チップＭＦとチップＡＤをワンパッケージ化せず、個別にＱＦＰ(Quad Flat package)型のパッケージに封止してプリント配線基板１４に実装することもできる。
【０１９３】
本発明のパッケージは、マルチメディア機器、情報家電などの機器、システム、例えば図７３に示すようなカーナビゲーションシステム、図７４に示すようなＣＤ−ＲＯＭ(Compact Disk ROM)駆動装置、図７５に示すようなゲーム機器、図７６に示すようなＰＤＡ(Personal Digital Assistance)、図７７に示すような移動体通信機器などに用いられ、以下において、それぞれの概要を説明する。
【０１９４】
図７３は、カーナビゲーションシステムの内部構成例を示す機能ブロック図である。このカーナビゲーションシステムは、制御部と、この制御部に接続された表示部、ＧＰＳおよびＣＤ−ＲＯＭとから構成されている。制御部は、メインＣＰＵ、プログラムＥＰＲＯＭ（４Ｍ）、ワークＲＡＭ（ＳＲＡＭ：１Ｍ）、Ｉ／Ｏ制御回路、ＡＲＴＯＰ、画像用ＲＡＭ（ＤＲＡＭ：４Ｍ）、ＣＧ(Computer Graphics)用ＲＯＭ（マスクＲＯＭ：４Ｍ）、ゲートアレイなどからなり、また表示部はスレーブマイクロコンピュータ、ＴＦＴなどから構成されている。
【０１９５】
このカーナビゲーションシステムにおいて、制御部のメインＣＰＵは、プログラムＥＰＲＯＭに格納されている制御プログラムに従って制御する。まず、制御部は、衛星と地上局との間で車の位置を測定するＧＰＳによる位置情報と、ＣＤ−ＲＯＭに格納されている地図情報とをＩ／Ｏ制御回路、ゲートアレイを介してそれぞれ入力し、これらの情報をワークＲＡＭに格納する。
【０１９６】
そして、ＣＧ用ＲＯＭに格納されている処理プログラムに従い、ワークＲＡＭに格納されている位置情報と地図情報とに基づいて車の位置を地図上に配置する処理などをＡＲＴＯＰにより行い、この画像情報を画像用ＲＡＭに格納する。その後、画像用ＲＡＭに格納されている画像情報を表示部に渡し、表示部においては、スレーブマイクロコンピュータの制御に基づいてＴＦＴによる画面上に画像情報を表示させることにより、車の位置が地図上に配置された画像を表示させることができる。
【０１９７】
このカーナビゲーションシステムにおいては、メインＣＰＵをプロセッサ、プログラムＥＰＲＯＭをフラッシュメモリ、ＡＲＴＯＰなどをＡＳＩＣによるロジック回路で構成することにより、このブロック部分に本実施の形態のチップＭＦＡを使用し、また画像用ＲＡＭをＤＲＡＭ、ゲートアレイをＡＳＩＣによるロジック回路で構成することにより、このブロック部分に本実施の形態のチップＡＤを使用することができる。また単に、メインＣＰＵ、プログラムＥＰＲＯＭの部分にチップＭＦ、画像用ＲＡＭの部分にチップＤを使用することなどもできる。
【０１９８】
図７４は、ＣＤ−ＲＯＭ駆動装置の内部構成例を示す機能ブロック図である。このＣＤ−ＲＯＭ駆動装置は、フラッシュメモリを含むマイクロコンピュータと、このマイクロコンピュータに双方向で接続されたプリサーボ回路、信号処理回路、ＲＯＭデコーダ、ホストＩ／Ｆと、プリサーボ回路、信号処理回路にそれぞれ双方向で接続されたピックアップ、ＳＲＡＭと、ＲＯＭデコーダに接続されたＤ／Ａと、ホストＩ／Ｆに接続されたバッファＲＡＭとなどから構成されている。
【０１９９】
また、信号処理回路にはＣＤ−ＲＯＭを駆動するモータＭが接続され、またＣＤ−ＲＯＭの信号はピックアップにより読み取られる。このモータの回転はプリサーボ回路、信号処理回路の信号により制御される。さらに、Ｄ／Ａにはスピーカが接続されている。また、このＣＤ−ＲＯＭ駆動装置はホストＩ／Ｆを介してホストコンピュータに接続されるようになっている。
【０２００】
このＣＤ−ＲＯＭ駆動装置においては、マイクロコンピュータの制御に基づいて、ＣＤ−ＲＯＭの信号をピックアップにより読み取り、この読み取り情報の処理を信号処理回路により行い、この処理された情報をＳＲＡＭに格納する。さらに、ＳＲＡＭに格納されている情報をＲＯＭデコーダによりデコードして、Ｄ／Ａを介してアナログ信号に変換した後にスピーカから出力することができると共に、バッファＲＡＭに一時的に格納した後にホストＩ／Ｆを介してホストコンピュータに出力することができる。
【０２０１】
このＣＤ−ＲＯＭ駆動装置においては、フラッシュメモリを含むマイクロコンピュータ、信号処理回路などのブロック部分に本実施の形態のチップＭＦＡを使用し、またバッファＲＡＭ、ホストＩ／Ｆのブロック部分に本実施の形態のチップＡＤを使用することができる。また単に、フラッシュメモリを含むマイクロコンピュータの部分にチップＭＦ、バッファＲＡＭの部分にチップＤを使用することなどもできる。
【０２０２】
図７５は、ゲーム機器の内部構成例を示す機能ブロック図である。このゲーム機器は、本体制御部と、本体制御部に接続されたスピーカ、ＣＤ−ＲＯＭ、ＲＯＭカセット、ＣＲＴが接続された表示ＲＡＭ（ＳＤＲＡＭ：４Ｍ）、バッファＲＡＭ（ＤＲＡＭ：４Ｍ）およびキーボードとから構成されている。本体制御部は、メインＣＰＵ、システムＲＯＭ（マスクＲＯＭ：１６Ｍ）、ＤＲＡＭ（ＳＤＲＡＭ：４Ｍ）、ＲＡＭ（ＳＲＡＭ：２５６ｋ）、サウンドプロセッサ、グラフィックプロセッサ、画像圧縮プロセッサ、Ｉ／Ｏ制御回路などから構成されている。
【０２０３】
このゲーム機器において、本体制御部のメインＣＰＵは、システムＲＯＭに格納されている制御プログラムに従って制御する。ＣＤ−ＲＯＭ、ＲＯＭカセットに格納されている画像・音声情報と、キーボードからの指示情報とをＩ／Ｏ制御回路を介してそれぞれ入力し、これらの情報をＤＲＡＭ、ＲＡＭに格納する。
【０２０４】
そして、ＤＲＡＭ、ＲＡＭに格納されている情報をサウンドプロセッサ、グラフィックプロセッサを用いてそれぞれオーディオ、ビデオ信号に処理して、オーディオ信号はスピーカーから音声として出力し、またビデオ信号は表示ＲＡＭに一時的に格納した後にＣＲＴの画面上に画像として表示させることができる。この際に、ビデオ信号は画像圧縮プロセッサにより情報量が圧縮されてバッファＲＡＭに格納されて用いられる。
【０２０５】
このゲーム機器においては、メインＣＰＵ、システムＲＯＭ、サウンドプロセッサ、グラフィックプロセッサなどのブロック部分に本実施の形態のチップＭＦＡを使用し、またＤＲＡＭ、画像圧縮プロセッサなどのブロック部分に本実施の形態のチップＡＤを使用することができる。また単に、メインＣＰＵ、システムＲＯＭの部分にチップＭＦ、ＤＲＡＭ、ＲＡＭ、バッファＲＡＭなどの部分にチップＤを使用することなどもできる。
【０２０６】
図７６は、ＰＤＡの内部構成例を示す機能ブロック図である。このＰＤＡは、グラフィック制御回路、手書き入力回路、メモリ制御回路、セキュリティ管理回路、通信制御回路からなるフラッシュメモリを含むマイクロコンピュータと、このマイクロコンピュータのグラフィック制御回路に接続されたＬＣＤ、手書き入力回路に接続されたＡ／Ｄを介したディジタイザ、メモリ制御回路に接続されたシステムメモリ（マスクＲＯＭ：１６Ｍ）、セキュリティ管理回路に接続されたＩＣカード、通信制御回路に接続されたＩＲ−ＩＦ、ＲＳ−２３２Ｃ、ＰＣＭＣＩＡ制御回路を介したＰＣＭＣＩＡカードとから構成されている。このマイクロコンピュータは、通信制御回路からネットワークを介してＰＨＳ、ＧＳＭ、ＡＤＣなどに接続されるようになっている。
【０２０７】
このＰＤＡにおいては、システムメモリに格納されている制御プログラムに従ってメモリ制御回路により制御し、ディジタイザを用いて書かれた情報をＡ／Ｄによりディジタル信号に変換した後、手書き入力回路に格納する。この手書き入力回路に格納されている情報は、グラフィック制御回路を用いて信号処理した後にＬＣＤの画面上に表示させることができる。他に、外部との通信情報、セキュリティ管理情報などもグラフィック制御回路を介してＬＣＤの画面上に表示させることができる。
【０２０８】
さらに、ＰＨＳ、ＧＳＭ、ＡＤＣなどとの通信は、ネットワークを介して通信制御回路の制御により行うことができ、またＩＲ−ＩＦ、ＲＳ−２３２Ｃ、ＰＣＭＣＩＡ制御回路を介したＰＣＭＣＩＡカードなどからの情報もマイクロコンピュータに取り込むことができる。また、ＩＣカードの情報は、セキュリティ管理回路によるセキュリティ管理のために用いられる。
【０２０９】
このＰＤＡにおいては、グラフィック制御回路、手書き入力回路、メモリ制御回路、セキュリティ管理回路、通信制御回路からなるフラッシュメモリを含むマイクロコンピュータのブロック部分に本実施の形態のチップＭＦＡを使用することができる。また単に、グラフィック制御回路、手書き入力回路などの部分にチップＤを使用することなどもできる。
【０２１０】
図７７は、移動体通信機器の内部構成例を示す機能ブロック図である。この移動体通信機器は、フラッシュメモリを含むＣＰＵと、このＣＰＵに接続されたＣＨコーデック、ＬＣＤコントローラ／ドライバ、ＩＣカードと、ＣＨコーデックに接続され、モデムを介して接続されたＲＦ／ＩＦ、スピーチコーデックと、ＬＣＤコントローラ／ドライバに接続されたＬＣＤとから構成され、ＲＦ／ＩＦにはアンテナ、スピーチコーデックにはスピーカ、マイクがそれぞれ接続されている。
【０２１１】
この移動体通信機器において、ＣＰＵのフラッシュメモリに格納されているプログラムにより制御し、信号の受信時には、アンテナからの信号をＲＦ／ＩＦを介して受信して、モデムを用いて変調する。そして、変調した信号をＣＨコーデック、スピーチコーデックを用いて音声信号に変換し、スピーカから音声として出力することができる。
【０２１２】
また、信号の送信時には、受信時とは逆に、マイクからの音声信号をスピーチコーデック、ＣＨコーデックを用いて変換し、モデムを用いて復調した後に、ＲＦ／ＩＦを介してアンテナから送信することができる。
【０２１３】
この移動体通信機器においては、ＣＰＵ、ＣＨコーデックなどのブロック部分に本実施の形態のチップＭＦＡを使用し、またＬＣＤコントローラ／ドライバなどの部分に本実施の形態のチップＡＤを使用することができる。また単に、ＣＰＵの部分にチップＭＦを使用することなどもできる。
【０２１４】
以上のように、本実施の形態のチップＭＦ、チップＭＦＡ、チップＡＤ、チップＤなどの組み合わせにより構成される半導体集積回路装置は、カーナビゲーションシステム、ＣＤ−ＲＯＭ駆動装置、ゲーム機器、ＰＤＡ、移動体通信機器などのマルチメディア機器、情報家電などの機器、システムなどに広く適用することができる。
【０２１５】
以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。
【０２１６】
本発明にかかる半導体集積回路装置は、ＭＣＭ的なアプローチから、ＣＰＵを含むマイクロコンピュータにフラッシュメモリ、さらにＡＳＩＣなどのロジック回路を形成した第１のチップと、ＤＲＡＭ、さらにＡＳＩＣなどのロジック回路を形成した１つまたは複数の第２のチップとなどの複数種類の半導体チップを互いに信号の入出力が可能に同一のパッケージの内部に収納したパッケージ構造において、機能ブロック構成による回路的にも、外部接続端子数の低減、２種類のチップの１パッケージ化による実装面積の縮小を図り、コストダウンを可能とすることができる半導体集積回路装置に有用であり、さらにこの半導体集積回路装置を用いたマルチメディア機器、情報家電などの機器、システムなどに広く適用することができる。
【０２１７】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
（１）回路的なコスト面においては、ＣＰＵおよびフラッシュメモリなどによるチップＭＦとＤＲＡＭによるチップＤとの２種類のチップをワンパッケージ化したパッケージ構造とすることで、外部接続端子数の低減、２種類のチップのワンパッケージ化による実装面積の縮小を図り、半導体集積回路装置のコストダウンを図ることができる。さらに、この半導体集積回路装置を用いた機器、システムなどにおける低コスト化も可能となる。
（２）チップＭＦ、チップＤのそれぞれにＡＳＩＣなどのロジック回路を内蔵するチップＭＦＡ、チップＡＤとする場合、ＤＲＡＭをシンクロナスＤＲＡＭとする場合には、さらに外部接続端子を共通にすることができるので、より一層、外部接続端子数を低減してコストダウンを図ることができる。
（３）回路的な動作面においては、ＤＲＡＭとＡＳＩＣなどのロジック回路とが搭載されたチップＡＤとすることで、ウェイト制御を不要にして、外部からみたＤＲＡＭのセルフリフレッシュ期間にロジック回路からＤＲＡＭに対するアクセス動作を行うことができるので、外部とチップＡＤとの間のデータ転送の高速化を実現することができる。
【０２１８】
特に、ＣＰＵ自身が時間をコントロールして１クロックサイクルを実現することにより、ウェイト信号のやり取りをしないで済むので、高速アクセスを行うことができる。さらに、この半導体集積回路装置を用いた機器、システムなどにおける処理の高速化も可能となる。
（４）ＤＲＡＭとロジック回路とが搭載されたチップＡＤと、ＣＰＵとフラッシュメモリとなどが搭載されたチップＭＦ、チップＭＦＡとの２種類のチップをワンパッケージ化したパッケージ構造においても、ＣＰＵから見たＤＲＡＭのセルフリフレッシュ期間にロジック回路からＤＲＡＭに対するアクセス動作が可能になるので、チップＡＤとチップＭＦ、チップＭＦＡとの間のデータ転送の高速化を実現することができる。
（５）ウェイト信号のやり取りをするウェイト制御が不要となるので、処理のタイミング自身をＣＰＵからコントロールすることができる、すなわち処理をするタイミング自身をＣＰＵのプログラムの中で分かるので、半導体集積回路装置のプログラム作成を容易にすることができる。
（６）汎用のＤＲＡＭインタフェースを使用することにより、ＤＲＡＭとロジック回路とが搭載されたチップＡＤと、ＣＰＵとフラッシュメモリとなどが搭載されたチップＭＦ、チップＭＦＡとを高速動作可能に直結することができる。
（７）電源レベルの異なるＤＲＡＭ、ロジック、フラッシュメモリなどを２以上のチップに分けて形成することにより、プロセス上の負担が低減されるため、これらをワンチップに混載して形成する場合に比べてチップの製造コストを大幅に低減することができる。
（８）ＣＰＵおよびフラッシュメモリなどによるチップＭＦとＤＲＡＭによるチップＤとの２種類のチップを超薄型の積層パッケージに搭載してワンパッケージ化したことにより、チップの実装面積を大幅に縮小することができる。
【図面の簡単な説明】
【図１】本発明の一実施の形態である半導体集積回路装置の構成例を示す概略構成図である。
【図２】本発明の一実施の形態である半導体集積回路装置の構成例を示す概略構成図である。
【図３】本発明の一実施の形態である半導体集積回路装置の構成例を示す概略構成図である。
【図４】本発明の一実施の形態である半導体集積回路装置の構成例を示す概略構成図である。
【図５】本発明の一実施の形態である半導体集積回路装置の構成例を示す概略構成図である。
【図６】本発明の一実施の形態である半導体集積回路装置の構成例を示す概略構成図である。
【図７】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図８】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図９】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図１０】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図１１】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図１２】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図１３】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図１４】本発明の実施の形態である半導体集積回路装置を構成する半導体チップの内部構成例を示す機能ブロック図と端子機能例を示す説明図である。
【図１５】半導体チップの端子機能例の一覧を示す説明図である。
【図１６】半導体チップの端子機能例の一覧を示す説明図である。
【図１７】半導体チップの端子機能例の一覧を示す説明図である。
【図１８】半導体チップの端子機能例の一覧を示す説明図である。
【図１９】半導体チップの接続例を示す接続図である。
【図２０】半導体チップの接続例を示す接続図である。
【図２１】半導体チップの内部機能例を概略的に示す概略構成図である。
【図２２】ＤＲＡＭアクセス制御部の詳細例を示す構成図である。
【図２３】内部制御信号生成回路による動作モードの遷移状態例を示す説明図である。
【図２４】ＤＲＡＭに対するＤＲＡＭアクセス制御部の制御例を示す動作タイミング図である。
【図２５】本発明の実施の形態であるパッケージの全体斜視図である。
【図２６】本発明の実施の形態であるパッケージの断面図である。
【図２７】テープキャリアの一面に形成されたリードのパターンを示す平面図である。
【図２８】テープキャリアの一面に形成されたリードのパターンを示す平面図である。
【図２９】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３０】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３１】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３２】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３３】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３４】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３５】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３６】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３７】本発明の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３８】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図３９】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４０】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４１】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４２】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４３】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４４】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４５】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４６】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４７】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４８】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図４９】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５０】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５１】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５２】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５３】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５４】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５５】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５６】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５７】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５８】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図５９】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６０】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６１】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６２】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６３】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６４】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６５】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６６】本発明の他の実施の形態である半導体集積回路装置の製造方法を示す断面図である。
【図６７】テープキャリアの一面に形成されたリードのパターンを示す平面図である。
【図６８】テープキャリアの一面に形成されたリードのパターンを示す平面図である。
【図６９】テープキャリアの一面に形成されたリードのパターンを示す平面図である。
【図７０】本発明の他の実施の形態である半導体集積回路装置を示す断面図である。
【図７１】本発明の他の実施の形態である半導体集積回路装置を示す断面図である。
【図７２】本発明の他の実施の形態である半導体集積回路装置を示す断面図である。
【図７３】本発明の半導体集積回路装置を用いたシステム構成例を示す機能ブロック図である。
【図７４】本発明の半導体集積回路装置を用いたシステム構成例を示す機能ブロック図である。
【図７５】本発明の半導体集積回路装置を用いたシステム構成例を示す機能ブロック図である。
【図７６】本発明の半導体集積回路装置を用いたシステム構成例を示す機能ブロック図である。
【図７７】本発明の半導体集積回路装置を用いたシステム構成例を示す機能ブロック図である。
【図７８】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図７９】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８０】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８１】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８２】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８３】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８４】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８５】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８６】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８７】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８８】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図８９】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図９０】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図９１】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図９２】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図９３】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【図９４】本発明者が検討したマイクロコンピュータ、フラッシュメモリ、ＤＲＡＭ、ＡＳＩＣ混載プロセスを示す断面図である。
【符号の説明】
１Ａ、１Ｂ ＴＣＰ
２ａ、２ｂ、２ｃ、２ｄ テープキャリア
３ａ、３ｂ デバイスホール
４ バンプ電極
５ａ、５ｂ リード
６ ポッティング樹脂
７ ソルダレジスト
８ａ、８ｂ、８ｃ、８ｄ スルーホール
９ 半田バンプ
１０ 接着剤
１１ 半田
１１ｐ 半田ペースト
１２ａ、１２ｂ Ｃｕ箔ホール
１４ プリント配線基板
１５ 電極
１６ 放熱フィン
１７ モールド樹脂
１８ ピン
１９ａ、１９ｂ 異方導電性フィルム
２０ ワイヤ
１００ 半導体基板
１０１ ｐ型ウエル
１０２ フィールド酸化膜
１０３ トンネル酸化膜
１０４ フローティングゲート
１０５ 第２ゲート絶縁膜（ＯＮＯ膜）
１０６、１０７ ゲート酸化膜
１０８ ゲート電極
１０９ コントロールゲート
１１０、１１１ ゲート電極
１１２ ｎ⁺型半導体領域
１１３ ｎ^-型半導体領域
１１４ サイドウォールスペーサ
１１５ ｎ⁺型半導体領域
１１６ 酸化シリコン膜
１１７ プラグ
１１８ ｎ型半導体領域
１１９ 酸化シリコン膜
１２０ 下部電極
１２１ 容量絶縁膜
１２２ 上部電極
１２３ 酸化シリコン膜
１２４ メタル配線
１２５ 酸化シリコン膜
１２６ メタル配線
１３０ ゲート酸化膜
Ａ ロジック回路
ＡＤ チップ
ＢＬ ビット線
Ｄ チップ
Ｆ フラッシュメモリ
Ｍ マイクロコンピュータ
ＭＦ チップ
ＭＦＡ チップ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device in which a plurality of types of semiconductor chips are housed in a single package so that signals can be input and output from each other from an MCM (Multi Chip Module) approach. It is effective when applied to a semiconductor integrated circuit device in which a logic LSI such as a microcomputer including a unit), a programmable non-volatile memory such as a flash memory, a dynamic random access memory (DRAM) and an application specific integrated circuit (ASIC) is packaged. Technology.
[0002]
[Prior art]
The present inventor, in a semiconductor device related to a system-on-chip, realizes a DRAM / SIMM (Single In-line Memory Module) approach, a flash memory / DRAM microcomputer-on-chip, which has high customer needs, a microcomputer, a flash memory, Instead of making all DRAMs, ASICs, etc. into one chip, we studied a technology that enables multiple types of semiconductor chips to be input and output with each other by storing them in a single package from an MCM approach. The following is a technique studied by the present inventor, and its outline is as follows.
[0003]
In recent years, in the advanced technology fields such as multimedia and information communication, by forming a microcomputer, flash memory, DRAM, ASIC, etc. on one chip, data transfer speed is increased, space saving (improving packaging density), There is an active movement to reduce power consumption. However, if such a large variety of LSIs are formed on a single chip, the burden of the semiconductor manufacturing process becomes extremely large.
[0004]
Hereinafter, the reason will be described based on the microcomputer, flash memory, DRAM, and ASIC mixed process studied by the present inventors. The outline of this mixed loading process is as follows.
[0005]
First, as shown in FIG. 78, a p-type impurity (boron) is ion-implanted into the main surface of the semiconductor substrate 100 to form a p-type well 101, and then a field oxide film 102 is formed on the surface of the p-type well 101 by a LOCOS method. Form. The element formed on the left end of the figure is a MOSFET constituting a DRAM memory cell, and the element formed on the right side is a high breakdown voltage constituting a MOSFET constituting a memory cell of a flash memory and a part of a peripheral circuit of the flash memory. The element formed at the right end of the MOSFET is a MOSFET constituting a logic LSI such as a microcomputer or ASIC. Note that an actual LSI is mainly composed of an n-channel MOSFET and a p-channel MOSFET, but only the region for forming the n-channel MOSFET is shown here for the sake of simplicity.
[0006]
Next, as shown in FIG. 79, a tunnel oxide film 103 of the flash memory is formed. The thickness of the tunnel oxide film 103 is about 8 to 13 nm.
[0007]
Next, as shown in FIG. 80, after the polycrystalline silicon film deposited on the semiconductor substrate 100 by the CVD method is patterned to form (part of) the floating gate 104 of the flash memory, as shown in FIG. Then, a second gate insulating film (ONO film) 105 having a thickness of about 10 to 30 nm is formed by laminating a silicon oxide film, a silicon nitride film, and a silicon oxide film on the top.
[0008]
Next, as shown in FIG. 82, a gate oxide film 106 of a high voltage MOSFET is formed in the peripheral circuit region of the flash memory. The gate oxide film 106 is formed with a thickness (10 to 30 nm) thicker than the gate oxide films of other MOSFETs in order to increase the breakdown voltage.
[0009]
Next, as shown in FIG. 83, a MOSFET gate oxide film 107 constituting a logic LSI and a MOSFET gate oxide film 130 constituting a DRAM memory cell are formed. The thickness of the gate oxide film 107 is about 4 to 10 nm, and the thickness of the gate oxide film 130 is about 8 to 15 nm.
[0010]
Next, as shown in FIG. 84, the polycrystalline silicon film deposited on the semiconductor substrate 100 by the CVD method is patterned, so that the gate electrode (word line) 108 of the DRAM memory cell, the control gate 109 of the flash memory, After simultaneously forming the gate electrode 110 of the withstand voltage MOSFET and the gate electrode 111 of the MOSFET constituting the logic LSI, as shown in FIG. 85, the floating gate 104 (partially formed) of the flash memory is patterned to form the floating gate. 104 is formed.
[0011]
Next, as shown in FIG. 86, n-type impurities (phosphorus and arsenic) are ion-implanted into a part of the memory cell region of the flash memory, and n of the flash memory ⁺ After forming the type semiconductor region 112, as shown in FIG. 87, n-type impurities (phosphorus and arsenic) are ion-implanted into a part of the memory cell region of the flash memory, the peripheral circuit region, and the logic LSI formation region to N of memory ^- Type semiconductor regions 113, 113, n of high voltage MOSFET ^- Type semiconductor regions 113 and 113 and n of MOSFETs constituting the logic LSI ^- The mold semiconductor regions 113 and 113 are formed simultaneously.
[0012]
Next, as shown in FIG. 88, the gate electrode (word line) 108 of the DRAM memory cell, the control gate 109 of the flash memory, the gate electrode 110 of the high voltage MOSFET, and the sidewalls of the gate electrode 111 of the MOSFET constituting the logic LSI Sidewall spacers 114 are formed on the substrate.
[0013]
Next, as shown in FIG. 89, an n-type impurity (phosphorus or arsenic) is ion-implanted into a part of the memory cell region of the flash memory, the peripheral circuit region, and the logic LSI formation region to ⁺ Type semiconductor region 115, n of high voltage MOSFET ⁺ Type semiconductor regions 115 and 115, n of MOSFETs constituting the logic LSI ⁺ By simultaneously forming the type semiconductor regions 115, 115, one of the source region and the drain region of the flash memory and the source region of the high breakdown voltage MOSFET, and the drain region and the source region and drain region of the MOSFET constituting the logic LSI are made LDD (Lightly Doped Drain) structure.
[0014]
Next, as shown in FIG. 90, the silicon oxide film 116 deposited on the semiconductor substrate 100 by the CVD method is etched to form connection holes on both sides of the DRAM gate electrode (word line). ⁺ After forming connection holes in the upper part of the type semiconductor region 112, plugs 117 of a polycrystalline silicon film are formed in these connection holes. N-type semiconductor regions 118 are formed on both sides of the DRAM gate electrode by impurities diffused from the polycrystalline silicon film. Thereafter, the polycrystalline silicon film deposited on the silicon oxide film 116 by the CVD method is patterned to form the DRAM bit line BL and the flash memory bit line BL.
[0015]
Next, as shown in FIG. 91, after depositing a silicon oxide film 119 on the semiconductor substrate 100 by a CVD method, the polycrystalline silicon film deposited on the silicon oxide film 119 is patterned to lower the lower electrode 120 of the DRAM capacitor. Form.
[0016]
Next, as shown in FIG. 92, the tantalum oxide film (or silicon nitride film) and the polycrystalline silicon film deposited on the semiconductor substrate 100 are patterned to form the capacitor capacitor insulating film 121 and the upper electrode 122 of the DRAM capacitor. After the formation, as shown in FIG. 93, a silicon oxide film 123 is deposited on the semiconductor substrate 100 by the CVD method, and the Al film deposited on the silicon oxide film 123 is patterned to form the first layer metal wiring 124. Form. Thereafter, as shown in FIG. 94, a silicon oxide film 125 is deposited on the semiconductor substrate 100 by a CVD method, and then the Al film deposited on the silicon oxide film 125 is patterned to form a second-layer metal wiring 126. To do.
[0017]
The above is the outline of the microcomputer, flash memory, DRAM, ASIC mixed process.
[0018]
[Problems to be solved by the invention]
According to the study of the present inventor, the above-described mixed loading process has the following problems.
[0019]
(1) In order to increase the speed of the logic portion, it is necessary to shorten the gate length of the MOSFET and reduce the thickness of the gate oxide film. On the other hand, the gate oxide film of the MOSFET in the DRAM portion needs to be made somewhat thicker than the gate oxide film of the MOSFET in the logic portion in consideration of the breakdown voltage. Furthermore, the gate oxide film of the high breakdown voltage MOSFET of the flash memory to which a high breakdown voltage is applied needs to be thicker in order to ensure a sufficient breakdown voltage. That is, when a DRAM, a logic, and a flash memory are mixedly mounted, a gate oxide film having a different film thickness is required depending on a required power supply level, so that the number of steps and the number of masks are greatly increased.
[0020]
(2) If the DRAM is composed of one transistor and one capacitor, high-temperature heat treatment (heat treatment for stabilizing the tantalum oxide film or high-temperature nitridation treatment for forming a silicon nitride film) is performed when the capacitor is formed. It is necessary to set the gate length slightly longer. However, if the gate length of the logic portion is increased, the high speed of the logic portion is sacrificed.
[0021]
(3) Since the altitude of the DRAM portion on the semiconductor chip is higher than that of the logic portion and a step is generated between them, the wiring formation is adversely affected. In particular, this tendency is remarkable in the case of a DRAM adopting a stacked capacitor structure.
[0022]
In this way, when trying to achieve one chip while maintaining the performance of DRAM, logic, and flash memory together, the number of processes and the number of masks will increase significantly, or a new mixed mounting process suitable for one chip will be added. In any case, the manufacturing cost is significantly increased.
[0023]
In addition to the cost analysis of the manufacturing process as described above, the microcomputer system including the CPU has a strong demand for mounting both the flash memory and the DRAM in terms of the circuit based on the functional block configuration. Therefore, it is indispensable to make two types of semiconductor chips, a flash memory and a DRAM, into one package. Therefore, the present inventor assigns common signals of the semiconductor chips to the common external connection terminals, thereby reducing the number of external connection terminals and reducing the mounting area by making a single package of a plurality of types of semiconductor chips. I thought that it would be possible to reduce the cost of microcomputer systems.
[0024]
One object of the present invention is to reduce the number of external connection terminals in a package structure in which two types of semiconductor chips, a CPU, a flash memory, and a DRAM, are packaged in one package. It is an object of the present invention to provide a semiconductor integrated circuit device capable of reducing the mounting area by making a single package of a chip and making it possible to reduce the cost of a microcomputer system.
[0025]
Furthermore, an object of the present invention is to provide a common external connection terminal when a logic circuit such as an ASIC is incorporated in each semiconductor chip, or when a DRAM is a synchronous DRAM. It is another object of the present invention to provide a semiconductor integrated circuit device capable of reducing the cost by reducing the number of external connection terminals.
[0026]
Another object of the present invention is to provide a semiconductor integrated circuit device as described above at a low cost.
[0027]
In the microcomputer system as described above, for example, a so-called DRAM on-chip in which a semiconductor chip called a so-called flash memory-equipped microcomputer, on which a CPU and a flash memory are mounted, and a logic circuit such as a DRAM and an ASIC are mounted. When considering two types of semiconductor chips, ie, a semiconductor chip called logic, it is essential to take measures against the operation between the flash memory microcomputer and the DRAM on-chip logic. That is, measures are required for the data transfer speed in the access operation from the CPU of the microcomputer equipped with the flash memory to the DRAM of the DRAM on-chip logic and the access operation from the logic circuit in the DRAM on-chip logic to the DRAM.
[0028]
For example, when it is desired to connect the semiconductor chips of the flash memory-equipped microcomputer and the DRAM on-chip logic at a high speed, the DRAM on-chip logic can be connected at a high speed by using a DRAM direct connection interface. When the logic circuit wants to access the DRAM, a first method is to return a wait signal to the CPU when the logic circuit is operating. In this method, the microcomputer between the flash memory and the DRAM on-chip logic must be handled as an asynchronous memory, so that one clock cycle cannot be transferred, that is, the time for watching the wait signal cannot be obtained. Data transfer is clock cycle.
[0029]
Further, as a second method capable of realizing one clock cycle, there is a method in which the on-chip logic itself is bus arbitrated to a microcomputer equipped with a flash memory. In this method, the logic circuit of the DRAM on-chip logic outputs a request signal requesting the CPU to open the bus, and the CPU cannot do anything while the bus is open to the logic circuit. Arbitration overhead increases and the CPU itself cannot perform temporal control.
[0030]
Therefore, the inventor of the present invention pays attention to the fact that it is preferable that the CPU of the flash memory-equipped microcomputer itself controls the time, and effectively uses the DRAM self-refresh period as viewed from the CPU of the flash memory-equipped microcomputer. The DRAM can perform a self-refresh operation, and during the self-refresh period, an access operation to the DRAM can be performed from a logic circuit inside the DRAM on-chip logic, thereby enabling a flash memory-equipped microcomputer and a DRAM on-chip logic. The idea was that high-speed data transfer could be realized.
[0031]
One object of the present invention is to effectively use a DRAM self-refresh period viewed from the outside without using wait control in a semiconductor chip on which a DRAM and a logic circuit such as an ASIC are mounted. An object of the present invention is to provide a semiconductor integrated circuit device that enables an access operation from a logic circuit to a DRAM and realizes high-speed data transfer between the outside and a semiconductor chip.
[0032]
Even in a package structure in which two types of chips, a semiconductor chip on which a DRAM and a logic circuit are mounted and a semiconductor chip on which a CPU and a flash memory are mounted, are packaged in one package, the wait control is unnecessary and the CPU is It is an object of the present invention to provide a semiconductor integrated circuit device capable of enabling an access operation from a logic circuit to a DRAM during the self-refresh period of the DRAM and realizing a high-speed data transfer between semiconductor chips.
[0033]
It is another object of the present invention to provide a semiconductor integrated circuit device capable of facilitating program creation because the wait control for exchanging wait signals becomes unnecessary and the processing timing itself can be controlled from the CPU.
[0034]
Further, by using a general-purpose DRAM interface, a semiconductor integrated circuit capable of directly connecting a semiconductor chip on which a DRAM and a logic circuit are mounted and a semiconductor chip on which a CPU and a flash memory are mounted so as to operate at high speed. To provide an apparatus.
[0035]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0036]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0037]
That is, in the semiconductor device of the present invention, the semiconductor chip is positioned in the device hole formed in the insulating substrate,
One end of a plurality of conductors partially formed on the first surface of the insulating substrate is connected to a plurality of connection electrodes formed on the main surface of the semiconductor chip,
The other ends of the plurality of conductors are respectively connected to conductive materials embedded in a plurality of through holes arranged along the side of the insulating substrate,
The semiconductor chip is mold A plurality of packages having a structure sealed with a resin are laminated in alignment with the positions of the through holes,
The conductive materials embedded in the through holes are connected to each other to form a composite package,
A plurality of the semiconductor chips in the composite package are mold Encapsulated with resin,
The plurality of semiconductor chips in the composite package are semiconductor chips of different types.
Said mold The thickness of the resin is the same as the thickness of the insulating substrate stacked in plurality.
[0038]
In addition, a method for manufacturing a semiconductor device of the present invention includes:
(A) After forming a device hole and a through hole in each of the plurality of tape carriers, by patterning a conductive layer formed on one surface of the tape carrier, one end protrudes into the device hole, and the other end Forming a lead connected to the through hole;
(B) After bonding the leads to the connection terminals of the semiconductor chips arranged in the respective device holes of the plurality of tape carriers and electrically connecting them together, the semiconductor chips are sealed with a resin. Forming a tape carrier;
(C) After laminating the plurality of tape carriers in the vertical direction so that the through holes overlap each other, a conductor layer is formed inside the through holes to electrically connect the through holes, Forming a laminated TCP;
(D) including a step of forming an external connection terminal of the multilayer TCP at one end of the through hole, and connecting the connection terminals common to the plurality of semiconductor chips mounted on the plurality of tape carriers to the plurality of tape carriers. Are drawn out to the same external connection terminal through the through holes formed in the same place.
[0039]
In the semiconductor device manufacturing method of the present invention, the semiconductor chip includes at least a semiconductor chip on which a CPU and a flash memory are formed, and one or more semiconductor chips on which at least a DRAM is formed.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[0041]
First, a configuration example of the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIGS.
[0042]
The semiconductor integrated circuit device according to the present embodiment is, for example, an LSI package having a stacked structure in which a plurality of types of semiconductor chips are connected to each other so as to be able to input and output signals. As shown in FIG. A chip MF (first semiconductor chip) referred to as a so-called flash memory-equipped microcomputer on which a microcomputer M including a memory and peripheral circuits and a flash memory F are mounted; a logic circuit A such as a DRAMD and an ASIC; The chip AD (second semiconductor chip) called DRAM on-chip logic is mounted, and the connection terminals of each chip MF and chip AD are connected to each other through a bus inside the package. And is connected to an external connection terminal that enables connection to the outside.
[0043]
Here, the flash memory F is a programmable nonvolatile memory that is one of LSI memories, and is a memory that performs writing or erasing by applying a high voltage to a memory cell. The DRAMD is a memory that needs to repeatedly supply a control (refresh) signal for data reproduction in order to hold the data contents in one of the LSI memories. Furthermore, an ASIC is an IC for a specific application or a dedicated IC. Unlike a general-purpose LSI sold in the general market such as a large-capacity memory LSI or a microprocessor LSI, an ASIC is an LSI developed and sold for a specific device. is there.
[0044]
As other configuration examples, as shown in FIG. 2, a chip MF (first semiconductor chip) on which a microcomputer M including a CPU, a memory, peripheral circuits, and the like and a flash memory F are mounted, and only a DRAMD 1 and a configuration in which a logic circuit A such as an ASIC is removed from the second semiconductor chip with respect to the configuration example of FIG.
[0045]
Furthermore, as another configuration example, as shown in FIG. 3, a so-called flash memory-mounted on-chip logic micro, in which a microcomputer M including a CPU, a memory, peripheral circuits, and the like, a flash memory F, and a logic circuit A are mounted. A chip MFA (first semiconductor chip) referred to as a computer and a chip D (second semiconductor chip) on which only DRAMD is mounted. The first semiconductor chip is different from the configuration example of FIG. A logic circuit A such as an ASIC is mounted.
[0046]
In addition, for example, as a modification of FIG. 1, when the chip MFA and the chip AD are configured as shown in FIG. 4, one chip MF and a plurality of chips as shown in FIG. 5 are modified as the modification of FIG. 2. 3 may be configured as a modification example of FIG. 3 such as a case of a chip MFA and a plurality of chips D as shown in FIG.
[0047]
In the configuration example of the semiconductor integrated circuit device using the chip MF + chip AD, the chip MF + chip D, the chip MFA + chip D, the chip MFA + chip AD, the chip MF + chip D (expansion), and the chip MFA + chip D (expansion) as described above, The microcomputer M, the flash memory F, the DRAM D, the logic circuit A and the like mounted on each chip are composed of similar functional blocks even if the chip configuration is different.
[0048]
Further, the chip AD and the chip D are easily connected directly to the chip MF and the chip MFA according to a general-purpose DRAM interface specification, and the DRAMD is used as an expansion memory in each semiconductor integrated circuit device. Further, the logic circuit A such as the ASIC of the chip AD can control the access to the DRAMD inside the chip AD independently of the access control by the CPU of the chip MF and the chip MFA.
[0049]
Here, the outline of each semiconductor chip will be described with reference to FIGS. In particular, the chip MF, the chip AD, and the chip D will be described in order. 15 to 18 show a list of terminal function examples of the chip MF.
[0050]
7 and 8 show examples of the 144 pins of the chip MF, FIG. 7 is a functional block diagram showing an example of the internal configuration thereof, and FIG. 8 is an explanatory diagram showing an example of terminal functions. 9 and 10 show examples of the 112 pins of the chip MF, FIG. 9 is a functional block diagram showing an example of the internal configuration thereof, and FIG. 10 is an explanatory diagram showing an example of terminal functions. The difference between the 144-pin chip MF and the 112-pin chip MF is that the external terminals for data input / output differ between D0 to D31 and D0 to D15, corresponding to the data widths of 32 bits and 16 bits, respectively. In this example, the 144-pin chip MF will be mainly described.
[0051]
This 144-pin chip MF is formed with at least a microcomputer and a flash memory, and has a circuit configuration having an overall control and processing function of the semiconductor integrated circuit device and a programmable memory function that can be electrically erased collectively. For example, as shown in FIG. 7, processor CPU, flash memory Flash, random access memory / cache memory RAM / Cache, data transfer controller DTC, direct memory access controller DMAC, bus state controller BSC, user break controller UBC, interrupt Controller INTC, serial communication interface SCI, multi-function timer pulse unit MTU, compare match timer CMT, A / D converter / D, watchdog timer WDT, and a like phase look Troup circuit PLL.
[0052]
The processor CPU is a central processing unit having a RISC type instruction set, for example. Since this CPU basically operates in one cycle per instruction, the instruction execution speed is dramatically improved, and the internal 32-bit configuration is provided to enhance data processing capability. Features of this CPU are general-purpose register machines (32-bit x 16 general-purpose registers, 32-bit x 3 control registers, 32-bit x 4 system registers), RISC compatible instruction set (16-bit instruction length) Improved code efficiency due to fixed length, load store architecture (basic operations are executed between registers), adoption of delayed branch instructions to reduce pipeline disturbance during branching, C-oriented instruction set), instruction execution time 1 Instructions / cycle (35ns / instruction at 28MHz operation), address space is 4GB in architecture, built-in multiplier, 32x32 → 64 multiplication is executed for 2-4 cycles, 32x32 + 64 → 64 multiply-accumulate operation is 2 Various functions such as ˜4-cycle execution and 5-stage pipeline system are provided.
[0053]
The flash memory Flash is a circuit that incorporates a programmable memory that can be erased collectively, for example, 64 Kbytes or 128 Kbytes. The flash is connected to the CPU, DMAC, and DTC via, for example, a 32-bit data bus. The CPU, DMAC, and DTC can access the flash with a width of 8, 16, or 32 bits. This Flash data can always be accessed in one state.
[0054]
The random access memory / cache memory RAM / Cache is a memory including, for example, a 4 KB random access memory RAM and a 1 KB cache memory Cache. The features of this cache are: instruction code and PC relative read / data caching, line length is 4 bytes (1 long word is 2 instructions long), cache tag is 256 entries, direct map system, built-in ROM / RAM, built-in I The / O area is not a cache target and is also used as a built-in RAM. When the cache is enabled, various functions such as using 2 KB of the built-in RAM as an address array / data array are provided.
[0055]
The data transfer controller DTC is a circuit that is activated by an interrupt or software and can perform data transfer. Features of this DTC are data transfer independent of the CPU by peripheral I / O interrupt requests, transfer mode can be set for each interrupt factor (transfer mode is set in memory), and one activation factor・ Multiple data transfer is possible, abundant transfer modes (normal mode / repeat mode / block transfer mode) can be selected, transfer unit can be set to byte / word / longword, interrupt request that activates DTC is requested to CPU (It is possible to generate an interrupt to the CPU after completion of one data transfer, and an interrupt can be generated to the CPU after completion of all designated data transfers.) Various functions that can start transfer by software are provided. The address space can be specified by 32 bits for both the transfer source address and the transfer destination address, and the transfer target device performs data transfer to the built-in flash memory Flash, RAM / Cache, external memory, built-in peripheral circuit, etc. Is called.
[0056]
The direct memory access controller DMAC is composed of, for example, four channels, and transfers data between an external device with DACK (transfer request acceptance signal), an external memory, a memory-mapped external device, and a built-in peripheral circuit (excluding DMAC, BSC, UBC) It is a circuit that can be performed at high speed instead of. When this DMAC is used, the load on the CPU can be reduced and the operating efficiency of the chip MF can be increased. This DMAC features cycle steal transfer, dual address mode transfer, and direct transfer mode / indirect transfer mode switchable (channel 3 only). This direct transfer mode transfers data at the source address. Transfer to the destination address, and the indirect transfer mode is a function that uses data at the transfer source address as an address and transfers data at the address to the transfer destination address. In addition, a specific channel has a reload function, external request, built-in circuit, transfer request function by auto request, bus mode selection, priority order fixed mode, priority setting by round robin mode, interrupt request to CPU Various functions such as are provided.
[0057]
The bus state controller BSC is a circuit that separates address spaces, outputs control signals according to various memories, and the like. As a result, DRAM, SRAM, ROM, etc. can be directly connected to the chip MF without an external circuit. The BSC features memory access during external expansion (external data bus is 32 bits), the address space is divided into 5 areas (SRAM space x 4 areas, DRAM space x 1 area), and each area has a bus. Size (8/16/32 bits), number of wait cycles, output of chip select signal corresponding to each area, output of DRAM bar RAS and bar CAS signal when accessing DRAM space, Tp cycle for securing RAS precharge time can be generated Characteristics such as DRAM burst access function (DRAM high-speed access mode support), DRAM refresh function (programmable refresh interval, bar CAS before bar RAS refresh / self-refresh support), wait cycle by external wait signal Le insertable, various functions such as access address data multiplex I / O device is provided.
[0058]
The user break controller UBC is a circuit that provides a function that facilitates user program debugging. When a break condition is set in this UBC, a user break interrupt is generated according to the contents of the bus cycle by the CPU or DMAC and DTC. By using this function, it is possible to easily create a high-function self-monitor debugger, and it is possible to easily debug a program with a single chip MF without using a large-scale in-circuit emulator. . The features of this UBC are that when the CPU or DMAC generates a bus cycle of a set condition, an interrupt is generated, and an on-chip debugger can be easily constructed. Further, as a break condition, an address, CPU cycle or DMA / The DTC cycle, instruction fetch or data access, read or write, and operand size (longword, word, byte) can be set. When this break condition is satisfied, a user break interrupt is generated and a user break interrupt exception routine created by the user Can be executed.
[0059]
The interrupt controller INTC is a circuit that determines the priority order of interrupt factors and controls interrupt requests to the processor CPU. This INTC has a register for setting the priority order of each interrupt, so that interrupt requests can be processed according to the priority order set by the user. Features of this INTC are nine external interrupt terminals, 43 internal interrupt factors, 16 levels of priority can be set, noise canceller function indicating the state of the NMI terminal, and the occurrence of an interrupt to the outside When the chip MF is releasing the bus right, the external bus master can be notified that the internal peripheral circuit interrupt has occurred and the bus right can be requested.
[0060]
The serial communication interface SCI includes, for example, two independent channels, and these two channels have the same function. This SCI is a circuit capable of serial communication by two methods of asynchronous communication and clock synchronous communication. In addition, a serial communication function (multiprocessor communication function) between a plurality of processors is provided. Features of this SCI include selection of asynchronous / clock synchronous mode per channel, simultaneous transmission and reception (full duplex), built-in dedicated baud rate generator, communication function between multiprocessors, etc. Various functions are provided.
[0061]
The multifunction timer pulse unit MTU is a circuit composed of, for example, six channels of 16-bit timers. Features of this MTU are 16 types of waveform output or 16 types of pulse input / output processing based on 5 channels of 16-bit timer, 16 output compare registers and input capture registers, a total of 16 Independent comparator, 8 types of counter input clocks can be selected, input capture function, pulse output mode (one-shot / toggle / PWM / complementary PWM / reset synchronous PWM), multiple counter synchronization function, complementary PWM output mode (6 Output non-overlap waveform for inverter control of phase, automatic dead time setting, PWM duty can be set arbitrarily from 0 to 100%, output OFF function), reset synchronous PWM mode (regular phase normal phase / reverse phase PWM waveform 3 phase output), phase counting mode (2 phase encoder) Various functions of the dust counting available), etc. are provided.
[0062]
The compare match timer CMT is composed of, for example, two channels, is composed of a 16-bit free running counter, a single compare register, and the like, and has a function of generating an interrupt request upon a compare match.
[0063]
The A / D converter A / D is 10 bits × 8 channels, enables conversion by an external trigger, and incorporates two units of a sample and hold function so that two channels can be sampled simultaneously.
[0064]
The watchdog timer WDT is a 1-channel timer and is a circuit capable of monitoring the system. This WDT outputs an overflow signal to the outside if the counter value overflows due to a system runaway or the like without being correctly rewritten by the CPU. At the same time, an internal reset signal of the chip MF can be generated. When not used as WDT, it can also be used as an interval timer. When used as an interval timer, an interval timer interrupt is generated every time the counter overflows. The WDT is also used when the standby mode is canceled. The internal reset signal can be generated by register setting, and the type of reset can be selected from power-on reset or manual reset. The features of this WDT include switching of watchdog timer / interval timer, and a function of generating an internal reset, an external signal or an interrupt when the count overflows.
[0065]
The phase look loop circuit PLL has a built-in clock oscillator, for example, and operates as a PLL circuit for clock multiplication.
[0066]
In the chip MF configured as described above, these internal circuits are connected to each other by an internal address bus BUSAI and upper and lower internal data buses BUSDI as shown in FIG. The external connection terminal I / O is connected by a peripheral address bus BUSAO, a peripheral data bus BUSDO, and a control signal line SL.
[0067]
The internal address bus BUSAI has a 24-bit bus width, and each of the processor CPU, flash memory Flash, random access memory / cache memory RAM / Cache, data transfer controller DTC, direct memory access controller DMAC, and bus state controller BSC. Connected between.
[0068]
The internal data bus BUSDI includes an upper 16-bit bus and a lower 16-bit bus. The processor CPU, the flash memory Flash, the random access memory / cache memory RAM / Cache, the data transfer controller DTC, and the direct memory access controller, respectively. The DMAC and the bus state controller BSC are connected to each other, and can support a data width of 32 bits by an upper 16-bit bus and a lower 16-bit bus.
[0069]
The peripheral address bus BUSAO has a 24-bit bus width, and includes internal circuits of a bus state controller BSC, an interrupt controller INTC, a serial communication interface SCI, a multi-function timer pulse unit MTU, a compare match timer CMT, and a watchdog timer WDT. It is connected between the external connection terminal I / O.
[0070]
The peripheral data bus BUSDO has a 16-bit bus width, and includes internal circuits of a bus state controller BSC, an interrupt controller INTC, a serial communication interface SCI, a multi-function timer pulse unit MTU, a compare match timer CMT, and a watchdog timer WDT. It is connected between the external connection terminal I / O.
[0071]
The control signal line SL includes a data transfer controller DTC, a direct memory access controller DMAC, a bus state controller BSC, a user break controller UBC, an interrupt controller INTC, a serial communication interface SCI, a multi-function timer pulse unit MTU, a compare match timer CMT, A / The D converters A / D are connected to each other between the internal circuits and between these internal circuits and the external connection terminal I / O.
[0072]
In this chip MF, as the external connection terminal I / O, functions are assigned as shown in FIG. 8, and there are 98 input / output terminals and 8 input terminals. The functions of each external connection terminal I / O are as shown in the list of terminal function examples corresponding to the classification, symbol, input / output, and name, as shown in FIGS. The 112-pin chip MF has a function assignment as shown in FIG. 10, and has 74 input / output terminals and 8 input terminals.
[0073]
FIG. 11 is a functional block diagram showing an example of the internal configuration of the chip AD, and FIG. 12 is an explanatory diagram showing an example of its terminal function. The chip AD shows an example of 144 pins.
[0074]
The chip AD has a circuit configuration in which a DRAM and an ASIC are formed and has a memory function that can be written / read at any time and a processing function by a logic circuit. For example, as shown in FIG. DRAM bank Bank, main amplifier MA, data transfer circuit DT, digital signal processing circuit DSP, row address buffer RAB, column address buffer CAB, and control logic / timing generation circuit CR / TG. As this DRAM, a simple dynamic random access memory DRAM capable of writing / reading at any time which requires a memory holding operation, a synchronous synchronous DRAM (SDRAM) using a clock, and an extended data out DRAM capable of extending the data output time (EDO-DRAM).
[0075]
The power supply circuit VS is a circuit that supplies necessary power to a plurality of DRAM banks Bank and the main amplifier MA by inputting the voltages of the power supply Vcc and the ground Vss from the outside.
[0076]
Each of the plurality of DRAM banks Bank can operate independently, and each bank includes, for example, a memory cell, a word decoder, a column decoder, a sense amplifier, and a timing generator. For example, the capacity of these DRAM banks Bank is 256 kbits per bank.
[0077]
The main amplifier MA is a circuit that performs data input / output between the plurality of DRAM banks Bank and the external connection terminals D0 to D31. For example, there are 128 global data lines between each DRAM bank Bank, and data is exchanged therethrough.
[0078]
The data transfer circuit DT switches the data transfer pattern between the DRAM including the DRAM bank Bank and the main amplifier MA and the digital signal processing circuit DSP in real time. For example, it is possible to select one of adjacent data or clear the data.
[0079]
The digital signal processing circuit DSP is a circuit that executes processing of digital signals such as images and sounds. For example, in the case of image processing, it executes processing for removing the hidden surface by Z comparison, processing for giving transparency by α blending, etc. To do. Further, the data is output from the serial output ports SD0 to SD23 to an output device such as a display. The digital signal processing circuit DSP and the data transfer circuit DT are controlled by control signals C0 to C27.
[0080]
The row address buffer RAB and the column address buffer CAB are circuits that take in address signals from the external address signal input terminals A0 to A10, generate internal address signals, and supply them to each DRAM bank Bank. The column address is fetched at the timing of bar CASL, bar CASH, bar CASHL, bar CASHH at the timing row address of bar RAS.
[0081]
The control logic / timing generation circuit CR / TG is a circuit that generates various timing signals necessary for the operation of the DRAM. The input bar CS is a chip select signal, the bar RAS is a row address strobe signal, the bar CASL, the bar CASH, the bar CASHL, the bar CASHH is a column address strobe signal, the RD / bar WR is a read / write signal (if it is high level, it is read, Low level indicates writing). The four column address strobe signals are for enabling byte control (read / write control for each byte). The bar CASL is the least significant byte D0 to D7, and the bar CASH is the second least significant byte D8. ˜D15, the bar CASHL is for the third least significant byte D16 to D23, and the bar CASHH is for the most significant byte D24 to D31.
[0082]
In the internal circuit of the chip AD configured as described above, the plurality of DRAM banks Bank and the row address buffer RAB and the column address buffer CAB are connected to each other by the internal address bus BUSAI, and further, the row address buffer RAB, the column address The buffer CAB and the external connection terminal I / O are connected by a peripheral address bus BUSAO, and the main amplifier MA and the external connection terminal I / O are connected by a peripheral data bus BUSDO.
[0083]
The data transfer circuit DT and the digital signal processing circuit DSP are connected to each other by an address bus and a data internal bus BUSI, and between the data transfer circuit DT, the digital signal processing circuit DSP, and the external connection terminal I / O. Are connected by a peripheral bus BUSO for data and control signals.
[0084]
In this chip AD, as shown in FIG. 12, as the external connection terminals, as shown in FIG. 12, voltage terminals Vcc and Vss of the ground Vss, address terminals A0 to A10, data input / output terminals D0 to D31, chip select terminal bar CS, Row address strobe terminal bar RAS, column address strobe terminal bar CASL, bar CASH, bar CASHL, bar CASHH, read / write terminal RD / bar WR, clock terminal CK, serial data output terminals SD0-SD23, ASIC control signal terminal C0- C27 is provided.
[0085]
FIG. 13 is a functional block diagram showing an example of the internal configuration of the chip D, and FIG. Chip D shows an example of 50 pins.
[0086]
The chip D has a circuit configuration in which only a DRAM is formed and has a memory function that can be written / read at any time. For example, as shown in FIG. 13, a power supply circuit VS, a plurality of DRAM banks Bank, a main amplifier MA, A row address buffer RAB, a column address buffer CAB, and a control logic / timing generation circuit CR / TG are included.
[0087]
The chip D has a circuit configuration only of DRAM from which the logic circuit of the data transfer circuit DT and the digital signal processing circuit DSP of the chip AD shown in FIG. Is the same as the internal circuit of the chip AD, and a functional description thereof is omitted here.
[0088]
In this chip D, as shown in FIG. 14, as external connection terminals, voltage terminals Vcc and Vss of power supply Vcc, ground Vss, address terminals A0 to A11, data input / output terminals DQ0 to DQ31, row address strobe terminal bar RAS. Column address strobe terminal bar LCAS, bar UCAS, write enable terminal bar WE, and output enable terminal bar OE are provided.
[0089]
In the semiconductor integrated circuit device according to the present embodiment configured by combining the chip MF and chip MFA with one or more chips AD and chip D as described above, in particular, as one feature of the present invention, Signal terminals common to the connection terminal of the chip MF or chip MFA and the connection terminal of the chip AD or chip D are commonly assigned to the same external connection terminal. Hereinafter, the connection terminals commonly assigned to the same external connection terminal will be described in detail.
[0090]
FIG. 19 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 7 and 8 and the two 50-pin chips D shown in FIGS. In FIG. 19, only the connection between the signal terminal common to the connection terminal of the chip MF and the connection terminal of the chip D and the external connection terminal is shown, and in fact, the signal terminal independent of only the chip MF. The connection terminal is also connected to the external connection terminal.
[0091]
In the connection between the 144-pin chip MF and the 50-pin two chips D, the address terminals A0 to A11 of the chip MF are connected to the address terminals A0 to A11 of the two chips D and the same external connection terminals A0 to A11. The data input / output terminals D0 to D31 of the chip MF are divided and connected to the data input / output terminals DQ0 to DQ15 of the respective chips D and are connected to the same external connection terminals D0 to D31.
[0092]
The power terminal Vcc and the ground terminal Vss of the chip MF are connected to the power terminal Vcc and the ground terminal Vss of the chip D, respectively, and are connected to the same external connection terminals Vcc and Vss. In addition, since this voltage terminal is actually allocated to a plurality of terminals of the chip MF, the chip D, and the external connection terminal, the same terminals are connected to each other.
[0093]
Further, for the control signal, the row address strobe terminal bar RAS of the chip MF is connected in common to the two chips D and is connected to the external connection terminal bar RAS, and the column address strobe terminal bars CASL and CASH of the chip MF are Connected to the column address strobe terminal bar LCAS, bar UCAS of one chip D and connected to the external connection terminal bar CASL, bar CASH, the column address strobe terminal bar CASHL, bar CASHH of the chip MF is the column of the other chip D The address strobe terminal bar LCAS is connected to the bar UCAS and is connected to the external connection terminal bar CASHL and the bar CASHH.
[0094]
The read / write terminal RD / bar WR of the chip MF is connected in common to the write enable terminal bar WE of the two chips D and is connected to the external connection terminal RD / bar WR, and the chip select terminal bar CS3 of the chip MF. Are connected in common to the output enable terminal bar OE of the two chips D and to the external connection terminal bar CS3.
[0095]
As described above, in the connection between the chip MF, the chip D, and the external connection terminal, all the connection terminals of the chip D are connected to the same external connection terminal in common with the connection terminal of the chip MF. Note that in the semiconductor integrated circuit device including the chip MF and the chip D, there are actually connection terminals that are independent signal terminals only in the chip MF, and therefore external connection terminals connected to the independent connection terminals are also included. It is provided so that it can be connected to the outside.
[0096]
FIG. 20 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 7 and 8 and the 144-pin chip AD shown in FIGS. Note that FIG. 20 also shows only the connection between the signal terminal and the external connection terminal common to the connection terminal of the chip MF and the connection terminal of the chip AD as in FIG. The connection terminals, which are independent signal terminals only for the chip AD, are also connected to the external connection terminals.
[0097]
In the connection between the 144-pin chip MF and the 144-pin chip AD, the address terminals A0 to A10 of the chip MF are connected to the address terminals A0 to A10 of the chip AD and to the same external connection terminals A0 to A10. The data input / output terminals D0 to D31 of the chip MF are connected to the data input / output terminals D0 to D31 of the chip AD and to the same external connection terminals D0 to D31.
[0098]
The power terminal Vcc and the ground terminal Vss of the chip MF are connected to the power terminal Vcc and the ground terminal Vss of the chip AD, respectively, and are also connected to the same external connection terminals Vcc and Vss. In addition, since this voltage terminal is actually allocated to a plurality of terminals of the chip MF, the chip AD, and the external connection terminal, the same terminals are connected to each other.
[0099]
Further, regarding the control signals, the row address strobe terminal bar RAS, column address strobe terminal bar CASL, bar CASH, bar CASHL, bar CASHH, read / write terminal RD / bar WR, chip select terminal bar CS3, clock terminal of chip MF CK is connected to the row address strobe terminal bar RAS, column address strobe terminal bar CASL, bar CASH, bar CASHL, bar CASHH, read / write terminal RD / bar WR, chip select terminal bar CS3, and clock terminal CK of the chip AD, respectively. At the same time, the row address strobe terminal bar RAS, column address strobe terminal bar CASL, bar CASH, bar CASHL, bar CASHH, read / write of the same external connection terminal respectively. Write terminal RD / bar WR, chip select terminal bar CS3, which is connected to the clock terminal CK.
[0100]
As described above, in the semiconductor integrated circuit device including the chip MF and the chip AD, the serial data outputs SD0 to SD23 and the ASIC control signal terminals C0 to C27, which are signals specific to only the chip AD, are actually independent. Since connection terminals that are independent signal terminals also exist only in the chip MF, external connection terminals connected to these independent connection terminals are also provided so as to be connectable to the outside.
[0101]
In the semiconductor integrated circuit device, when the DRAM of chip AD and chip D is a synchronous DRAM, it is necessary to further synchronize inside the semiconductor integrated circuit device. The clock terminal to which the clock signal is assigned is also connected to the same external connection terminal as a common connection terminal.
[0102]
Next, with respect to the operation of the present embodiment, in a semiconductor integrated circuit device constituted by a combination of the chip MF and chip MFA and one or more chips AD and chip D, the processor CPU of the chip MF (chip MFA) An outline of the read operation, write operation, and refresh operation for the DRAM of the chip AD (chip D) will be described.
(1) Read operation
For example, in the address multiplex, since the address signal is input in a time division manner, two synchronization signals, ie, a row address strobe signal bar RAS and a column address strobe signal bar CAS from the processor CPU are required. The period when the bar RAS is at a high level (H) is a period during which the RAS circuit is precharged, and during this period, no memory operation is performed inside the chip. On the other hand, the period in which the bar CAS is H is a period in which the CAS-related circuits such as the data output buffer and the data input buffer are precharged, and during this period, the reading operation and the writing operation with the outside of the chip AD are not performed.
[0103]
When the bar RAS is at a low level (L), the RAS circuit is activated and the memory operation starts. Subsequently, when the bar CAS becomes L, a read operation or a write operation starts, and data is exchanged with the chip MF outside the chip AD. Thus, in the DRAM of the chip AD, the precharge period and the active period are alternately repeated. Usually, the cycle time of the bar RAS is the cycle time of the chip AD.
[0104]
The read operation is designated by setting the write enable signal bar WE to H before the falling time of the bar CAS and holding it until the bar CAS rises. Once the data is output, it is held until the bar CAS rises. Here, there are three types of access time, and the time from when the bar RAS and bar CAS fall to the time when data is output to the data output terminal is called the bar RAS access time and the bar CAS access time, respectively. The time from when the data is determined until the data is output is called the address access time.
(2) Write operation
Since the relationship between the address signal and the bars RAS and CAS is the same as that in the read operation, description thereof is omitted here. In addition, the timing standard of the bar RAS and bar CAS such as the cycle time is the same as the read operation. However, the writing operation is designated by setting the bar WE to L before the falling time of the bar CAS. During this cycle, the data output terminal is held in a high impedance state. There is also a specification of Read Modify Write operation in which the data read once to the chip MF outside the chip AD is changed by the chip MF and written to the same memory cell again while the bar RAS remains L.
(3) Refresh operation
There are a refresh operation that is interrupted during a random access operation such as reading and writing, and a refresh operation that is performed only to hold the stored information in the chip AD during the battery backup period. In the former, bar RAS only refresh and CBR (bar CAS before bar RAS) refresh are standard, and in the latter, self refresh is standard.
[0105]
For example, in the bar RAS only refresh, all memory cells in one row (word line) are simultaneously refreshed during one cycle of the bar RAS of the same timing standard as the read operation and the write operation. However, the refresh address must be given from the chip MF outside the chip AD by setting the bar CAS to H.
[0106]
This refreshing method includes concentrated refresh and distributed refresh. Centralized refresh is a method in which refresh is repeated in the minimum cycle, and during this period, memory access from the chip MF outside the chip AD is not possible, but during the remaining period, refresh is not interrupted and memory access is accepted from the outside. In the distributed refresh, one cycle of the refresh operation is equally distributed during the maximum refresh period. Actually, since distributed refresh is frequently used, one cycle of the refresh operation is a timing at which the cycle of the normal read / write operation is interrupted.
[0107]
Further, the CBR refresh is internally determined as a refresh operation by setting the bar CAS to L before the bar RAS. By this determination pulse, an address is generated from the internal refresh address counter, and a word line is selected and refreshed. Therefore, it is not necessary to give an address from the outside of the chip AD.
[0108]
Further, in the self-refresh, the pulse width of the bar RAS is set to, for example, 100 μs or more at the CBR timing after the end of the normal memory cycle. Internally, when this time is exceeded, a refresh operation using a refresh address counter and a refresh timer starts, and self-refreshing continues as long as both the bars RAS and CAS are L. The smaller the refresh frequency, the lower the power consumption of the chip AD. This frequency is automatically adjusted by a timer that detects the internal temperature of the chip AD. It should be noted that a bar RAS precharge period is required when shifting from self refresh to a normal cycle.
[0109]
As described above, the reading operation, the writing operation, and the refreshing operation are performed from the processor CPU of the chip MF to the DRAM of the chip AD, and particularly in the self-refreshing operation of the refresh, as one feature of the present invention, This logic circuit can perform a refresh operation / access operation. Hereinafter, it will be described in detail that the refresh operation / access operation can be performed during the self-refresh operation.
[0110]
FIG. 21 is a schematic configuration diagram schematically showing an internal function example of the chip AD shown in FIG. The chip AD is composed of a dynamic random access memory DRAM, a memory built-in logic Logic, and a DRAM access control circuit DAC. Note that the DRAM, memory built-in logic logic, and DRAM access control circuit DAC in FIG. 21 are respectively the DRAM portion including the plurality of DRAM banks Bank and the main amplifier MA, the data transfer circuit DT, and the digital signal processing circuit shown in FIG. This corresponds to the ASIC portion by the DSP and the access control portion by the row address buffer RAB and the column address buffer CAB. The input buffer IB and the output buffer OB are connected to the circuit I / O that performs data input / output between the main amplifier MA and the external connection terminals D0 to D32 shown in FIG. 11 and the digital signal processing circuit DSP. / O is supported.
[0111]
In this chip AD, a chip select signal bar CS, a row address strobe signal bar RAS, and a column address strobe signal bar CAS are input to a DRAM access control circuit DAC via a control signal terminal, an address signal, and a data signal. Can be input / output via the data input / output terminal. Further, in the chip AD, the DRAM and the DRAM access control circuit DAC are connected by an address bus BUSA, and the DRAM, the memory logic built-in logic, and the data input / output terminal are connected by a data bus BUSD. Yes. For example, the internal data bus BUSD has a 64-bit bus width that is wider than the 8-bit data input / output terminal.
[0112]
Further, in the chip AD, the memory built-in logic Logic and the DRAM access control circuit DAC are connected by an address bus and a control signal line, and the DRAM access control circuit DAC performs a self-refresh operation on the memory built-in logic Logic. A permission signal is output, and a read / write signal R / W and an address signal are output from the logic logic built in the memory to the DRAM access control circuit DAC. The read / write signal R / W can also be output separately for the read signal R and the write signal W. During the self-refresh period, a data input / output inhibition signal DIS is output from the DRAM access control circuit DAC to the input buffer IB and the output buffer OB. During the self-refresh period by the data input / output inhibition signal DIS, the input buffer IB prohibits data input from the outside of the chip AD, and the output buffer circuit OB outputs the data on the data bus BSD to the outside of the chip AD. Is prohibited.
[0113]
FIG. 22 is a block diagram showing a detailed example of the DRAM access control circuit DAC. The DRAM access control circuit DAC includes an internal control signal generation circuit CSG, a plurality of selector circuits SC, and the like. The chip select signal bar CS, the row address strobe signal bar RAS, the column address that are input to the internal control signal generation circuit CSG. Based on the strobe signal bar CAS, a control signal for selecting an address and the like are generated, and a self-refresh operation permission signal is generated and output to the logic logic in the memory.
[0114]
The logic logic with built-in memory that has received this permission signal can access the DRAM, outputs a read / write signal R / W to the DRAM access control circuit DAC, makes a read / write request, and outputs an address signal. An arbitrary memory cell can be selected by outputting to the DRAM access control circuit DAC, and data can be read / written between the selected memory cell and the logic logic incorporated in the memory. Note that this read / write request can be made by outputting the read signal R when a read request is made, and by outputting the write signal W when making a write request.
[0115]
The control signal of the address generated by the internal control signal generation circuit CSG is for the access operation from the processor CPU of the chip MF outside the chip AD and the access operation from the memory logic Logic inside the chip AD. These are used as address control signals for selecting one of the memory cells of the DRAM by selecting one via the selector circuit SC.
[0116]
FIG. 23 is an explanatory diagram showing an example of the transition state of the operation mode by the internal control signal generation circuit CSG. This operation mode can be divided into a normal DRAM access operation mode, a DRAM self-refresh operation mode, and an internal memory logic logic access operation mode. From the normal DRAM access operation mode to the self-refresh operation mode. Transition without request for read / write by the read / write signal R / W from the logic logic in the memory, and the return to the normal DRAM access operation mode is performed by releasing the refresh.
[0117]
The self-refresh operation mode is changed to the internal access operation mode when there is a read / write request from the logic logic incorporated in the memory, and the return to the self-refresh operation mode is performed upon completion of the read / write. Similarly, a transition from the normal DRAM access operation mode to the internal access operation mode is made when there is a read / write request from the logic logic built in the memory, and the return to the normal DRAM access operation mode is performed by releasing the refresh. .
[0118]
FIG. 24 is an operation timing chart showing a control example of the DRAM access control circuit DAC including the internal control signal generation circuit CSG for the DRAM. In the operation control for the DRAM, as shown in FIG. 24A, the DRAM self-execution between the normal DRAM access period in which the normal DRAM access can be performed and the normal DRAM access period and the normal DRAM access period. There is a DRAM self-refresh period in which refresh can be performed. This DRAM self-refresh period is a period in which a normal access operation from the chip MF to the DRAM is not performed.
[0119]
In the DRAM self-refresh period, a self-refresh operation permission signal is output to the memory logic Logic based on the row address strobe signal bar RAS and the column address strobe signal bar CAS in synchronization with the clock signal CK. The refresh operation is canceled only when there is a request for an access operation for reading / writing by the control signal R / W for the DRAM from the logic logic in the memory, and from the logic logic (digital signal processing circuit DSP) for the memory in the DRAM. The access operation is enabled.
[0120]
In the execution of the refresh operation / access operation in this self-refresh period, for example, as shown in FIG. 24 (b), the read operation can be repeated in accordance with the read request by the control signal R. The refresh operation can be executed during the period, the read operation can be repeated according to the write request by the control signal W, the refresh operation can be executed during the period between the write, and the read by the control signal R The read and write access operations can be repeated according to the request and the write request by the control signal W, and the refresh operation can be executed during the period between the access operations.
[0121]
As described above, when the processor CPU of the chip MF performs a self-refresh operation on the DRAM of the chip AD, the logic logic built in the memory of the chip AD can access the DRAM, and the DRAM is requested by a write request from the logic logic built in the memory. In addition, data can be written to the DRAM, and data can be read from the DRAM in response to a read request.
[0122]
Note that the access operation to the DRAM by the memory logic of the chip AD during this self-refresh operation is the same when another chip is connected to the chip AD. For example, the chip MFA, or simply including the CPU, etc. The same effect can be expected for this semiconductor chip. That is, the present invention can be applied to a semiconductor integrated circuit device having a package structure in which an access operation to the DRAM of the chip AD from the outside and a self-refresh operation of the DRAM can be performed.
[0123]
Next, a specific structure of the package according to the present embodiment will be described in detail. FIG. 25 is an overall perspective view of the package of the present embodiment, and FIG. 26 is a cross-sectional view of the package.
[0124]
The package of the present embodiment seals the first chip MF (microcomputer with built-in flash memory) in which a microcomputer and flash memory are formed in a first TCP (Tape Carrier Package) 1A, A stacked TCP structure in which the second chip AD (DRAM-on-chip logic) in which the ASIC is formed is sealed in a second TCP 1B, and the two TCPs 1A and 1B are overlapped in the vertical direction and joined together. have.
[0125]
The first chip MF sealed with the first TCP 1A is disposed in the device hole 3a opened in the center of the tape carrier 2a with its main surface (element formation surface) facing down, It is electrically connected to one end (inner lead portion) of a lead 5a formed on one surface of the tape carrier 2a via a bump electrode 4 formed on the peripheral portion of the main surface. The main surface of the chip MF is covered with a potting resin 6 that protects an LSI (microcomputer with a flash memory) formed on the main surface from the external environment.
[0126]
The leads 5a formed on one surface of the tape carrier 2a have a pattern as shown in FIG. The surfaces of these leads 5a are covered with a solder resist 7 except for one end portion (inner lead portion) protruding into the device hole 3a. The other end of each lead 5a is electrically connected to a through hole 8a penetrating from one surface of the tape carrier 2a to the other surface. These through holes 8a are arranged in two rows along the four sides of the tape carrier 2a. On the surface of each through hole 8a, as shown in FIG. Solder bumps 9 serving as external connection terminals for mounting are joined.
[0127]
The second TCP 1B is stacked on top of the first TCP 1A. TCP1A and TCP1B are closely joined by an adhesive 10 applied to the mating surfaces of both. The second chip AD sealed in the TCP 1B is arranged with its main surface facing down in the device hole 3b opened in the central portion of the tape carrier 2b. Via the formed bump electrode 4, it is electrically connected to one end (inner lead portion) of a lead 5b formed on one surface of the tape carrier 2b. The main surface of the chip AD is coated with a potting resin 6 that protects an LSI (DRAM on chip logic) formed on the main surface from the external environment.
[0128]
The outer diameter of the TCP 1B tape carrier 2b is the same as that of the TCP 1A tape carrier 2a. The size of the device hole 3b of the tape carrier 2b is smaller than the device hole 3a of the tape carrier 2a because the outer diameter of the chip AD is smaller than that of the chip MF.
[0129]
The leads 5b formed on one surface of the tape carrier 2b have a pattern as shown in FIG. The other end of each lead 5b is electrically connected to a through hole 8b penetrating from one surface of the tape carrier 2b to the other surface. These through holes 8b are arranged in two rows along the four sides of the tape carrier 2b, like the through holes 8a of the tape carrier 2a. The through holes 8a of the tape carrier 2a and the through holes 8b of the tape carrier 2b are formed with the same number and the same pitch, and the through holes 8a and 8b that face each other when the tape carriers 2a and 2b are overlapped are accurately They are arranged so as to overlap. The through holes 8 a and 8 b are filled with solder 11, and the through holes 8 a and 8 b facing each other are electrically connected via the solder 11.
[0130]
In the stacked TCP of the present embodiment, the through-holes 8a and 8b in which the connection terminals (pins) common to the two chips MF and AD (that is, having the same function) are arranged at the same positions on the tape carriers 2a and 2b. Through the solder bumps 9 joined to one end of the through hole 8a, and is commonly drawn out to the outside (printed wiring board).
[0131]
In FIG. 27, the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 200) of the through holes 8a formed on the tape carrier 2a are given. In FIG. 28, the numbers (1 to 144) of the connection terminals formed on the chip AD and the numbers (1 to 200) of the through holes 8b formed on the tape carrier 2b are given. The same number is attached | subjected to the through holes 8a and 8b arrange | positioned in the same position of the tape carriers 2a and 2b.
[0132]
Table 1 shows an example of the allocation of the connection terminals of the chips MF and AD and the through holes 8a and 8b. In the table, the numbers (1 to 144) in the MFpin # column correspond to the connection terminal numbers (1 to 144) of the chip MF shown in FIG. 27, and the numbers (1 to 144) in the ADpin # column are This corresponds to the connection terminal numbers (1 to 144) of the chip AD shown in FIG. The numbers in the Via # column are assigned to the connection terminals common to either or both of the chips MF and AD among the numbers (1 to 200) of the through holes 8a and 8b shown in FIGS. Number.
[0133]
[Table 1]

[0134]
As shown in FIGS. 27 and 28, the connection terminals common to the chips MF and AD are arranged at substantially the same positions of the chips MF and AD. As a result, the leads 5a and 5b of the tape carriers 2a and 2b can be easily routed and the lead length can be shortened, so that the data transfer of the chips MF and AD can be speeded up. Further, since the number of necessary through holes 8a and 8b can be minimized, the outer diameter of the tape carriers 2a and 2b can be reduced to reduce the package size.
[0135]
Although not particularly limited, each member constituting the stacked TCP of the present embodiment is configured with the following materials and dimensions.
[0136]
The tape carriers 2a and 2b are made of a polyimide resin film having a thickness of 75 μm. The leads 5a and 5b are made of Cu (copper) foil having a thickness of 18 μm, and Au (gold) or Sn (tin) is plated on the surface of one end portion (inner lead portion) thereof. The adhesive 10 is made of polyimide resin, and its film thickness is 12 μm. The solder resist 7 is made of an epoxy resin and has a film thickness of 20 μm. The solder bumps 9 which are external connection terminals and the solder 11 in the through holes 8a and 8b are made of a lead (Pb) -tin (Sn) alloy. The chip MF and the chip AD are made of single crystal silicon having a thickness of 50 μm, and the potting resin 6 that protects the main surfaces thereof is made of an epoxy resin. The bump electrodes 4 formed on the main surfaces of the chip MF and the chip AD are made of Au, and the height thereof is 20 μm. That is, this multilayer TCP is configured such that the total thickness of the chip MF and the bump electrode 4 is thinner than the thickness of the tape carrier 2a, and the total thickness of the chip AD and the bump electrode 4 is thinner than the thickness of the tape carrier 2b. As a result, the thickness of the portion excluding the solder bumps 9 in the stacking direction is 218 μm.
[0137]
Next, a manufacturing method of the stacked TCP according to the present embodiment will be described with reference to FIGS. 29A to 33A are cross-sectional views of the TCP 1B, and FIG. 29B are cross-sectional views of the TCP 1A.
[0138]
First, as shown in FIG. 29, tape carriers 2a and 2b made of a polyimide resin film are prepared, and punched out to form device holes 3a and through holes 8a in the tape carrier 2a, and device holes 3b in the tape carrier 2b. And through-holes 8b are formed. These tape carriers 2a and 2b are long films wound on reels, but only a part of them (one each for TCP1A and 1B) is shown in the figure.
[0139]
Next, as shown in FIG. 30, after laminating a Cu foil on one surface of each of the tape carriers 2a and 2b, the Cu foil is wet etched to form leads 5a on the tape carrier 2a, and leads to the tape carrier 2b. 5b is formed. At the same time, a Cu foil hole 12a is formed at one end of the through hole 8a, and a Cu foil hole 12b is formed at one end of the through hole 8b. In order to secure the contact area between the solder (11) filled in the through holes 8a and 8b in the later process and the leads 5a and 5b and prevent disconnection of the through holes, the diameter of the Cu foil hole 12a is larger than that of the through holes 8a. And the diameter of the Cu foil hole 12b is made smaller than that of the through hole 8b. Further, since the Cu foil has a smaller thermal expansion coefficient and higher dimensional stability than the polyimide resin tape carriers 2a and 2b, the diameters of the Cu foil holes 12a and 12b are made smaller than those of the through holes 8a and 8b. And positioning at the time of superimposing the tape carrier 2a and the tape carrier 2b using the through holes 8a and 8b in a subsequent process can be performed with high accuracy.
[0140]
Next, as shown in FIG. 31, the surface of one end portion (inner lead portion) of the lead 5a protruding into the device hole 3a of the tape carrier 2a and one end of the lead 5b protruding into the device hole 3b of the tape carrier 2b. After plating the surface of the inner part (inner lead part) with Au or Sn by electrolytic plating, the solder resist 7 is applied to the lower surface of the tape carrier 2a, and the adhesive 10 is applied to the lower surface of the tape carrier 2b. To do.
[0141]
Next, as shown in FIG. 32, the bump electrodes 4 formed on the connection terminals of the chip MF and the leads 5a of the tape carrier 2a are collectively connected by a gang bonding method. Further, the bump electrodes 4 formed on the connection terminals of the chip AD and the leads 5b of the tape carrier 2b are collectively connected by a gang bonding method. The chip MF and the chip AD are polished in advance in a wafer state, and then the thickness is reduced to 50 μm by spin etching. The bump electrode 4 is formed in the final step of the wafer process using a stud bump bonding method. Since the inner lead portions of the leads 5a and 5b are plated with Au or Sn, the lead 5a and the bump electrode 4 and the lead 5b and the bump electrode 4 are joined by Au—Au bonding or Au—Sn eutectic bonding. Is done. The bonding between the leads 5a and 5b and the bump electrode 4 may be performed by a single point bonding method instead of the gang bonding method.
[0142]
Next, as shown in FIG. 33, the potting resin 6 is attached to the main surface of the chip MF and the gap between the tape carrier 2a and the device hole 3a using a resin potting dispenser. Similarly, the potting resin 6 is applied to the main surface of the chip AD and the gap between the tape carrier 2b and the device hole 3b.
[0143]
Next, after separating the long tape carriers 2a and 2b into pieces using a cutting die, each tape carrier 2a and 2b is mounted on a socket and subjected to an aging inspection to select non-defective products. The aging of the tape carriers 2a and 2b is performed by applying a socket pin to a test pad formed on each part of the tape carriers 2a and 2b. Through the steps so far, the TCP 1A in which the chip MF is sealed and the TCP 1B in which the chip AD is sealed are almost completed.
[0144]
Next, as shown in FIG. 34, the tape carriers 2a and 2b are overlapped and thermocompression bonded so that the positions of the opposed through holes 8a and 8b are exactly coincident, and both are bonded by the adhesive 10, TCP1A and 1B are made into one package. As described above, since the chip MF is thinner than the tape carrier 2a and the chip AD is thinner than the tape carrier 2b, the TCP 1A and the TCP 1B can be tightly bonded. For positioning the through hole 8a and the through hole 8b, the Cu foil holes 12a and 12b described above are used. Or you may utilize the pad for a test formed in each part of tape carrier 2a, 2b.
[0145]
Next, as shown in FIG. 35, a solder paste made of a lead (Pb) -tin (Sn) alloy is embedded in the through holes 8a and 8b by a screen printing method, and then the solder paste is reflowed to solder 11 Form.
[0146]
Thereafter, a solder bump 9 is formed at one end of the through hole 8a of the tape carrier 2a, thereby completing the multilayer TCP shown in FIGS. The solder bump 9 is formed by positioning a solder ball previously formed on the through hole 8a with the solder bump forming surface of the tape carrier 2a facing upward, and then reflowing the solder ball. Alternatively, solder bumps arranged on the surface of the glass substrate may be transferred to the surface of the through hole 8a. The solder bump 9 is made of a lead (Pb) -tin (Sn) alloy having a melting point lower than that of the solder 11 filled in the through holes 8a and 8b.
[0147]
In order to mount the manufactured laminated TCP on the printed wiring board, the solder bumps 9 are positioned on the electrodes 15 of the printed wiring board 14 as shown in FIG. You only need to reflow.
[0148]
In the stacked TCP of this embodiment, heat generated from the chips MF and AD escapes to the substrate mainly through the solder bumps 9. Therefore, when the TCPs 1A and 1B are stacked, a chip with a larger amount of heat generation is placed on the lower side (substrate On the side close to In the above example, the chip MF on which the flash memory-equipped microcomputer is formed has more function blocks and generates more heat than the chip AD on which the DRAM on-chip logic is formed. MF is arranged. In addition, by disposing a chip having a large number of connection terminals on the lower side (substrate side), it is easy to route wiring for connecting the connection terminals of the chip and the external connection terminals.
[0149]
Further, in such a multilayer module that generates a large amount of heat and is system-on-chip, it is preferable that the memory cell of the DRAM formed on the chip AD adopts a multilayer capacitor (STC) structure. This is because the multilayer capacitor structure has less thermal leakage current and higher thermal reliability than the planar capacitor structure. Furthermore, since the multilayer capacitor structure can extend the refresh cycle, it is possible to suppress the amount of heat generation.
[0150]
When the amount of heat generated by the chip is very large, as shown in FIG. 37, a radiation fin 16 made of a metal having a high thermal conductivity such as Al may be attached to the top of the laminated TCP. In this case, the chip MF that generates a large amount of heat is disposed on the top of the chip AD (on the side close to the radiation fins 16).
[0151]
Next, another embodiment of the package of the present invention will be described.
[0152]
In the manufacturing method described above, after TCP1A and TCP1B are overlapped, solder 11 is embedded in the facing through holes 8a and 8b (see FIGS. 34 and 35). It may be packaged.
[0153]
First, as shown in FIG. 38, TCP1A and TCP1B are individually formed according to the method described above. Next, as shown in FIG. 39, the solder paste 11p is embedded inside the through hole 8a of the TCP 1A, and the solder paste 11p is embedded inside the through hole 8b of the TCP 1B. A screen printing method is used for embedding the solder paste 11p.
[0154]
Next, as shown in FIG. 40, the tape carriers 2a and 2b are overlapped and thermocompression bonded, and both are bonded with the adhesive 10, and the solder paste 11p is reflowed to solder the solder 11 into the through holes 8a and 8b. Form. Subsequent steps are the same as in the manufacturing method described above.
[0155]
In this manufacturing method, since TCP1A and TCP1B are temporarily attached with the adhesive force of the solder paste 11p, through-holes 8a facing each other until the superimposed TCP1A and 1B are transported to a heating furnace or the like and are thermocompression bonded together. , 8b can be prevented from being displaced.
[0156]
As another method for forming the through holes 8a and 8b, the tape carriers 2a and 2b are overlapped to form the TCP 1A and 1B as one package, and then a hole is formed in the tape carriers 2a and 2b using a drill, and then the inside of the hole is formed. Alternatively, the conductive layer may be formed by electroless plating.
[0157]
Further, the sealing of the chips MF and AD can be performed by a transfer mold method instead of the potting method. In this case, first, as shown in FIG. 41, the bump electrode 4 of the chip MF and the lead 5a of the tape carrier 2a are electrically connected according to the method described above, and the bump electrode 4 of the chip AD and the lead 5b of the tape carrier 2b are connected. Connect electrically.
[0158]
Next, as shown in FIG. 42, the chips MF and AD are sealed with the mold resin 17. In order to seal the chips MF and AD, the tape carriers 2a and 2b are respectively attached to the mold, and the plurality of chips MF and AD are respectively sealed in a batch. As the mold resin 17, an epoxy resin is used.
[0159]
In the illustrated example, the entire surfaces of the chips MF and AD are covered with the mold resin 17, but the back surface of the chips MF and AD may be exposed from the mold resin 17. In that case, the resin can be poured into the main surfaces and side surfaces of the chips MF and AD by applying heat-pressing the resin processed into a sheet shape to the upper surfaces of the tape carriers 2a and 2b instead of the normal transfer mold method. . However, in this method, it is necessary to control the amount of resin poured with high accuracy so that the resin does not protrude from the upper surfaces of the tape carriers 2a and 2b.
[0160]
In the package of the present invention, since the thickness of the mold resin 17 for sealing the chips MF and AD is extremely thin, the back surface of the chips MF and AD is exposed from the mold resin 17 or the entire surfaces of the chips MF and AD are molded. If the thickness of the mold resin 17 is uneven between the main surface and the back surface of the chip MF, AD in the structure coated with the resin 17, there is a difference in the thermal expansion coefficient between the chip MF, AD and the mold resin 17. Warping occurs in the TCPs 1A and 1B, leading to chip cracks and poor connection during board mounting. Accordingly, the mold resin 17 has a low thermal expansion coefficient, and it is necessary to select a material close to the thermal expansion coefficient of the chips MF and AD.
[0161]
Next, the tape carriers 2a and 2b are separated into pieces using a cutting die, and each TCP 1A and 1B is subjected to an aging inspection to select non-defective products, and as shown in FIG. The tape carriers 2a and 2b are overlapped and heat-pressed so that the positions of 8b and 8b are exactly matched, and the two are joined by the adhesive 10. Thereafter, solder 11 is formed in the through holes 8a and 8b according to the above-described method, and solder bumps 9 are formed on one end of the through hole 8a of the tape carrier 2a, thereby completing the multilayer TCP. Alternatively, as shown in FIG. 44, the inside of the through hole 8a of the TCP 1A and the inside of the through hole 8b of the TCP 1B may be filled with the solder 11, and then the TCP 1A and 1B may be stacked to form one package.
[0162]
The chip MF and the chip AD may be sealed together with the mold resin 17 at the same time. In this case, first, as shown in FIG. 45, the bump electrode 4 of the chip MF and the lead 5a of the tape carrier 2a are electrically connected according to the method described above, and the bump electrode 4 of the chip AD and the lead 5b of the tape carrier 2b are connected. After the electrical connection, the tape carriers 2 a and 2 b are overlapped and thermocompression bonded, and both are bonded with the adhesive 10. Next, as shown in FIG. 46, after the chips MF and AD are simultaneously sealed with the mold resin 17, as shown in FIG. 47, the solder 11 is formed inside the through holes 8a and 8b according to the method described above, Further, solder bumps 9 are formed at one end of the through hole 8a of the tape carrier 2a.
[0163]
According to the above method of sealing the chips MF and AD with the mold resin 17, the outer diameter accuracy of the sealing portion is improved as compared with the method of sealing the chips MF and AD with the potting resin 6. A highly stable and uniform layered TCP can be manufactured. Moreover, the sealing time can be shortened by sealing a plurality of chips MF and AD in a batch. Furthermore, by making the thickness of the mold resin 17 the same as that of the tape carriers 2a and 2b, there is no gap between the TCP 1A and the TCP 1B, so that it is possible to prevent problems such as moisture accumulation between the TCP 1A and the TCP 1B. A highly reliable stacked TCP can be manufactured.
[0164]
In the multilayer TCP of the present invention, the external connection terminals can be constituted by the leads 5a and 5b instead of the method of constituting the external connection terminals by the solder bumps 9. A method for manufacturing this stacked TCP will be described with reference to FIGS.
[0165]
First, as shown in FIG. 48, tape carriers 2a and 2b made of a polyimide resin film are punched to form device holes 3a in the tape carrier 2a, and device holes 3b are formed in the tape carrier 2b. The tape carriers 2a and 2b are not formed with the through holes 8a and 8b as described above.
[0166]
Next, as shown in FIG. 49, the lead 5a is formed on the tape carrier 2a according to the method described above, and the lead 5b is formed on the tape carrier 2b, and Au or Sn is formed on the surface of one end portion (inner lead portion) thereof. After the plating, the solder resist 7 is applied to one surface of the tape carrier 2a, and the adhesive 10 is applied to one surface of the tape carrier 2b. The leads 5a and 5b are formed in such a length that their other end portions (outer lead portions) can be used as external connection terminals.
[0167]
Next, as shown in FIG. 50, the bump electrode 4 of the chip MF and the lead 5a of the tape carrier 2a are electrically connected according to the above-described method, and the bump electrode 4 of the chip AD and the lead 5b of the tape carrier 2b are electrically connected. Then, the chips MF and AD are sealed with the potting resin 6. Subsequently, the tape carriers 2a and 2b are separated into individual pieces, and the individual TCPs 1A and 1B are subjected to an aging inspection to select non-defective products.
[0168]
Next, as shown in FIG. 51, the tape carriers 2a and 2b are overlapped and bonded according to the above-described method to form one package of the TCPs 1A and 1B. Then, as shown in FIG. 52, the leads 5a and 5b The tape carriers 2a and 2b supporting the other end portion (outer lead portion) are cut and removed.
[0169]
Next, after solder plating is applied to the surfaces of the other end portions (outer lead portions) of the leads 5a and 5b, the other end portions (outer lead portions) of the leads 5a and 5b are formed by lead molding as shown in FIG. Molded into a gull wing using a mold. The leads 5a and 5b are simultaneously formed using the same mold.
[0170]
In order to mount the manufactured laminated TCP on the printed wiring board, the other ends (outer lead portions) of the leads 5a and 5b are placed on the electrodes 15 of the printed wiring board 14 as shown in FIG. After being overlaid, the solder plating is reflowed. At that time, the leads 5 a and 5 b connected to the connection terminals common to the two chips MF and AD are connected to the same electrode 15 of the printed wiring board 14. That is, this multilayer TCP has a structure in which the connection terminals common to the two chips MF and AD are electrically connected through the leads 5a and 5b and drawn out to the outside (printed wiring board) through the leads 5a and 5b. It has become.
[0171]
In the illustrated stacked TCP, the main surfaces of the chips MF and AD are arranged facing upward, but may be disposed facing downward. Further, although the chips MF and AD are sealed with the potting resin 6, the chips MF and AD may be sealed with the mold resin 17 as shown in FIG.
[0172]
According to the above-described multilayer TCP in which the external connection terminals are configured by the leads 5a and 5b, the manufacturing process can be simplified as compared with the above-described multilayer TCP in which the external connection terminals are configured by the solder bumps 9. The manufacturing cost of the laminated TCP can be reduced. Further, since it is not necessary to provide the through holes 5a and 5b in the tape carriers 2a and 2b, the leads 5a and 5b can be easily routed, and the manufacturing cost of the tape carriers 2a and 2b can be reduced.
[0173]
Furthermore, by simultaneously forming the lead 5a of the tape carrier 2a and the lead 5b of the tape carrier 2b with the same mold, the time required for forming the external connection terminals can be shortened. Further, the area of the electrode 15 occupying the surface of the printed wiring board 14 can be reduced by overlapping and connecting the other ends (outer lead parts) of the leads 5 a and 5 b on the electrode 15 of the printed wiring board 14. In addition, the stacked TCP can be mounted (connection between the leads 5a and 5b and the electrode 15) at a time.
[0174]
The leads 5a and 5b constituting the external connection terminal may be individually formed using two molds. Also in this case, as shown in FIG. 56 (structure in which chips MF and AD are sealed with potting resin 6) and FIG. 57 (structure in which chips MF and AD are sealed with mold resin 17), two chips MF and AD The leads 5 a and 5 b connected to the common connection terminal are connected to the same electrode 15 of the printed wiring board 14.
[0175]
The stacked TCP shown in FIG. 58 forms an external connection terminal by forming the other end portion (outer lead portion) of the lead 5a formed on the lower TCP 1A into a gull wing shape, and the electrical connection between the TCP 1A and the TCP 1B is as follows. This is done through the solder 11 embedded in the through holes 8a and 8b formed in the tape carriers 2a and 2b.
[0176]
In the above structure in which the external connection terminal is configured by a lead formed into a gull wing, the stress applied to the connection portion due to the difference in thermal expansion coefficient between the multilayer TCP and the printed wiring board is absorbed by deformation of the flexible lead.・ Because it is relaxed, the connection reliability with the substrate is high compared to the structure in which the external connection terminals are configured by solder bumps.
[0177]
As shown in FIG. 59, the package of the present invention can be individually mounted on the printed wiring board 14 without making TCP1A and TCP1B into one package. In this case, the mounting density is reduced as compared with the stacked TCP in which the TCPs 1A and 1B are packaged in one package, but the process of stacking the TCPs 1A and 1B into a single package becomes unnecessary, thereby reducing the manufacturing cost of the package. be able to.
[0178]
As shown in FIG. 60, the laminated TCP of the present invention uses pins 18 used in a PGA (Pin Grid Array) type package as shown in FIG. An external connection terminal can also be configured. The surface of the pin 18 is plated with Sn (tin) or the like, and is electrically connected to the lead 5a and / or the lead 5b inside the through holes 8a and 8b.
[0179]
Further, the laminated TCP of the present invention can also connect the chip MF and the lead 5a and the chip AD and the lead 5b using an anisotropic conductive film.
[0180]
In order to manufacture a laminated TCP using an anisotropic conductive film, first, as shown in FIG. 61, device holes 3a, through holes 8a and leads 5a are formed in a tape carrier 2a according to the method described above, and the tape carrier After the device hole 3b, the through hole 8a and the lead 5b are formed in 2b, the solder resist 7 is applied to one surface of the tape carrier 2a, and the adhesive 10 is applied to one surface of the tape carrier 2b.
[0181]
Next, as shown in FIG. 62, an anisotropic conductive film 19a, which has been cut into approximately the same dimensions as the device hole 3a of the tape carrier 2a in advance, is connected to one end of the lead 5a (inner Position on the lead). Similarly, an anisotropic conductive film that has been cut in advance to approximately the same dimensions as the device hole 3b of the tape carrier 2b is placed on one end (inner lead portion) of the lead 5b that protrudes 19b into the device hole 3b. Position.
[0182]
Next, as shown in FIG. 63, after positioning on the anisotropic conductive film 19a with the main surface of the chip MF on which the bump electrode 4 is formed facing downward, the anisotropic conductive film 19a is heated and pressurized. Thus, the bump electrode 4 and the lead 5a are electrically connected through the conductive particles in the anisotropic conductive film 19a. Similarly, the anisotropic conductive film 19b is heated and pressed after positioning on the anisotropic conductive film 19b with the main surface of the chip AD on which the bump electrodes 4 are formed facing downward, and the anisotropic conductive film 19b. The bump electrode 4 and the lead 5b are electrically connected through the conductive particles in 19b. Subsequently, the tape carriers 2a and 2b are separated into individual pieces, and the individual TCPs 1A and 1B are subjected to an aging inspection to select non-defective products.
[0183]
Next, as shown in FIG. 64, after the tape carriers 2a and 2b are overlapped according to the above-described method to form the TCPs 1A and 1B into one package, as shown in FIG. 65, the solder 11 is placed inside the through holes 8a and 8b. And solder bumps 9 are formed at one end of the through hole 8a.
[0184]
The above-described various laminated TCPs of the present invention can be applied not only to the combination of the chip MF and the chip AD but also to the configuration examples of the chip MFA + chip D, the chip MFA + chip AD, the chip MF + chip D, and the like. is there. The stacked TCP of the present invention can also be applied when three or more chips are stacked.
[0185]
In the stacked TCP shown in FIG. 66, a chip MF in which a microcomputer and a flash memory are formed is sealed in TCP 1A, and two chips D in which only a DRAM is formed. ₁ , D ₂ Is sealed in two TCP1C and TCP1D, and the three TCP1A, 1C, and 1D are stacked in the vertical direction and integrally joined together.
[0186]
The chip MF encapsulated in the lowermost TCP 1A is arranged in the device hole 3a of the tape carrier 2a with its main surface (element formation surface) facing upward, and is formed in the periphery of the main surface The bump electrode 4 is electrically connected to one end (inner lead portion) of a lead 5a formed on one surface of the tape carrier 2a. The chip MF is sealed with a mold resin 17. The leads 5a formed on one surface of the tape carrier 2a have a pattern as shown in FIG.
[0187]
On top of TCP1A, chip D ₁ Is stacked, and further on top of it is chip D ₂ Are stacked. Chip D sealed in TCP1C ₁ Is arranged in the device hole 3c opened in the central portion of the tape carrier 2c with its main surface facing upward, and via the bump electrode 4 formed in the central portion of the main surface, the tape carrier 2c is electrically connected to one end (inner lead portion) of the lead 5c formed on one surface. Similarly, chip D sealed in TCP1D ₂ Is arranged in the device hole 3d opened in the central portion of the tape carrier 2d with its main surface facing upward, and via the bump electrode 4 formed in the central portion of the main surface, the tape carrier It is electrically connected to one end (inner lead portion) of a lead 5d formed on one surface of 2d. These chips D ₁ , D ₂ Is also sealed with a mold resin 17. The lead 5c formed on one surface of the tape carrier 2c has a pattern as shown in FIG. 68, and the lead 5d formed on one surface of the tape carrier 2d has a pattern as shown in FIG. Yes.
[0188]
This stacked TCP is composed of the above three chips MF, D ₁ , D ₂ Are formed in the tape carrier 2a by electrically connecting through the through holes 8a, 8c and 8d arranged at the same position of the tape carriers 2a, 2c and 2d. In addition, the lead 5a is structured to be drawn out to the outside (printed wiring board) through the other end portion (outer lead portion) of the lead 5a. It goes without saying that the external connection terminal can be constituted by the above-described solder bump, pin, or the like in addition to the lead.
[0189]
In FIG. 67, the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 144) of the through holes 8a formed on the tape carrier 2a are attached. FIG. 68 shows chip D. ₁ The numbers (1-46) of the connection terminals formed on the tape carrier 2 and the numbers (1-144) of the through holes 8c formed on the tape carrier 2c are attached. FIG. ₂ The numbers (1-46) of the connection terminals formed on the head and the numbers (1-144) of the through holes 8d formed in the tape carrier 2d are attached. The same numbers are attached to the through holes 8a, 8c, 8d arranged at the same positions of the tape carriers 2a, 2c, 2d.
[0190]
Chip D ₁ , D ₂ If the area of each is less than half of the area of the chip MF, as shown in FIG. ₁ , D ₂ Are placed side by side, chip D ₁ , D ₂ The common connection terminals can be connected by the common lead 5e. In this way, an ultra-thin package can be realized as in the case of the stacked TCP on which the two chips MF and AD are mounted.
[0191]
The package of the present invention is not limited to the structure described above, and various design changes can be added to the details thereof. For example, as shown in FIG. 71, a structure in which the chip MF sealed in the TCP 1A and the lead 5a formed on the tape carrier 2a are electrically connected by an Au wire 20 may be employed.
[0192]
In addition to the stacked TCP structure, for example, as shown in FIG. 72, the chip MF and the chip AD are not packaged as one package, but individually sealed in a QFP (Quad Flat package) type package. Can also be implemented.
[0193]
The package of the present invention includes devices and systems such as multimedia devices and information home appliances, such as a car navigation system as shown in FIG. 73, a CD-ROM (Compact Disk ROM) drive device as shown in FIG. Such a game device, a PDA (Personal Digital Assistance) as shown in FIG. 76, a mobile communication device as shown in FIG. 77, and the like will be described below.
[0194]
FIG. 73 is a functional block diagram showing an example of the internal configuration of the car navigation system. This car navigation system includes a control unit, a display unit connected to the control unit, a GPS, and a CD-ROM. The control unit includes a main CPU, program EPROM (4M), work RAM (SRAM: 1M), I / O control circuit, ARTOP, image RAM (DRAM: 4M), and CG (Computer Graphics) ROM (mask ROM: 4M). ), A gate array, etc., and the display unit is composed of a slave microcomputer, TFT, and the like.
[0195]
In this car navigation system, the main CPU of the control unit controls according to a control program stored in a program EPROM. First, the control unit receives GPS position information for measuring the position of the vehicle between the satellite and the ground station, and map information stored in the CD-ROM via an I / O control circuit and a gate array, respectively. The information is input and stored in the work RAM.
[0196]
Then, according to the processing program stored in the CG ROM, the processing of arranging the vehicle position on the map based on the position information and map information stored in the work RAM is performed by ARTOP, and this image information is Store in the image RAM. Thereafter, the image information stored in the image RAM is passed to the display unit, and the display unit displays the image information on the screen based on the TFT under the control of the slave microcomputer, so that the position of the car is displayed on the map. The image arranged in the can be displayed.
[0197]
In this car navigation system, the main CPU is constituted by a processor, the program EPROM is constituted by a flash memory, the ARTOP is constituted by a logic circuit by ASIC, the chip MFA of this embodiment is used for this block portion, and the image RAM Is configured with a DRAM and a gate array with an ASIC logic circuit, the chip AD of this embodiment can be used for this block portion. It is also possible to simply use the chip MF for the main CPU, the program EPROM portion, and the chip D for the image RAM portion.
[0198]
FIG. 74 is a functional block diagram showing an internal configuration example of the CD-ROM drive device. This CD-ROM drive device includes a microcomputer including a flash memory, a pre-servo circuit, a signal processing circuit, a ROM decoder, a host I / F, and a pre-servo circuit and a signal processing circuit that are bi-directionally connected to the microcomputer. A pickup and SRAM connected bidirectionally, a D / A connected to a ROM decoder, a buffer RAM connected to a host I / F, and the like are included.
[0199]
A motor M for driving the CD-ROM is connected to the signal processing circuit, and signals from the CD-ROM are read by a pickup. The rotation of the motor is controlled by signals from a pre-servo circuit and a signal processing circuit. Furthermore, a speaker is connected to the D / A. The CD-ROM driving device is connected to a host computer via a host I / F.
[0200]
In this CD-ROM driving device, the signal of the CD-ROM is read by a pickup based on the control of the microcomputer, the read information is processed by a signal processing circuit, and the processed information is stored in the SRAM. Furthermore, the information stored in the SRAM can be decoded by a ROM decoder, converted into an analog signal via a D / A, and then output from a speaker. The data can be output to the host computer via F.
[0201]
In this CD-ROM drive device, the chip MFA of the present embodiment is used in the block portion of a microcomputer including a flash memory, a signal processing circuit, and the like, and the block RAM and the host I / F are implemented in the present embodiment. A chip AD of the form can be used. It is also possible to simply use the chip MF for the microcomputer part including the flash memory and the chip D for the buffer RAM part.
[0202]
FIG. 75 is a functional block diagram showing an example of the internal configuration of the game device. This game machine includes a main body control unit, a display RAM (SDRAM: 4M), a buffer RAM (DRAM: 4M) and a keyboard connected to a speaker, a CD-ROM, a ROM cassette, a CRT connected to the main body control unit. It is configured. The main body control unit includes a main CPU, a system ROM (mask ROM: 16M), a DRAM (SDRAM: 4M), a RAM (SRAM: 256k), a sound processor, a graphic processor, an image compression processor, an I / O control circuit, and the like. ing.
[0203]
In this game machine, the main CPU of the main body control unit controls according to a control program stored in the system ROM. The image / audio information stored in the CD-ROM and ROM cassette and the instruction information from the keyboard are input via the I / O control circuit, and the information is stored in the DRAM and RAM.
[0204]
Then, the information stored in the DRAM and RAM is processed into audio and video signals using a sound processor and a graphic processor, respectively, and the audio signal is output as sound from the speaker, and the video signal is temporarily stored in the display RAM. After being stored, it can be displayed as an image on the CRT screen. At this time, the video signal is used after the amount of information is compressed by the image compression processor and stored in the buffer RAM.
[0205]
In this game machine, the chip MFA of the present embodiment is used for block portions such as a main CPU, system ROM, sound processor, and graphic processor, and the chip of the present embodiment is used for block portions such as a DRAM and an image compression processor. AD can be used. It is also possible to simply use the chip D for the parts such as the chip MF, DRAM, RAM, and buffer RAM for the main CPU and system ROM.
[0206]
FIG. 76 is a functional block diagram showing an example of the internal configuration of a PDA. The PDA includes a microcomputer including a flash memory including a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit, an LCD connected to the graphic control circuit of the microcomputer, and a handwriting input circuit. Digitizer via connected A / D, system memory (mask ROM: 16M) connected to memory control circuit, IC card connected to security management circuit, IR-IF, RS- connected to communication control circuit 232C, and a PCMCIA card via a PCMCIA control circuit. This microcomputer is connected to a PHS, GSM, ADC, etc. via a network from a communication control circuit.
[0207]
In this PDA, control is performed by a memory control circuit in accordance with a control program stored in a system memory, information written using a digitizer is converted into a digital signal by A / D, and then stored in a handwriting input circuit. The information stored in the handwriting input circuit can be displayed on the LCD screen after signal processing using the graphic control circuit. In addition, external communication information, security management information, and the like can be displayed on the LCD screen via the graphic control circuit.
[0208]
Furthermore, communication with PHS, GSM, ADC, etc. can be performed by control of a communication control circuit via a network, and information from a PCMCIA card via an IR-IF, RS-232C, PCMCIA control circuit, etc. Can be imported into a microcomputer. The information on the IC card is used for security management by the security management circuit.
[0209]
In this PDA, the chip MFA of this embodiment can be used in a block portion of a microcomputer including a flash memory including a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit. It is also possible to simply use the chip D for parts such as a graphic control circuit and a handwriting input circuit.
[0210]
FIG. 77 is a functional block diagram showing an example of the internal configuration of a mobile communication device. This mobile communication device includes a CPU including a flash memory, a CH codec connected to the CPU, an LCD controller / driver, an IC card, an RF / IF connected to the CH codec via a modem, and speech. It consists of a codec and an LCD connected to an LCD controller / driver. An antenna is connected to the RF / IF, and a speaker and a microphone are connected to the speech codec.
[0211]
In this mobile communication device, control is performed by a program stored in the flash memory of the CPU, and when a signal is received, the signal from the antenna is received via the RF / IF and modulated using a modem. Then, the modulated signal can be converted into an audio signal using a CH codec and a speech codec and output from the speaker as audio.
[0212]
When transmitting a signal, the voice signal from the microphone is converted using a speech codec or CH codec and demodulated using a modem, and then transmitted from an antenna via an RF / IF. Can do.
[0213]
In this mobile communication device, the chip MFA of the present embodiment can be used for block portions such as a CPU and a CH codec, and the chip AD of the present embodiment can be used for portions such as an LCD controller / driver. . It is also possible to simply use the chip MF for the CPU portion.
[0214]
As described above, the semiconductor integrated circuit device configured by combining the chip MF, the chip MFA, the chip AD, the chip D, and the like according to the present embodiment includes a car navigation system, a CD-ROM drive device, a game device, a PDA, and a mobile device. It can be widely applied to multimedia devices such as body communication devices, devices such as information home appliances, and systems.
[0215]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0216]
In the semiconductor integrated circuit device according to the present invention, from an MCM approach, a first chip in which a logic circuit such as a flash memory and an ASIC is formed in a microcomputer including a CPU, and a logic circuit such as a DRAM and an ASIC are formed. In a package structure in which a plurality of types of semiconductor chips, such as one or a plurality of second chips, are housed in the same package so that signals can be input and output with each other, the external connection is also achieved in terms of the circuit by the functional block configuration This is useful for a semiconductor integrated circuit device capable of reducing the number of terminals, reducing the mounting area by integrating two types of chips into one package, and enabling cost reduction. Further, multimedia using this semiconductor integrated circuit device It can be widely applied to devices and systems such as devices and information appliances.
[0217]
【The invention's effect】
Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1) In terms of circuit cost, a package structure in which two types of chips, a chip MF made of a CPU and a flash memory, and a chip D made of a DRAM are made into one package, thereby reducing the number of external connection terminals; The mounting area can be reduced by making one type of chip into one package, and the cost of the semiconductor integrated circuit device can be reduced. Furthermore, it is possible to reduce the cost of equipment, systems, etc. using this semiconductor integrated circuit device.
(2) When the chip MF and the chip D are the chip MFA and the chip AD each incorporating a logic circuit such as an ASIC, when the DRAM is a synchronous DRAM, the external connection terminals can be further shared. Therefore, it is possible to further reduce the cost by reducing the number of external connection terminals.
(3) In terms of circuit operation, the chip AD on which a DRAM and a logic circuit such as an ASIC are mounted eliminates the need for wait control, and from the logic circuit to the DRAM during the DRAM self-refresh period viewed from the outside. Therefore, it is possible to realize high-speed data transfer between the outside and the chip AD.
[0218]
In particular, since the CPU itself controls the time to realize one clock cycle, it is not necessary to exchange wait signals, so that high speed access can be performed. Furthermore, it is possible to increase the processing speed in equipment, systems, etc. using this semiconductor integrated circuit device.
(4) Even in a package structure in which two types of chips, a chip AD on which a DRAM and a logic circuit are mounted, a chip MF on which a CPU and a flash memory are mounted, and a chip MFA are integrated into one package, the CPU sees it. Since the logic circuit can access the DRAM during the self-refresh period of the DRAM, high-speed data transfer between the chip AD, the chip MF, and the chip MFA can be realized.
(5) Since wait control for exchanging wait signals is not required, the processing timing itself can be controlled from the CPU, that is, the processing timing itself can be known in the CPU program. Can be easily created.
(6) By using a general-purpose DRAM interface, a chip AD on which a DRAM and a logic circuit are mounted and a chip MF and a chip MFA on which a CPU and a flash memory are mounted are directly connected so as to be capable of high-speed operation. Can do.
(7) Since the DRAM, logic, flash memory, etc. having different power levels are formed in two or more chips, the burden on the process is reduced. Compared to the case where these are formed in one chip. Thus, the manufacturing cost of the chip can be greatly reduced.
(8) The mounting area of the chip is greatly reduced by mounting two types of chips, a chip MF using a CPU and a flash memory, and a chip D using a DRAM in an ultra-thin stacked package. Can do.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 2 is a schematic configuration diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 3 is a schematic configuration diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 4 is a schematic configuration diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 5 is a schematic configuration diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 6 is a schematic configuration diagram showing a configuration example of a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 7 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention, and an explanatory diagram showing an example of a terminal function.
FIG. 8 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention, and an explanatory diagram showing an example of terminal functions.
FIG. 9 is a functional block diagram showing an internal configuration example of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention and an explanatory diagram showing an example of terminal functions.
FIG. 10 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention, and an explanatory diagram showing an example of terminal functions.
FIG. 11 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention, and an explanatory diagram showing an example of a terminal function.
FIG. 12 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention, and an explanatory diagram showing an example of a terminal function.
FIG. 13 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention and an explanatory diagram showing an example of terminal functions.
FIG. 14 is a functional block diagram showing an example of the internal configuration of a semiconductor chip constituting the semiconductor integrated circuit device according to the embodiment of the present invention, and an explanatory diagram showing an example of a terminal function.
FIG. 15 is an explanatory diagram showing a list of terminal functions of the semiconductor chip.
FIG. 16 is an explanatory diagram showing a list of terminal functions of the semiconductor chip.
FIG. 17 is an explanatory diagram showing a list of terminal function examples of a semiconductor chip;
FIG. 18 is an explanatory diagram showing a list of terminal functions of the semiconductor chip.
FIG. 19 is a connection diagram illustrating a connection example of a semiconductor chip.
FIG. 20 is a connection diagram illustrating a connection example of a semiconductor chip.
FIG. 21 is a schematic configuration diagram schematically showing an example of an internal function of a semiconductor chip.
FIG. 22 is a block diagram showing a detailed example of a DRAM access control unit.
FIG. 23 is an explanatory diagram illustrating an example of a transition state of an operation mode by an internal control signal generation circuit.
FIG. 24 is an operation timing chart showing a control example of a DRAM access control unit for a DRAM.
FIG. 25 is an overall perspective view of a package according to an embodiment of the present invention.
FIG. 26 is a cross-sectional view of a package according to an embodiment of the present invention.
FIG. 27 is a plan view showing a lead pattern formed on one surface of the tape carrier.
FIG. 28 is a plan view showing a lead pattern formed on one surface of the tape carrier.
FIG. 29 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
30 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 31 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
32 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
33 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
34 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention; FIG.
FIG. 35 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.
FIG. 36 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 37 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention;
FIG. 38 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 39 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
40 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
41 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 42 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
43 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
44 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
45 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 46 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
47 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
48 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
49 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 50 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
51 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
52 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 53 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
54 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 55 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
56 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 57 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 58 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 59 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.
60 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention; FIG.
FIG. 61 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 62 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 63 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 64 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 65 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device in another embodiment of the present invention;
FIG. 66 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention;
FIG. 67 is a plan view showing a lead pattern formed on one surface of the tape carrier.
FIG. 68 is a plan view showing a lead pattern formed on one surface of the tape carrier.
FIG. 69 is a plan view showing a lead pattern formed on one surface of the tape carrier.
FIG. 70 is a cross-sectional view showing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 71 is a cross-sectional view showing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 72 is a cross-sectional view showing a semiconductor integrated circuit device according to another embodiment of the present invention.
FIG. 73 is a functional block diagram showing a system configuration example using the semiconductor integrated circuit device of the present invention.
FIG. 74 is a functional block diagram showing a system configuration example using the semiconductor integrated circuit device of the present invention.
FIG. 75 is a functional block diagram showing a system configuration example using the semiconductor integrated circuit device of the present invention.
FIG. 76 is a functional block diagram showing a system configuration example using the semiconductor integrated circuit device of the present invention.
77 is a functional block diagram showing a system configuration example using the semiconductor integrated circuit device of the present invention. FIG.
78 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors; FIG.
FIG. 79 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 80 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 81 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process investigated by the present inventors;
FIG. 82 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 83 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process studied by the present inventors.
FIG. 84 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 85 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 86 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
87 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors. FIG.
88 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors. FIG.
FIG. 89 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 90 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 91 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process investigated by the present inventors.
FIG. 92 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 93 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
FIG. 94 is a cross-sectional view showing a microcomputer, flash memory, DRAM, and ASIC mixed process examined by the present inventors.
[Explanation of symbols]
1A, 1B TCP
2a, 2b, 2c, 2d tape carrier
3a, 3b Device hole
4 Bump electrode
5a, 5b lead
6 Potting resin
7 Solder resist
8a, 8b, 8c, 8d Through hole
9 Solder bump
10 Adhesive
11 Solder
11p solder paste
12a, 12b Cu foil hole
14 Printed circuit board
15 electrodes
16 Radiation fin
17 Mold resin
18 pin
19a, 19b Anisotropic conductive film
20 wires
100 Semiconductor substrate
101 p-type well
102 Field oxide film
103 Tunnel oxide film
104 floating gate
105 Second gate insulating film (ONO film)
106, 107 Gate oxide film
108 Gate electrode
109 Control gate
110, 111 gate electrode
112 n ⁺ Type semiconductor region
113 n ^- Type semiconductor region
114 Sidewall spacer
115 n ⁺ Type semiconductor region
116 Silicon oxide film
117 plug
118 n-type semiconductor region
119 Silicon oxide film
120 Lower electrode
121 capacitive insulation film
122 Upper electrode
123 Silicon oxide film
124 metal wiring
125 Silicon oxide film
126 Metal wiring
130 Gate oxide film
A Logic circuit
AD chip
BL bit line
D chip
F Flash memory
M microcomputer
MF chip
MFA chip

Claims (11)

The semiconductor chip is positioned in the device hole formed in the insulating substrate,
One end of a plurality of conductors partially formed on the first surface of the insulating substrate is connected to a plurality of connection electrodes formed on the main surface of the semiconductor chip,
The other ends of the plurality of conductors are respectively connected to conductive materials embedded in a plurality of through holes arranged along the side of the insulating substrate,
A plurality of packages having a structure in which the semiconductor chip is sealed with a mold resin are stacked in accordance with the positions of the through holes,
The conductive materials embedded in the through holes are connected to each other to form a composite package,
The plurality of semiconductor chips in the composite package are collectively sealed with the mold resin,
The plurality of semiconductor chips in the composite package are semiconductor chips of different types.
The thickness of the mold resin is the same as the thickness of the insulating substrate stacked in plurality. The semiconductor device according to claim 1, wherein the conductor is a lead, a wiring layer, a bonding wire, or a combination thereof formed on the first surface of the insulating substrate. Of the plurality of stacked packages, an external connection connected to the conductive material embedded in the through hole is provided on a second surface which is the back surface of the first surface of the insulating substrate of the lowermost package. The semiconductor device according to claim 1, further comprising a terminal. The semiconductor device according to claim 1, wherein the through holes are arranged in a peripheral portion of the insulating substrate. The semiconductor device according to claim 1, wherein the insulating substrate is made of a polyimide resin film. A package stacking terminal and a substrate mounting terminal disposed on both front and back surfaces of the insulating substrate are provided outside a sealing portion in which the semiconductor chip is sealed with the mold resin. Item 14. A semiconductor device according to Item 1. 7. The semiconductor device according to claim 6, wherein the package stacking terminal disposed on the surface side of the insulating substrate is an upper package mounting land. The semiconductor device according to claim 6, wherein the package stacking terminal or the substrate mounting terminal disposed on the back side of the insulating substrate has a solder ball structure. A semiconductor chip is positioned in a device hole formed in the wiring board, a connection electrode formed on the main surface of the semiconductor chip and the wiring board are connected by a bonding wire, and the semiconductor chip is sealed with a mold resin. A semiconductor device in which a plurality of packages are stacked,
The plurality of semiconductor chips in the plurality of packages are collectively sealed with the mold resin,
The thickness of the mold resin is the same as the thickness of the wiring board laminated in plural,
The plurality of packages are stacked by aligning common connection terminals formed on the wiring board and connecting the connection terminals to each other. The connection terminals formed on the wiring board are formed on both front and back surfaces of the wiring board through through holes arranged along a peripheral portion of a specific side of the wiring board,
The semiconductor device according to claim 9, wherein the connection terminals formed on both front and back surfaces of the wiring board are electrically connected to each other in pairs. The connection terminal formed on the front surface side of the wiring board constitutes an upper package mounting land, and the connection terminal formed on the rear surface side constitutes a connection terminal for the lower package or an external connection terminal. The semiconductor device according to claim 10.

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