JP4021930B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to, for example, a one-chip mixed type semiconductor integrated circuit device in which a plurality of functional circuits having different functions are mixedly mounted on a single semiconductor chip, and a semiconductor integrated circuit that suppresses electrical interference between chips during multi-testing. The present invention relates to a circuit device.

  There is an increasing demand for multi-functionality, miniaturization, and low price mainly in the field of products using semiconductor devices, especially personal computers, mobile phones, game machines and the like.

  The system becomes more complex as multi-functionality is promoted. When the system becomes complicated, semiconductor devices having various functions are required, and a huge capacity of memory is required. For this reason, the number of single semiconductor devices required for constructing the system increases.

  In a single semiconductor device, many functions are being integrated into one chip year by year, particularly with a processor, and the size of the single semiconductor device has been reduced. The memory device is also the same, and the capacity integrated on one chip is increasing, and it is also downsized.

  However, the progress of multi-function is rapid, and the progress of miniaturization has been slowing down.

  Therefore, in recent years, multi-chip modules in which semiconductor chips having different functions are accommodated in one package have appeared, and the progress of miniaturization of semiconductor products has been promoted. A multichip module accommodates a good semiconductor chip in one package. For this reason, an assembly process for assembling a non-defective semiconductor chip is required as compared with a single semiconductor device. If a connection failure or the like occurs during this assembly process, a defective product may be included even if a good semiconductor chip is included, which hinders reduction in manufacturing costs. Under such circumstances, it is difficult to say that the multichip module is a technology that can satisfy the demand for price reduction.

  In view of such circumstances, recently, a technique for mounting a plurality of functional circuits having different functions on one semiconductor chip, so-called system-on-silicon technique, has been sought. System-on-silicon technology has the potential to satisfy all of the demands for multifunction, size reduction, and price reduction.

  System-on-silicon technology currently has the following technical problems to be solved, for example.

(1) Accurately measure characteristics of a plurality of functional circuits mixed in one semiconductor chip and having different functions at the time of testing. (2) Each of a plurality of functional circuits having different functions. Maximizing the characteristics of a single semiconductor chip

The present invention has been made in view of the above circumstances, and a first object of the invention is to provide characteristics of each of a plurality of functional circuits which are mixedly mounted on one semiconductor chip and have different functions. Another object of the present invention is to provide a one-chip mixed type semiconductor integrated circuit device that can be measured accurately during a test.
Another object of the present invention is to provide a one-chip mixed type semiconductor integrated circuit device capable of maximizing the characteristics of a plurality of functional circuits having different functions from each other and mounted on a single semiconductor chip.
A third object is to provide electrical interference between the semiconductor integrated circuit devices, particularly power supply, even if the test of the semiconductor integrated circuit device is performed simultaneously on a single wafer with a plurality of semiconductor integrated circuit devices. An object of the present invention is to provide a semiconductor integrated circuit device having a structure capable of suppressing interference between voltages and measuring characteristics of each semiconductor integrated circuit device with high accuracy.
A fourth object is to provide static current consumption characteristics of each semiconductor integrated circuit device even when a static current consumption test of the semiconductor integrated circuit device is simultaneously performed on a single wafer by a plurality of semiconductor integrated circuit devices. It is possible to provide a semiconductor integrated circuit device capable of measuring the above with high accuracy.

A semiconductor integrated circuit device according to a first aspect of the present invention includes a first conductive type semiconductor substrate, at least two second conductive type first semiconductor regions formed in the semiconductor substrate, A first conductive type second semiconductor region formed in the second conductive type first semiconductor region is isolated from the semiconductor substrate, and the at least two second conductive type first semiconductor regions are separated from each other. And a semiconductor integrated circuit portion formed of semiconductor elements formed adjacent to each other and formed in the second conductive type first semiconductor region and the first conductive type second semiconductor region, and the semiconductor In order to apply an operating voltage to the integrated circuit portion, the first semiconductor region and the second semiconductor region have at least one high potential power terminal and low potential power terminal, and the at least two second potential terminals are provided. Isolation of conductive type first semiconductor region And besides formed adjacent areas, when configuring the test time and the semiconductor integrated circuit, which comprises a terminal for applying a bias potential to the semiconductor substrate.

A semiconductor integrated circuit device according to a second aspect of the present invention includes a first conductivity type semiconductor substrate, at least two second conductivity type first semiconductor regions formed in the semiconductor substrate, and A first conductive type second semiconductor region formed in the second conductive type first semiconductor region is isolated from the semiconductor substrate, and the at least two second conductive type first semiconductor regions are separated from each other. And a plurality of semiconductor elements formed in the first semiconductor region and the second semiconductor region and constituting a processor circuit, the other first semiconductor region, and the other second A plurality of semiconductor elements formed in a semiconductor region and constituting a static memory circuit; a high-potential power supply terminal and a low-potential power supply terminal for supplying an operating voltage to the processor circuit and the static memory circuit; Above Separating two or more first semiconductor region of a second conductivity type even without, and in addition formed adjacent areas, when configuring the test time and the semiconductor integrated circuit, applying a bias potential to the semiconductor substrate Terminal.

A semiconductor integrated circuit device according to a third aspect of the present invention includes a first conductivity type semiconductor substrate, a second conductivity type first well formed in the first conductivity type semiconductor substrate, and the first well. A first conductivity type second well formed therein, a second conductivity type third well formed in the first conductivity type semiconductor substrate, and a first conductivity type formed in the third well. A plurality of fourth functional wells, a plurality of first functional circuits formed in the first well and the second well, wherein the first well and the third well are separated and adjacent to each other. A semiconductor element, a plurality of semiconductor elements constituting a second functional circuit formed in the third well and the fourth well, and a first power supply means for applying an operating power to the first functional circuit; Second power supply means for applying operating power to the second functional circuit; and The conductivity type of the semiconductor substrate, when configuring the test time and the semiconductor integrated circuit unit comprises a, a terminal for applying the semiconductor bias potential.

According to the present invention, a one-chip mixed type semiconductor integrated circuit in which the characteristics of each of a plurality of functional circuits having different functions are mixedly mounted on a single semiconductor chip and can be accurately measured during a test. Equipment can be provided.
Further, it is possible to provide a one-chip mixed type semiconductor integrated circuit device capable of maximizing the characteristics of a plurality of functional circuits having different functions from each other and mounted on a single semiconductor chip.
Further, even when a test of a semiconductor integrated circuit device is performed simultaneously on a single wafer with a plurality of semiconductor integrated circuit devices, electrical interference between the semiconductor integrated circuit devices, particularly interference between power supply voltages is suppressed. Therefore, it is possible to provide a semiconductor integrated circuit device having a structure capable of measuring characteristics of each semiconductor integrated circuit device with high accuracy.
According to the present invention, even if the static current consumption test of the semiconductor integrated circuit device is performed simultaneously on a single wafer with a plurality of semiconductor integrated circuit devices, the static current consumption characteristics of the individual semiconductor integrated circuit devices can be obtained. A semiconductor integrated circuit device capable of measuring with high accuracy can be provided.

  Several embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  1A and 1B are diagrams showing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along line 1B-1B in FIG. (C) is sectional drawing which follows the 1C-1C line | wire in (A) figure.

  As shown in FIGS. 1A to 1C, a semiconductor integrated circuit chip 1 is formed with a processor 2, SRAM 3, DRAM 4, and Flash-EEPROM 5 as functional circuits. These functional circuits are isolated from each other by an isolated region 10 provided in the chip 1. Further, the isolated region 10 is in contact with the side surface of the chip 1 over the entire circumference.

  In the description of the embodiment of the present invention, the processor 2 is basically configured by a logic circuit such as a control circuit such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor), or an arithmetic circuit in addition to a microprocessor. Is defined as including

  Similarly, the SRAM 3 is defined to include a memory circuit basically composed of a logic circuit such as a cross-coupled latch circuit in addition to the SRAM.

  Similarly, the DRAM 4 is defined to include a synchronous control DRAM in addition to the asynchronous control DRAM.

  Similarly, the Flash-EEPROM 5 is defined to include a NAND type as well as a NOR type.

  FIG. 2 is a plan view when the semiconductor integrated circuit device according to the first embodiment of the present invention is formed on a wafer.

  As shown in FIG. 2, when the plurality of chips 1 are formed on the silicon wafer 11, the isolated region 10 is in contact with the entire side surface of the chip 1. They are isolated from each other by the rate region 10.

  3 is an enlarged view of the wafer shown in FIG. 2. FIG. 3A is a plan view inside a two-dot chain line frame 3A in FIG. 2, and FIG. 3B is a line 3B-3B in FIG. A sectional view taken along line (C) is a sectional view taken along line 3C-3C in FIG.

  As shown in FIGS. 3A to 3C, there is a dicing line 12 between each chip. The wafer 11 is diced along the dicing line 12. Thereby, each chip 1 is separated from the wafer 11. At this time, the isolation region 10 is also formed in the dicing line 12 so that the isolation region 10 contacts the entire circumference of the side surface of the chip 1.

  FIG. 4 is a plan view when the semiconductor integrated circuit device according to the first embodiment of the present invention is being tested.

  As shown in FIG. 4, the probe card 100 includes measurement units 101 </ b> A to 101 </ b> D corresponding to the four chips 1. A probe 102 is led out to each of the measurement units 101A to 101D. On the edge of the probe card 100, a contactor 103 for electrically connecting the probe 102 to a wafer prober (not shown) is provided. The probe 102 is in electrical contact with the pad 104 of the chip 1. The wafer prober applies an operating voltage and a test pattern to the four chips 1 simultaneously via the probe 102. As a result, the four chips 1 are tested at the same time, and their characteristics are measured to determine whether the chip 1 is good or bad.

  FIG. 5 is a diagram showing a wafer probing test system.

  In a normal test system, one test station is assigned to one test apparatus (single station type). On the other hand, in the system shown in FIG. 5, a plurality of test stations 200 </ b> A and 200 </ b> B are assigned to one test apparatus 300. Such a system is called a multi-station type, and shortens the test time per chip as compared with the single station type. The apparatus according to the first embodiment of the present invention is tested using a single station type or a multi-station type test system as shown in FIG.

  In the device according to the first embodiment, the functional circuits such as the processor 2, the SRAM 3, the DRAM 4, and the Flash-EEPROM 5 are separated from each other by the separation region 10. Therefore, each functional circuit can be tested without being affected by other functional circuits. As a result, the characteristics of each of a plurality of functional circuits having different functions mixedly mounted on one chip 1 can be accurately measured.

  The separation region 10 is in contact with the side surface of the chip 1 over the entire circumference. Therefore, even if a plurality of chips 1 are tested at the same time in the state shown in FIG. 4, each of the functional circuits included in the chip 1 is replaced with the functional circuits included in the other chips. Test without being affected. Thereby, the characteristics of each of a plurality of functional circuits having different functions mixedly mounted on one chip 1 can be accurately measured simultaneously on the chip 1.

  Next explained is a semiconductor integrated circuit device according to the second embodiment of the invention.

  FIG. 6 is a sectional view of a semiconductor integrated circuit device according to the second embodiment of the present invention.

  The cross section shown in FIG. 6 is taken when the chip 1 is formed on a silicon wafer.

  As shown in FIG. 6, in the apparatus according to the second embodiment, the isolation region 10 is a P-type silicon substrate (P-SUB). The P-type silicon substrate 10 is, for example, a wafer itself. A plurality of large N-type wells (N-WELL) 22 are provided in the substrate 10. In the apparatus according to the second embodiment, four large wells 22-2 to 22-5 are provided. A processor 2, SRAM 3, DRAM 4, and Flash-EEPROM 5 are formed in each of the four large wells 22-2 to 22-5. The large wells 22-2 to 22-5 are supplied with the optimum power supply potential for each functional circuit. In the semiconductor integrated circuit device according to the second embodiment, the high potential power supply VCC is in the well 22-2, the high potential power supply VDD3 is in the well 22-3, the high potential power supply VDD4 is in the well 22-4, and the well 22-5. Is supplied with a high potential power supply VDD5. The high-potential power supply VCC is an external power supply supplied from outside the chip 1 together with a low-potential power supply VSS (not shown). Internal power generated. The voltage conversion includes a step-down that lowers the level of the external power supply and a step-up that raises the level. The P-type silicon substrate 10 is grounded during actual use and during testing.

  Hereinafter, a detailed cross-sectional structure of each well will be described, and then a power supply system included in the apparatus according to the second embodiment will be described.

  FIG. 7 is a cross-sectional view of the well 22-2 shown in FIG.

  As shown in FIG. 7, a P-type well 23-2 and an N-type well 24-2 are formed in a large N-type well 22-2. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-2. An N-channel MOSFET (hereinafter referred to as NMOS) 1 is formed in the P-type well 23-2. Further, the same high potential power supply VCC as that of the large N-type well 22-2 is supplied to the N-type well 24-2. A P-channel MOSFET (hereinafter referred to as PMOS) 1 is formed in the N-type well 24-2. The N-type well 24-2 has a higher impurity concentration than the large N-type well 22-2. Thereby, the PMOS 1 can be miniaturized, but the N-type well 24-2 may be omitted.

  A P-type well 25-2 is formed in the large N-type well 22-2. A low potential power source VSS (ground potential) is supplied to the P-type well 25-2. An N-type well 26-2 and a P-type well 27-2 are formed in the P-type well 25-2. A high potential power supply VDD2 is supplied to the N-type well 26-2. The power supply VDD2 is different from the power supply VCC, and is an internal power supply generated by converting the external power supply potential in the chip 1. A PMOS 2 is formed in the N-type well 26-2. The P-type well 27-2 is supplied with a low potential power supply VSS. An NMOS 2 is formed in the P-type well 27-2. The P-type well 27-2 has a higher impurity concentration than the P-type well 25-2. The P-type well 27-2 may be omitted similarly to the N-type well 24-2.

  The processor 2 is basically composed of NMOS 1 and 2 and PMOS 1 and 2. However, the processor 2 may be composed only of NMOS 2 and PMOS 2 driven by the internal power supply VDD2. In this case, the NMOS1 and the PMOS1 driven by the external power supply VCC are preferably used for a voltage generation circuit for generating the internal power supply VDD2 from the external power supply VCC, for example. In addition, a plurality of P-type wells similar to the P-type well 25-2 may be formed in the large N-type well 22-2.

  In FIG. 7, reference numeral G indicates the gate of the MOSFET.

  FIG. 8 is a cross-sectional view of the well 22-3 shown in FIG.

  As shown in FIG. 8, a P-type well 23-3 and an N-type well 24-3 are formed in a large N-type well 22-3, respectively. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-3. An NMOS 3 is formed in the P-type well 23-3. The N-type well 24-3 is supplied with the same high potential internal power supply VDD3 as the large N-type well 22-3. A PMOS 3 is formed in the N-type well 24-3. The N-type well 24-3 has a higher impurity concentration than the large N-type well 22-3. The N-type well 24-3 may be omitted.

  A P-type well 25-3 is formed in the large N-type well 22-3. A low potential power supply VSS (ground potential) is supplied to the P-type well 25-3. An N-type well 26-3 and a P-type well 27-3 are formed in the P-type well 25-3. A high potential internal power supply VDD3 'is supplied to the N-type well 26-3. The internal power supply VDD3 ′ is generated by converting the voltage of the internal power supply VDD3 in the chip 1. A PMOS 4 is formed in the N-type well 26-3. The P-type well 27-3 is supplied with a low potential power supply VSS. An NMOS 4 is formed in the P-type well 27-3. The P-type well 27-3 has a higher impurity concentration than the P-type well 25-3. The P-type well 27-3 may not be provided similarly to the N-type well 24-3.

  The SRAM 3 basically includes NMOSs 3 and 4 and PMOSs 3 and 4. However, the SRAM 3 may include only NMOSs 4 and PMOSs 4 driven by the internal power supply VDD3 ′. In this case, the NMOS 3 and the PMOS 3 driven by the internal power supply VDD3 are preferably used for a voltage generation circuit for generating the internal power supply VDD3 ′ from the internal power supply VDD3, for example. Further, a plurality of P-type wells similar to the P-type well 25-3 may be formed in the large N-type well 22-3.

  In FIG. 8, reference numeral G indicates the gate of the MOSFET.

  9A and 9B are cross-sectional views of the well 22-4 shown in FIG.

  As shown in FIGS. 9A and 9B, a P-type well 23-4 and an N-type well 24-4 are formed in a large N-type well 22-4, respectively. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-4. An NMOS 5 is formed in the P-type well 23-4. The N-type well 24-4 is supplied with the same high potential internal power supply VDD4 as the large N-type well 22-4. A PMOS 5 is formed in the N-type well 24-4. The N-type well 24-4 has a higher impurity concentration than the large N-type well 22-4. The N-type well 24-4 may be omitted.

  Further, in the large N-type well 22-4, three P-type wells 25A-4, 25B-4, and 25C-4 are formed.

  A negative potential power supply VBB (about −2 to −3 V) is supplied to the first P-type well 25A-4. The negative potential power supply VBB is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A dynamic memory cell transistor is formed in the P-type well 25A-4.

  A low potential power supply VSS (ground potential) is supplied to the second P-type well 25B-4. An N-type well 26B-4 and a P-type well 27B-4 are formed in the P-type well 25B-4. A high potential internal power supply VDD4 'is supplied to the N-type well 26B-4. The internal power supply VDD4 ′ is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A PMOS 6 is formed in the N-type well 26B-4. The P-type well 27B-4 is supplied with a low potential power supply VSS. An NMOS 6 is formed in the P-type well 27B-4. The P-type well 27B-4 has a higher impurity concentration than the P-type well 25B-4. The P-type well 27B-4 may be omitted similarly to the N-type well 24-4.

  A negative potential power supply VBB (about −2 to −3 V) is supplied to the third P-type well 25C-4. An N-type well 26C-4 and a P-type well 27C-4 are formed in the P-type well 25C-4, respectively. A high potential internal power supply VDD4 ″ is supplied to the N-type well 26C-4. The internal power supply VDD4 ″ is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A PMOS 7 is formed in the N-type well 26C-4. A negative potential power supply VBB is supplied to the P-type well 27C-4. An NMOS 7 is formed in the P-type well 27C-4. The P-type well 27C-4 has a higher impurity concentration than the P-type well 25C-4. The P-type well 27C-4 may be omitted in the same manner as the N-type well 24-4.

  The memory cell array of the DRAM 4 is composed of dynamic memory cell transistors, and the peripheral circuit of the DRAM 4 is composed of NMOS 5 and 6 and PMOS 5 and 6. The peripheral circuit of the DRAM 4 may be configured by only the NMOS 6 and the PMOS 6 driven by the internal power supply VDD4 ′. In this case, the NMOS 5 and the PMOS 5 driven by the internal power supply VDD4 are preferably used in a voltage generation circuit that generates the internal power supplies VDD4 ′, VDD4 ″, and VBB from the internal power supply VDD4, for example.

  The peripheral circuit of the DRAM 4 includes a circuit that uses the boosted potential VPP, such as a word line driver. In order to configure such a circuit, an N-type well to which the boosted potential VPP is supplied may be formed in the P-type well 25B-4 or the like.

  The NMOS 7 and the PMOS 7 formed in the P-type well 25C-4 supplied with the negative potential power supply VBB are formed in, for example, an input / output circuit for exchanging signals with the outside of the chip 1 or other wells. It may be used to constitute an internal interface circuit for exchanging signals with other functional circuits formed on the chip 1 such as the processor 2 and driven by different power sources. A surge may be input to the input / output circuit and the internal interface circuit. In order to clamp this surge, a negative potential VBB is supplied to the P-type well 25C-4. Such a P-type well to which a negative potential is supplied may be provided not only in the N-type well 22-4 but also in each of the N-type wells 22-2, 22-3, 22-5. An input / output circuit that exchanges signals with the outside of the chip 1 and an internal interface circuit that exchanges signals with other functional circuits are preferably formed in a P-type well to which a negative potential is supplied.

  9A and 9B, reference symbol G refers to the gate of the MOSFET, reference symbol BL refers to the bit line, reference symbol WL refers to the word line, and reference symbol PL refers to the plate electrode of the memory capacitor. Reference numeral SN denotes a storage electrode of the memory capacitor.

  FIGS. 10A and 10B are cross-sectional views of the well 22-5 shown in FIG.

  As shown in FIGS. 10A and 10B, a P-type well 23-5 and an N-type well 24-5 are formed in a large N-type well 22-5. The P-type well 23-5 is supplied with a low potential power source VSS (ground potential). An NMOS 9 is formed in the P-type well 23-5. The N-type well 24-5 is supplied with the same high potential internal power supply VDD5 as the large N-type well 22-5. A PMOS 9 is formed in the N-type well 24-5. The N-type well 24-5 has a higher impurity concentration than the large N-type well 22-5. The N-type well 24-5 may be omitted.

  Furthermore, in the large N-type well 22-5, two P-type wells 25A-5 and 25B-5 are formed.

  A low potential power supply VSS (ground potential) is supplied to the first P-type well 25A-5. An N-type well 26A-5 and a P-type well 27A-5 are formed in the P-type well 25A-5, respectively. A high potential internal power supply VDD5 ″ is supplied to the N-type well 26A-5. The internal power supply VDD5 ″ is generated by converting the voltage of the internal power supply VDD5 within the chip 1. A PMOS 8 is formed in the N-type well 26A-5. The P-type well 27A-5 is supplied with a low potential power supply VSS. An NMOS 8 is formed in the P-type well 27A-5. The P-type well 27A-5 has a higher impurity concentration than the P-type well 25A-5. The P-type well 27A-5 may not be provided in the same manner as the N-type well 24-5.

  Further, an N-type well 26A0-5 is further formed in the first P-type well 25A-5. The N-type well 26A0-5 is supplied with the high potential internal power supply VDD5 'and the boosted potential VEE while being switched to each other. The internal power supply VDD5 ′ and the boosted potential VEE are generated by converting the voltage of the internal power supply VDD5 within the chip 1. A P-type well 28-5 is formed in the N-type well 26A0-5. The P-type well 28-5 is supplied with a low potential power supply VSS, a boosted potential VEE, and a step-down potential VBB, which are switched to each other. The step-down potential VBB is generated by converting the voltage of the internal power supply VDD5 in the chip 1. NAND type memory cell transistors are formed in the P type well 28-5. When erasing data from the NAND type memory cell transistor, the control gate CG is grounded, and the boosted potential VEE is supplied to the N type well 26A0-5 and the P type well 28-5, respectively. As a result, electrons are extracted from the floating gate FG to the P-type well 28-5, and data is erased. On the other hand, when data is written to the NAND type memory cell transistor, the control gate CG is set to the program voltage, the potential VDD5 ′ is supplied to the N type well 26A0-5, and the step-down potential VBB is supplied to the P type well 28-5. Thereby, electrons are injected into the floating gate FG from the channel below the floating gate FG, and data is written. When reading data stored in the NAND type memory cell transistor, the control gate CG is used as a read voltage, the potential VDD5 ′ is supplied to the N type well 26A0-5, and the low potential VSS is supplied to the P type well 28-5. Supply. As a result, data “0, 1” represented by whether or not current flows through the channel is determined according to the charged state of the floating gate FG, and the data is read out to the bit line BL.

  A low potential power supply VSS (ground potential) is supplied to the second P-type well 25B-5. An N-type well 26B-5 and a P-type well 27B-5 are formed in the P-type well 25B-5, respectively. The N-type well 26B-5 is supplied with a high potential internal power supply VDD5 ″. The internal power supply VDD5 ″ is generated by converting the voltage of the internal power supply VDD5 within the chip 1. A PMOS 10 is formed in the N-type well 26B-5. The P-type well 27B-5 is supplied with a low potential power supply VSS. An NMOS 10 is formed in the P-type well 27B-5. The P-type well 27B-5 has a higher impurity concentration than the P-type well 25B-5. The P-type well 27B-5 may not be provided in the same manner as the N-type well 24-5.

  The memory cell array of the Flash-EEPROM 5 is composed of NAND type memory cell transistors, and the peripheral circuit of the Flash-EEPROM 5 is composed of NMOS 8, 9, 10 and PMOS 8, 9, 10. The peripheral circuit of the Flash-EEPROM 5 may be composed of only the NMOSs 8 and 10 and the PMOSs 8 and 10 driven by the internal power supplies VDD5 ″ and VDD5 ″. In this case, the NMOS 9 and the PMOS 9 driven by the internal power supply VDD5 are used, for example, in a voltage generation circuit that generates the internal power supplies VDD5 ′, VDD5 ″, VDD5 ″, VBB, and VEE from the internal power supply VDD5. good.

  In FIGS. 10A and 10B, the reference symbol G indicates the gate of the MOSFET.

  FIG. 11 is a block diagram of a power supply system included in the apparatus according to the second embodiment.

  As shown in FIG. 11, a large N-type well 22-2 is driven by an external power supply VCC, VSS, and has a voltage generation circuit 30-2 that generates internal power supplies VDD2, VDD3, VDD4, and VDD5 from the external power supply VCC. Is formed. The internal power supply VDD2 is a high-potential power supply that is used by a part or the whole of the processor 2. The internal power supply VDD3 is a high potential power supply supplied to the large N-type well 22-3, the internal power supply VDD4 is a high potential power supply supplied to the large N-type well 22-4, and the internal power supply VDD5 is a large N-type well 22-. 5 is a high-potential power source supplied to 5. In the larger N-type well 22-2, a control circuit 31-2 is formed which is driven by external power supplies VCC and VSS, and controls generation of internal power supplies VDD3, VDD4 and VDD5 by control signals TV3, TV4 and TV5. Yes. Further, internal voltage monitor terminals VDD3M to VDD5M are connected to the voltage generating circuit 30-2. The level of the voltage actually generated by the voltage generation circuit 30-2 can be monitored by this monitoring terminal.

  In the large N-type well 22-3, a voltage generation circuit 30-3 that is driven by the internal power supply VDD3 and the external power supply VSS and generates the internal power supplies VDD3 ′ and VDD3 ″ from the internal power supply VDD3 is formed. Each of the internal power supplies VDD3 ′ and VDD3 ″ is a high-potential power supply used by a part of or the entire SRAM 3 (the internal power supply VDD3 ″ shown in FIG. 11 is omitted in FIG. 8). ing). In the larger N-type well 22-3, a control circuit 31-3 that is driven by the internal power supply VDD3 and the external power supply VSS and controls the generation of the internal power supplies VDD3 ′ and VDD3 ″ by the control signal TO3 is formed. . Further, the internal power supply monitoring terminals VDD3′M and VDD3 ″ M are connected to the voltage generating circuit 30-3. With this monitoring terminal, the voltage level actually generated by the voltage generation circuit 30-3 can be monitored.

  The large N-type well 22-4 is formed with a voltage generation circuit 30-4 that is driven by the internal power supply VDD4 and the external power supply VSS and generates the internal power supplies VDD4 ′, VDD4 ″, and VBB from the internal power supply VDD4. . The internal power supplies VDD4 ′ and VDD4 ″ are high-potential power supplies that are used in a part or the whole of the DRAM 4, respectively. The internal power supply VBB is a negative potential power supply used in the DRAM 4. In the larger N-type well 22-4, a control circuit 31-4 that is driven by the internal power supply VDD4 and the external power supply VSS and controls the generation of the internal power supplies VDD4 ′, VDD4 ″, and VBB by the control signal TO4 is formed. ing. Further, the internal power supply monitoring terminals VDD4′M, VDD4 ″ M, and VBBM are connected to the voltage generation circuit 30-4. The level of the voltage actually generated by the voltage generation circuit 30-4 can be monitored by this monitoring terminal.

  In the large N-type well 22-5, there is formed a voltage generation circuit 30-5 that is driven by the internal power supply VDD5 and the external power supply VSS and generates the internal power supplies VDD5 ′, VDD5 ″, VBB, and VEE from the internal power supply VDD5. ing. Each of the internal power supplies VDD5 ′ and VDD5 ″ is a high-potential power supply used in a part or the whole of the Flash-EEPROM 5 (in addition, the internal power supply VDD5 ″ shown in FIG. Is omitted). The internal power supply VBB is a negative potential power supply used in the Flash-EEPROM 5. The internal power supply VEE is a boosted potential power supply used in the Flash-EEPROM 5. The larger N-type well 22-5 is driven by an internal power supply VDD5 and an external power supply VSS, and a control circuit 31-5 that controls generation of the internal power supplies VDD5 ′, VDD5 ″, VBB, and VEE by a control signal TO5. Is formed. Furthermore, internal voltage monitor terminals VDD5′M, VDD5 ″ M, VBBM, and VEEM are connected to the voltage generating circuit 30-5. The level of voltage actually generated by the voltage generation circuit 30-5 can be monitored by this monitoring terminal.

  The control signal input terminal and the monitor terminal may be at least at the time of testing. For this reason, the control signal input terminal and the monitor terminal may be provided on the dicing line, for example, without being provided on the chip 1.

  12A and 12B are diagrams showing the generation timings of the external power supply and the internal power supply. FIG. 12A is a diagram showing the generation timing during actual use, and FIGS. FIG.

  As shown in FIG. 12 (A), the power supply system shown in FIG. 11 receives internal power supply VCC at time t0 and then supplies the internal power to wells 22-3 to 22-5 at time t1 in actual use. The power supplies VDD3 to VDD5 are generated simultaneously. As a result, potentials are applied to all of the wells 22-2 to 22-5, and all the functional circuits included in the chip 1 become operable.

  On the other hand, as shown in FIGS. 12B and 12C, at the time of the test, after receiving the supply of the external power supply VCC at the time t0, the internal power supply VDD3 to be supplied to the wells 22-3 to 22-5. VDD5 is generated at an arbitrary time (t01 to t08) by the input of the control signals TV3 to TV5. Thereby, potentials can be arbitrarily applied to the wells 22-3 to 22-5, and only selected ones of the plurality of functional circuits included in the chip 1 can be arbitrarily operated. For example, the internal power supply VDD4 is generated, and the generation of the internal power supplies VDD3 and VDD5 is stopped. As a result, power is supplied to the DRAM 4 so that the DRAM 4 can operate. However, since no power is supplied to the SRAM 3 and the Flash-EEPROM 5, no operation is performed.

  Note that the control signals TO3 to TO5 also control the generation timing of the internal power supply, similarly to the control signals TV3 to TV5. According to this, it is possible to arbitrarily operate only selected ones of several circuit blocks constituting the functional circuit. For example, only the internal power supply VDD3 ′ is generated, and the generation of the internal power supply VDD3 ″ is stopped. As a result, power is supplied to the circuit block using the internal power supply VDD 3 ′ in the SRAM 3, so that the circuit block using the internal power supply VDD 3 ″ can be operated. I do not.

  In the device according to the second embodiment, functional circuits such as the processor 2, SRAM 3, DRAM 4, and Flash-EEPROM 5 are formed in the N-type wells 22-2 to 22-5, respectively. Are separated from each other by PN junctions of the N-type wells 22-2 to 22-5 and the P-type silicon substrate 10. Therefore, each functional circuit can be tested without being affected by other functional circuits. As a result, the characteristics of each of a plurality of functional circuits having different functions mixedly mounted on one chip 1 can be accurately measured.

  Further, since the P-type silicon substrate 10 is a wafer itself, the functional circuits are separated from each other even between the chips. For this reason, a plurality of chips 1 can be simultaneously tested without being affected by the function circuits included in the other chips. Thereby, the characteristics of each of a plurality of functional circuits having different functions mixedly mounted on one chip 1 can be accurately measured simultaneously on the plurality of chips 1.

  Further, since different potentials are supplied to each of the wells 22-2 to 22-5, a power supply potential that can maximize the characteristics of each functional circuit can be applied to each functional circuit.

  In addition, since the power supply system of the apparatus according to the second embodiment can arbitrarily stop the generation of the internal power supply during the test, only a selected one of the plurality of functional circuits is operated. Of the several circuit blocks constituting the functional circuit, only selected ones can be operated. For this reason, it is possible to operate only the functional circuit to be inspected and not to operate other functional circuits, particularly in the inspection process. If the inspection is performed in this manner, the functional circuit being inspected is not affected by other functional circuits, so that accurate characteristics can be measured. For example, in a circuit having a large storage capacity such as DRAM 4 or Flash-EEPROM 5, there is an inspection process for specifying a defective row and a defective column. At this time, if the power supply of other functional circuits is turned off, Rows and defective columns can be specified more accurately.

  When the processor 2 tests the operation of accessing the DRAM 4, only the processor 2 and the DRAM 4 are turned on, and the other functional circuits, that is, the SRAM 3 and the Flash-EEPROM 5 are turned off. In this way, the processor 2 and the DRAM 4 are not affected by other functional circuits, so that the test accuracy is improved. Similarly, when the processor 2 tests the operation accessing the SRAM 3, and when the processor 2 tests the operation accessing the Flash-EEPROM 5, the power of other functional circuits is turned off. This improves the test accuracy.

  Also, when a large number of chips 1 are being measured at the same time, if there is a defective chip 1 and a large current is applied to the substrate 10, other chips 1 may be affected and accurate measurement may not be possible. There is sex. In this case, all the power supplies of the functional circuits included in the defective chip 1 are turned off using the above power supply system. In this way, even if there is a defective chip 1, other chips 1 are not affected.

  Next explained is a semiconductor integrated circuit device according to the third embodiment of the invention.

  FIG. 13 is a sectional view of a semiconductor integrated circuit device according to the third embodiment of the present invention.

  As shown in FIG. 13, in the apparatus according to the third embodiment, the processor 2 and the SRAM 3 are formed in the large well 22-2. A high potential power supply VCC is supplied to the well 22-2.

  14A and 14B are cross-sectional views of the well 22-2 shown in FIG.

  As shown in FIGS. 14A and 14B, a P-type well 23-2 and an N-type well 24-2 are formed in a large N-type well 22-2, respectively. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-2. An N-channel MOSFET (hereinafter referred to as NMOS) 1 is formed in the P-type well 23-2. Further, the same high potential power supply VCC as that of the large N-type well 22-2 is supplied to the N-type well 24-2. A P-channel MOSFET (hereinafter referred to as PMOS) 1 is formed in the N-type well 24-2. The N-type well 24-2 has a higher impurity concentration than the large N-type well 22-2. The N-type well 24-2 may be omitted.

  In the large N-type well 22-2, a first P-type well 25A-2 and a second P-type well 25B-2 are formed. A low potential power supply VSS (ground potential) is supplied to each of the P-type wells 25A-2 and 25B-2.

  An N-type well 26A-2 and a P-type well 27A-2 are formed in the first P-type well 25A-2. A high potential power supply VDD2 is supplied to the N-type well 26A-2. The power supply VDD2 is different from the power supply VCC, and is an internal power supply generated by converting the external power supply potential in the chip 1. A PMOS 2 is formed in the N-type well 26A-2. The P-type well 27A-2 is supplied with a low potential power supply VSS. An NMOS 2 is formed in the P-type well 27A-2. The P-type well 27A-2 has a higher impurity concentration than the P-type well 25A-2. The P-type well 27A-2 may not be provided in the same manner as the N-type well 24-2.

  An N-type well 26B-2 and a P-type well 27B-2 are formed in the second P-type well 25B-2. A high potential power supply VDD3 is supplied to the N-type well 26B-2. The power supply VDD3 is different from the power supply VCC, and is an internal power supply generated by converting the external power supply potential in the chip 1. A PMOS 3 is formed in the N-type well 26B-2. The P-type well 27B-2 is supplied with a low potential power supply VSS. An NMOS 3 is formed in the P-type well 27B-2. The P-type well 27B-2 has a higher impurity concentration than the P-type well 25B-2. The P-type well 27B-2 may not be provided in the same manner as the N-type well 24-2.

  The processor 2 is basically composed of NMOS 1 and 2 and PMOS 1 and 2. However, the processor 2 may be composed only of NMOS 2 and PMOS 2 driven by the internal power supply VDD2. In this case, the NMOS1 and the PMOS1 driven by the external power supply VCC are preferably used for a voltage generation circuit for generating the internal power supply VDD2 from the external power supply VCC, for example.

  The SRAM 3 is basically composed of NMOS 1, 3 and PMOS 1, 3, but the SRAM 3 may be composed of only NMOS 3 and PMOS 3 driven by the internal power supply VDD 3.

  Thus, the processor 2 and the SRAM 3 may be formed in one N-type well 22-2.

  In FIGS. 14A and 14B, reference numeral G indicates the gate of the MOSFET.

  Next explained is a semiconductor integrated circuit device according to the fourth embodiment of the invention.

  FIG. 15 is a sectional view of a semiconductor integrated circuit device according to the fourth embodiment of the present invention.

  As shown in FIG. 15, in the device according to the fourth embodiment, SRAM 3 and DRAM 4 are formed in a large well 22-4. An internal power supply VDD4 is supplied to the well 22-4.

  16A and 16B are cross-sectional views of the well 22-4 shown in FIG.

  As shown in FIGS. 16A and 16B, a P-type well 23-4 and an N-type well 24-4 are formed in a large N-type well 22-4, respectively. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-4. An NMOS 5 is formed in the P-type well 23-4. The N-type well 24-4 is supplied with the same high potential internal power supply VDD4 as the large N-type well 22-4. A PMOS 5 is formed in the N-type well 24-4. The N-type well 24-4 has a higher impurity concentration than the large N-type well 22-4. The N-type well 24-4 may be omitted.

  Further, in the large N-type well 22-4, three P-type wells 25A-4, 25B-4, and 25C-4 are formed.

  A negative potential power supply VBB (about −2 to −3 V) is supplied to the first P-type well 25A-4. The negative potential power supply VBB is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A dynamic memory cell transistor is formed in the P-type well 25A-4.

  A low potential power supply VSS (ground potential) is supplied to the second P-type well 25B-4. An N-type well 26B-4 and a P-type well 27B-4 are formed in the P-type well 25B-4. A high potential internal power supply VDD4 'is supplied to the N-type well 26B-4. The internal power supply VDD4 ′ is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A PMOS 6 is formed in the N-type well 26B-4. The P-type well 27B-4 is supplied with a low potential power supply VSS. An NMOS 6 is formed in the P-type well 27B-4. The P-type well 27B-4 has a higher impurity concentration than the P-type well 25B-4. The P-type well 27B-4 may be omitted similarly to the N-type well 24-4.

  A low potential power supply VSS (ground potential) is supplied to the third P-type well 25C-4. An N-type well 26C-4 and a P-type well 27C-4 are formed in the P-type well 25C-4, respectively. The N-type well 26C-4 is supplied with a high potential internal power supply VDD3. The internal power supply VDD3 is generated by converting the voltage of the internal power supply VDD4 in the chip 1. A PMOS 3 is formed in the N-type well 26C-4. The P-type well 27C-4 is supplied with a low potential power supply VSS. An NMOS 3 is formed in the P-type well 27C-4. The P-type well 27C-4 has a higher impurity concentration than the P-type well 25C-4. The P-type well 27C-4 may be omitted in the same manner as the N-type well 24-4.

  The memory cell array of the DRAM 4 is composed of dynamic memory cell transistors, and the peripheral circuit of the DRAM 4 is composed of NMOS 5 and 6 and PMOS 5 and 6. The peripheral circuit of the DRAM 4 may be configured by only the NMOS 6 and the PMOS 6 driven by the internal power supply VDD4 ′. In this case, the NMOS 5 and the PMOS 5 driven by the internal power supply VDD4 are preferably used in a voltage generation circuit that generates the internal power supplies VDD4 and VDD3 from the internal power supply VDD4, for example.

  The SRAM 3 is basically composed of NMOSs 3, 5, and PMOSs 3, 5. However, the SRAM 3 may be composed of only NMOSs 3, PMOS 3 driven by the internal power supply VDD3.

  Thus, the SRAM 3 and the DRAM 3 may be formed in one N-type well 22-4.

  In FIGS. 16A and 16B, reference symbol G refers to the gate of the MOSFET, reference symbol BL refers to the bit line, reference symbol WL refers to the word line, and reference symbol PL refers to the plate electrode of the memory capacitor. Reference numeral SN denotes a storage electrode of the memory capacitor.

  Next explained is a semiconductor integrated circuit device according to the fifth embodiment of the invention.

  FIG. 17 is a sectional view of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.

  As shown in FIG. 17, in the device according to the fifth embodiment, the DRAM 4 is formed by being distributed in large wells 22A-4 and 22B-4. The well 22A-4 is supplied with the internal power supply VDD4A, and the well 22B-4 is supplied with the internal power supply VDD4B.

  18A and 18B are cross-sectional views of the wells 22A-4 and 22B-4 shown in FIG. 17, respectively.

  As shown in FIGS. 18A and 18B, a P-type well 23A-4 and an N-type well 24A-4 are formed in a large N-type well 22A-4, respectively. The P-type well 23A-4 is supplied with a low potential power source VSS (ground potential). An NMOS 5A is formed in the P-type well 23A-4. The N-type well 24A-4 is supplied with the same high potential internal power supply VDD4A as the large N-type well 22A-4. A PMOS 5A is formed in the N-type well 24A-4. The N-type well 24A-4 has a higher impurity concentration than the large N-type well 22A-4. The N-type well 24A-4 may not be provided.

  Further, two P-type wells 25AA-4 and 25AB-4 are formed in the large N-type well 22A-4.

  A negative potential power supply VBB (about −2 to −3 V) is supplied to the first P-type well 25AA-4. The negative potential power supply VBB is generated by converting the voltage of the internal power supply VDD4A in the chip 1. A dynamic memory cell transistor is formed in the P-type well 25AA-4.

  A low potential power supply VSS (ground potential) is supplied to the second P-type well 25AB-4. An N-type well 26AB-4 and a P-type well 27AB-4 are formed in the P-type well 25AB-4, respectively. A high potential internal power supply VDD4A 'is supplied to the N-type well 26AB-4. The internal power supply VDD4A ′ is generated by converting the voltage of the internal power supply VDD4A within the chip 1. A PMOS 6A is formed in the N-type well 26AB-4. The P-type well 27AB-4 is supplied with a low potential power supply VSS. An NMOS 6A is formed in the P-type well 27AB-4. The P-type well 27AB-4 has a higher impurity concentration than the P-type well 25AB-4. The P-type well 27AB-4 may be omitted in the same manner as the N-type well 24A-4.

  In the large N-type well 22B-4, a P-type well 23B-4 and an N-type well 24B-4 are formed. The P-type well 23B-4 is supplied with a low potential power source VSS (ground potential). An NMOS 5B is formed in the P-type well 23B-4. The N-type well 24B-4 is supplied with the same high potential internal power supply VDD4B as the large N-type well 22B-4. A PMOS 5B is formed in the N-type well 24B-4. The N-type well 24B-4 has a higher impurity concentration than the large N-type well 22B-4. The N-type well 24B-4 may be omitted.

  Further, a P-type well 25BA-4 is formed in the large N-type well 22B-4. A low potential power source VSS (ground potential) is supplied to the P-type well 25BA-4. An N-type well 26BA-4 and a P-type well 27BA-4 are formed in the P-type well 25BA-4. A high potential internal power supply VDD4B 'is supplied to the N-type well 26BA-4. The internal power supply VDD4B ′ is generated by converting the voltage of the internal power supply VDD4B within the chip 1. A PMOS 6B is formed in the N-type well 26BA-4. The P-type well 27BA-4 is supplied with a low potential power supply VSS. An NMOS 6B is formed in the P-type well 27BA-4. The P-type well 27BA-4 has a higher impurity concentration than the P-type well 25BA-4. The P-type well 27BA-4 may not be provided in the same manner as the N-type well 24B-4.

  The memory cell array of the DRAM 4 is composed of dynamic memory cell transistors, and the peripheral circuit of the DRAM 4 is composed of NMOS 5A, 6A, 5B, 6B, PMOS 5A, 6A, 5B, 6B. The peripheral circuit of the DRAM 4 may be configured by only NMOSs 6A and 6B and PMOSs 6A and 6B driven by the internal power supplies VDD4A ′ and VDD4B ′. In this case, the NMOS 5A and PMOS 5A driven by the internal power supply VDD4A are, for example, a voltage generating circuit that generates the internal power supply VDD4A 'from the internal power supply VDD4A, and the NMOS 5B and PMOS 5B driven by the internal power supply VDD4B are, for example, Are preferably used in a voltage generation circuit for generating the internal power supply VDD4B ′ from the power supply.

  In this way, the DRAM 3 may be formed in a distributed manner in the two N-type wells 22A-4 and 22B-4.

  18A and 18B, reference symbol G refers to the gate of the MOSFET, reference symbol BL refers to the bit line, reference symbol WL refers to the word line, and reference symbol PL refers to the plate electrode of the memory capacitor. Reference numeral SN denotes a storage electrode of the memory capacitor.

  Next explained is a semiconductor integrated circuit device according to the sixth embodiment of the invention.

  FIG. 19 is a sectional view of a semiconductor integrated circuit device according to the sixth embodiment of the present invention.

  As shown in FIG. 19, in the apparatus according to the sixth embodiment, the Flash-EEPROM 5 is formed dispersed in large wells 22A-5 and 22B-5. An internal power supply VDD5A is supplied to the well 22A-5, and an internal power supply VDD5B is supplied to the well 22B-5.

  20A and 20B are cross-sectional views of the wells 22A-5 and 22B-5 shown in FIG. 19, respectively.

  As shown in FIGS. 20A and 20B, in the large N-type well 22A-5, a P-type well 23A-5 and an N-type well 24A-5 are formed. The P-type well 23A-5 is supplied with a low potential power source VSS (ground potential). An NMOS 9A is formed in the P-type well 23A-5. The N-type well 24A-5 is supplied with the same high potential internal power supply VDD5A as the large N-type well 22A-5. A PMOS 9A is formed in the N-type well 24A-5. The N-type well 24A-5 has a higher impurity concentration than the large N-type well 22A-5. The N-type well 24A-5 may not be provided.

  Further, a P-type well 25AA-5 is formed in the large N-type well 22A-4. A low potential power source VSS (ground potential) is supplied to the P-type well 25AA-5. An N-type well 26AA-5 and a P-type well 27AA-5 are formed in the P-type well 25AA-5. The N-type well 26AA-5 is supplied with the high potential internal power supply VDD5A ″. The internal power supply VDD5A ″ is generated by converting the voltage of the internal power supply VDD5A within the chip 1. A PMOS 8A is formed in the N-type well 26AA-5. The P-type well 27AA-5 is supplied with a low potential power supply VSS. An NMOS 8A is formed in the P-type well 27AA-5. The P-type well 27AA-5 has a higher impurity concentration than the P-type well 25AA-5. The P-type well 27AA-5 may not be provided in the same manner as the N-type well 24A-5.

  An N-type well 26A0-5 is further formed in the P-type well 25AA-5. The N-type well 26A0-5 is supplied with the high potential internal power supply VDD5A 'and the boosted potential VEE while being switched to each other. The internal power supply VDD5A ′ and the boosted potential VEE are generated by converting the voltage of the internal power supply VDD5A within the chip 1. A P-type well 28-5 is formed in the N-type well 26A0-5. The P-type well 28-5 is supplied with a low potential power supply VSS, a boosted potential VEE, and a step-down potential VBB, which are switched to each other. The step-down potential VBB is generated by converting the voltage of the internal power supply VDD5A within the chip 1. NAND type memory cell transistors are formed in the P type well 28-5.

  In the large N-type well 22B-5, a P-type well 23B-5 and an N-type well 24B-5 are respectively formed. The P-type well 23B-5 is supplied with a low potential power source VSS (ground potential). An NMOS 9B is formed in the P-type well 23B-5. The N-type well 24B-5 is supplied with the same high potential internal power supply VDD5B as the large N-type well 22B-5. A PMOS 9B is formed in the N-type well 24B-5. The N-type well 24B-5 has a higher impurity concentration than the large N-type well 22B-5. The N-type well 24B-5 may be omitted.

  Further, a P-type well 25BA-5 is formed in the large N-type well 22B-4. A low potential power supply VSS (ground potential) is supplied to the P-type well 25BA-5. An N-type well 26BA-5 and a P-type well 27BA-5 are formed in the P-type well 25BA-5. A high potential internal power supply VDD5B ′ is supplied to the N-type well 26BA-5. The internal power supply VDD5B ′ is generated by converting the voltage of the internal power supply VDD5B in the chip 1. A PMOS 10B is formed in the N-type well 26BA-5. The P-type well 27BA-5 is supplied with a low potential power supply VSS. An NMOS 10B is formed in the P-type well 27BA-5. The P-type well 27BA-5 has a higher impurity concentration than the P-type well 25BA-5. The P-type well 27BA-5 may not be provided in the same manner as the N-type well 24B-5.

  The memory cell array of the Flash-EEPROM 5 is composed of NAND type memory cell transistors, and the peripheral circuit of the Flash-EEPROM 5 is composed of NMOS 8A, 9A, 9B, 10B, and PMOS 8A, 9A, 9B, 10B. The peripheral circuit of the Flash-EEPROM 5 may be configured by only the NMOSs 8A, 10B and PMOSs 8A, 10B driven by the internal power supplies VDD5A ″ and VDD5B ′. In this case, the NMOS 9A and the PMOS 9A driven by the internal power supply VDD5A are, for example, the NMOS 9B driven by the internal power supply VDD5B in a voltage generation circuit that generates the internal power supplies VDD5A ′, VDD5A ″, VBB, and VEE from the internal power supply VDD5A. The PMOS 9B is preferably used in, for example, a voltage generation circuit that generates the internal power supply VDD5B ′ from the internal power supply VDD5B.

  In this way, the Flash-EEPROM 53 may be formed in a distributed manner in the two N-type wells 22A-5 and 22B-5.

  20A and 20B, reference numeral G indicates a gate of the MOSFET, reference numeral BL indicates a bit line, reference numeral CG indicates a control gate, and reference numeral FG indicates a floating gate.

  21A and 21B are views showing a semiconductor integrated circuit device according to a seventh embodiment of the present invention. FIG. 21A is a plan view, and FIG. 21B is a sectional view taken along line 21B-21B in FIG. (C) The figure is sectional drawing which follows the 21C-21C line | wire in (A) figure.

  As shown in FIGS. 21A to 21C, a semiconductor integrated circuit chip 1 includes a processor 2, SRAM 3, DRAM 4, Flash-EEPROM 5, D / A converter 6, and analog circuit 7 as functional circuits. Yes. These functional circuits are isolated from each other by an isolated region 10 provided in the chip 1. Further, the isolated region 10 is in contact with the side surface of the chip 1 over the entire circumference.

  Next explained is a semiconductor integrated circuit device according to the eighth embodiment of the invention.

  22A and 22B are cross-sectional views, respectively, of a semiconductor integrated circuit device according to the eighth embodiment of the present invention.

  The cross sections shown in FIGS. 22A and 22B are obtained when the chip 1 is formed on a silicon wafer.

  As shown in FIGS. 22A and 22B, in the apparatus according to the eighth embodiment, the isolation region 10 is a P-type silicon substrate (P-SUB). The P-type silicon substrate 10 is, for example, a wafer itself. A plurality of large N-type wells (N-WELL) 22 are provided in the substrate 10. In the apparatus according to the second embodiment, six large wells 22-2 to 22-7 are provided. In each of the six large wells 22-2 to 22-5, a processor 2, SRAM 3, DRAM 4, Flash-EEPROM 5, D / A converter 6 and analog circuit 7 are formed. The large wells 22-2 to 22-7 are each supplied with an optimum power supply potential for each functional circuit. In the semiconductor integrated circuit device according to the eighth embodiment, the high potential power supply VCC is in the well 22-2, the high potential power supply VDD3 is in the well 22-3, the high potential power supply VDD4 is in the well 22-4, and the well 22-5. The high potential power supply VDD5 is supplied to the well 22-6, the high potential power supply VDD6 is supplied to the well 22-7, and the high potential power supply VDD7 is supplied to the well 22-7. The high-potential power supply VCC is an external power supply that is supplied from the outside of the chip 1 together with a low-potential power supply VSS (not shown). The high-potential power supplies VDD3 to VDD7 respectively convert the external power supply potential into a voltage in the chip 1. Internal power generated.

  FIG. 23 is a cross-sectional view of the well 22-6 shown in FIGS. 22 (A) and 22 (B).

  As shown in FIG. 23, a P-type well 23-6 and an N-type well 24-6 are formed in a large N-type well 22-6. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-6. An NMOS 11 is formed in the P-type well 23-6. The N-type well 24-6 is supplied with the same high potential power supply VDD6 as the large N-type well 22-6. A PMOS 11 is formed in the N-type well 24-6. The N-type well 24-6 has a higher impurity concentration than the large N-type well 22-6. The N-type well 24-6 may be omitted.

  A P-type well 25-6 is formed in the large N-type well 22-6. A low potential power source VSS (ground potential) is supplied to the P-type well 25-6. An N-type well 26-6 and a P-type well 27-6 are formed in the P-type well 25-6, respectively. A high potential power supply VDD6 ′ is supplied to the N-type well 26-6. The power supply VDD6 ′ is an internal power supply generated by converting the voltage of the power supply VDD6 in the chip 1. A PMOS 12 is formed in the N-type well 26-6. The P-type well 27-6 is supplied with a low potential power supply VSS. An NMOS 12 is formed in the P-type well 27-6. The P-type well 27-6 has a higher impurity concentration than the P-type well 25-6. The P-type well 27-6 may be omitted similarly to the N-type well 24-6.

  The D / A converter 6 is basically composed of NMOSs 11 and 12 and PMOSs 11 and 12, but the D / A converter 6 may be composed of only NMOSs 12 and PMOSs 12 driven by the internal power supply VDD6 ′. good. In this case, the NMOS 11 and the PMOS 11 driven by the internal power supply VDD6 are preferably used for a voltage generation circuit for generating the internal power supply VDD6 ′ from the internal power supply VDD6, for example. In addition, a plurality of P-type wells similar to the P-type well 25-6 may be formed in the large N-type well 22-6.

  In FIG. 23, reference symbol G indicates the gate of the MOSFET. FIG. 24 is a cross-sectional view of the well 22-7 shown in FIGS. 22 (A) and 22 (B).

  As shown in FIG. 24, a P-type well 23-7 and an N-type well 24-7 are formed in a large N-type well 22-7, respectively. The P-type well 23-7 is supplied with a low potential power source VSS (ground potential). An NMOS 13 is formed in the P-type well 23-7. The N-type well 24-7 is supplied with the same high potential internal power supply VDD7 as the large N-type well 22-7. A PMOS 13 is formed in the N-type well 24-7. The N-type well 24-7 has a higher impurity concentration than the large N-type well 22-7. The N-type well 24-7 may be omitted.

  A P-type well 25-7 is formed in the large N-type well 22-7. The P-type well 25-7 is supplied with a low potential power source VSS (ground potential). An N-type well 26-7 and a P-type well 27-7 are formed in the P-type well 25-7. The N-type well 26-7 is supplied with the high potential internal power supply VDD7 '. The internal power supply VDD7 ′ is generated by converting the voltage of the internal power supply VDD7 within the chip 1. A PMOS 14 is formed in the N-type well 26-7. The P-type well 27-7 is supplied with a low potential power supply VSS. An NMOS 14 is formed in the P-type well 27-7. The P-type well 27-7 has a higher impurity concentration than the P-type well 25-7. The P-type well 27-7 may be omitted similarly to the N-type well 24-7.

  The analog circuit 7 is basically composed of NMOSs 13 and 14 and PMOSs 13 and 14, but the analog circuit 7 may be composed of only NMOSs 14 and PMOS 14 driven by the internal power supply VDD7 '. In this case, the NMOS 13 and the PMOS 13 driven by the internal power supply VDD7 are preferably used for a voltage generation circuit for generating the internal power supply VDD7 ′ from the internal power supply VDD7, for example. In the large N-type well 22-7, a plurality of P-type wells similar to the P-type well 25-7 may be formed.

  In FIG. 24, reference symbol G indicates the gate of the MOSFET. 25A and 25B are views showing a semiconductor integrated circuit device according to a ninth embodiment of the present invention. FIG. 25A is a plan view, and FIG. 25B is a sectional view taken along line 25B-25B in FIG. (C) The figure is sectional drawing which follows the 25C-25C line in (A) figure.

  As shown in FIGS. 25A to 25C, the semiconductor integrated circuit chip 1 includes an SRAM 3, a DRAM 4, a Flash-EEPROM 5, and a logic circuit (logic) 8 as functional circuits. These functional circuits are isolated from each other by an isolated region 10 provided in the chip 1. Further, the isolated region 10 is in contact with the side surface of the chip 1 over the entire circumference.

  The logic circuit 8 is a circuit configured by a logic circuit like the processor 2, but means a circuit having a smaller circuit scale than the processor 2.

  Next explained is a semiconductor integrated circuit device according to the tenth embodiment of the invention. FIG. 26 is a sectional view of a semiconductor integrated circuit device according to the tenth embodiment of the present invention.

  The cross section shown in FIG. 26 is taken when the chip 1 is formed on a silicon wafer.

  As shown in FIG. 26, in the apparatus according to the tenth embodiment, the isolation region 10 is a P-type silicon substrate (P-SUB). The P-type silicon substrate 10 is, for example, a wafer itself. A plurality of large N-type wells (N-WELL) 22 are provided in the substrate 10. In the apparatus according to the second embodiment, four large wells 22-3 to 22-5 and 22-8 are provided. An SRAM 3, a DRAM 4, a Flash-EEPROM 5, and a logic circuit 8 are formed in each of the four large wells 22-3 to 22-5 and 22-8. The large wells 22-3 to 22-5 and 22-8 are each supplied with an optimum power supply potential for each functional circuit. In the semiconductor integrated circuit device according to the tenth embodiment, the high potential power supply VCC is in the well 22-3, the high potential power supply VDD4 is in the well 22-4, the high potential power supply VDD5 is in the well 22-5, and the well 22-8. Is supplied with a high potential power supply VDD8. The high potential power supply VCC is an external power supply supplied from the outside of the chip 1 together with a low potential power supply VSS (not shown), and the high potential power supplies VDD4, VDD5, and VDD8 respectively convert the external power supply potential VCC in the chip 1. This is the internal power generated.

  27 is a cross-sectional view of the well 22-8 shown in FIG.

  As shown in FIG. 27, a P-type well 23-8 and an N-type well 24-8 are formed in a large N-type well 22-8. A low potential power supply VSS (ground potential) is supplied to the P-type well 23-8. An NMOS 15 is formed in the P-type well 23-8. The N-type well 24-8 is supplied with the same high potential power supply VDD8 as the large N-type well 22-8. A PMOS 15 is formed in the N-type well 24-8. The N-type well 24-8 has a higher impurity concentration than the large N-type well 22-8. The N-type well 24-8 may be omitted.

  A P-type well 25-8 is formed in the large N-type well 22-8. A low potential power source VSS (ground potential) is supplied to the P-type well 25-8. An N-type well 26-8 and a P-type well 27-8 are formed in the P-type well 25-8. A high potential power supply VDD8 'is supplied to the N-type well 26-8. The power supply VDD8 ′ is an internal power supply generated by converting the voltage of the power supply VDD8 in the chip 1. A PMOS 16 is formed in the N-type well 26-8. The P-type well 27-8 is supplied with a low potential power supply VSS. An NMOS 16 is formed in the P-type well 27-8. The P-type well 27-8 has a higher impurity concentration than the P-type well 25-8. The P-type well 27-8 may not be provided in the same manner as the N-type well 24-8.

  The logic circuit 8 is basically composed of NMOS 15 and 16, and PMOS 15 and 16, but the logic circuit 8 may be composed only of NMOS 16 and PMOS 16 driven by the internal power supply VDD8 ′. In this case, the NMOS 15 and the PMOS 15 driven by the internal power supply VDD8 are preferably used in, for example, a voltage generation circuit that generates the internal power supply VDD8 ′ from the internal power supply VDD8. In addition, a plurality of P-type wells similar to the P-type well 25-6 may be formed in the large N-type well 22-8.

  In FIG. 27, reference symbol G indicates the gate of the MOSFET. Next explained is a semiconductor integrated circuit device according to the eleventh embodiment of the invention. FIG. 28 is a plan view when the semiconductor integrated circuit device according to the eleventh embodiment of the present invention is tested.

  As shown in FIG. 28, the pads 104 may be arranged in a staggered manner in three rows. Although the present invention has been described above with reference to the embodiment, the following modifications are possible. For example, as the functional circuit, seven types of processor 2, SRAM 3, DRAM 4, Flash-EEPROM 5, D / A converter 6, analog circuit 7, and logic circuit 8 are given, but other circuits may be used. In addition, functional circuits formed in one semiconductor chip can be combined in various ways.

  In addition, the external potential power supply VCC is supplied to the well in which the processor 2 or the SRAM 3 is formed, but may be supplied to a well in which another functional circuit is formed. Further, a well to which the external potential power supply VCC is supplied may be further formed, and a circuit for generating a potential to be supplied to another well may be formed in this well. Next, a twelfth embodiment of the invention is described.

  FIG. 29 is a plan view showing a basic configuration of a semiconductor integrated circuit device chip according to the first to eleventh embodiments of the present invention.

  As shown in FIG. 29, in the semiconductor integrated circuit device according to the present invention, for example, the functional circuits of the processor 2, SRAM 3, DRAM 4, and Flash-EEPROM 5 are formed in wells 22-2 to 22-5 that are separated from each other. . For this reason, even if a plurality of chips formed on the wafer are tested at the same time, they are not easily influenced by the function circuits included in the other chips. As described with reference to FIG. Therefore, a highly accurate test can be realized. Realizing highly accurate testing improves the yield of product inspection at the wafer stage.

  This twelfth embodiment is intended to further improve the yield of product inspection at the wafer stage when, for example, the power supply voltage is further lowered from the current 3.3V.

  As shown in FIG. 29, in the basic configuration of the semiconductor integrated circuit device according to the present invention, among the power supply systems VCC and VSS of the functional circuit, the power supply VSS is common to the substrate bias system.

  FIG. 30 is a schematic diagram schematically showing a state in which the chip shown in FIG. 29 is multi-tested. FIG. 30 shows only the power supply system.

  As shown in FIG. 30, there are chips 1 </ b> A to 1 </ b> D formed on one wafer 11. The test apparatus 300 includes VCC generators 301A to 301D corresponding to the chips 1A to 1D, respectively. The VCC generators 301A to 301D generate the power sources of the chips 1A to 1D, that is, the high potential VCC and the low potential VSS, respectively, from the potential difference between the high potential V in the test apparatus and the ground potential GND in the test apparatus. The generated high potential VCC and low potential VSS are supplied to the chips 1A to 1D, respectively. The high potential VCC is used as a high potential power source for operating the integrated circuit, and the low potential VSS is used as a low potential power source for operating the integrated circuit, and a bias potential of the P-type substrate.

  FIG. 31 is an equivalent circuit diagram of the state shown in FIG. In FIG. 31, the integrated circuits formed in the chips 1A to 1D are shown as loads RA to RD, respectively. As shown in FIG. 31, the state in which the chips 1 </ b> A to 1 </ b> D are being tested at the same time is a state in which current flows simultaneously through the loads RA to RD. The current that flows through each of the loads RA to RD flows into the low potential VSS. The low potentials VSS are connected to each other via the wafer 11. Therefore, the ripples of the power supplies (VCCA, VSSA) supplied to the chip 1A,..., The ripples of the power supplies (VCCD, VSSD) supplied to the chip 1D are harmonics of the ripples of the respective power supplies, and the loads RA˜ Applied to both ends of RD. This is shown in FIG.

  FIG. 32 is a schematic diagram schematically showing the ripple of the power supply of each chip shown in FIG.

  In FIG. 32, reference numeral 400A indicates the power supply ripple of chip 1A, reference numeral 400B indicates the power supply ripple of chip 1B, reference numeral 400C indicates the power supply ripple of chip 1C, and reference numeral 400D indicates the power supply ripple of chip 1D. ing. When the chips 1A to 1D are tested one by one, the power supply ripples of the chips 1A to 1D are as indicated by reference numerals 400A to 400D.

  However, when the chips 1A to 1D are tested at the same time, the ripples of the power sources indicated by reference numerals 400A to 400D overlap with each other, resulting in harmonics as indicated by the reference numeral 401. And the ripple of the power supply of each of the chips 1A to 1D becomes a harmonic as indicated by reference numerals 401A to 401D.

  If the chips 1A to 1D are tested simultaneously, it is assumed that the chip 1C is defective and a large current flows from the high potential VCCC of the chip 1C to the low potential VSSC. At this time, as indicated by reference numeral 400 </ b> C, the ripple of the power source of the chip 1 </ b> C increases and becomes a higher harmonic 401. For this reason, the ripple of the power supply of each chip indicated by reference numerals 401A to 401D is also increased.

  At present, with the miniaturization of transistors, the power supply voltage is decreased from 5 V to 3.3 V, from 3.3 V to 2.5 V, and so on. When a large ripple occurs in the power supply when the power supply voltage becomes extremely small, the power supply voltage falls below the guaranteed operation voltage of the transistor, as indicated by reference numeral 402, or as indicated by reference numeral 403, The breakdown voltage may be exceeded. When the power supply voltage becomes equal to or lower than the transistor operation guarantee voltage, other chips 1A, 1B, and 1D other than the defective chip 1C also malfunction, and are judged to be defective during the test. Further, when the power supply voltage becomes equal to or higher than the withstand voltage of the transistor, the transistors of the chips 1A, 1B, and 1D are destroyed. Such a problem becomes more serious as transistor miniaturization and lower power supply voltage progress.

  Furthermore, the number of chips to be tested simultaneously is a small number, such as 4, 8, 16, etc., but will increase to 32, 64 in the future, and ultimately all the chips formed on the wafer 11 Tested at the same time. In such a case, because of one defective chip, 31 chips or 63 chips, in the worst case, all of the chips formed on the wafer 11 are made defective.

  Under such circumstances, when a chip whose voltage reduction is promoted is subjected to a multi-test, the yield of product inspection at the wafer stage is expected to decrease in the future.

  In order to solve such a situation, the chips 1A to 1D may be tested one by one. However, if the chips 1A to 1D are tested one by one, the test time per wafer increases and the throughput deteriorates.

  FIG. 33 is a system configuration diagram showing the configuration of a test system according to the twelfth embodiment of the present invention.

  In order not to deteriorate the throughput and reduce the yield of product inspection, it is preferable to test a plurality of wafers 11A to 11D at a time using a persite type test system as shown in FIG. In the persite test system, one chip is tested for each of the wafers 11A to 11D.

  As described above, the semiconductor integrated circuit devices according to the first to eleventh embodiments of the present invention are tested by the persite type test system according to the twelfth embodiment, so that the throughput does not deteriorate and the product The inspection yield can be prevented from decreasing.

  Next, thirteenth and fourteenth embodiments of the present invention will be described.

  By the way, as shown in FIG. 33, the persite test system has a plurality of test stations 200A to 200D and is expensive. For this reason, the persite test system requires a large capital investment.

  Therefore, in the thirteenth embodiment, even if a plurality of chips formed on one wafer are tested simultaneously, the situation where the ripple of the power supply becomes a harmonic can be solved, and the yield of product inspection at the wafer stage can be eliminated. A semiconductor integrated circuit device capable of suppressing the decrease is provided, and the fourteenth embodiment aims to provide a test system thereof.

  FIG. 34 is a plan view showing the basic configuration of the semiconductor integrated circuit device chip according to the thirteenth embodiment.

  As shown in FIG. 34, in the semiconductor integrated circuit device according to the thirteenth embodiment, the power supply system (VCC, VSS) of the integrated circuit and the bias system (VSS-SUB) of the substrate are mutually connected on the chip 1 ′. It is separated. Specifically, in the chip 1 ′, the low potential VSS-SUB wiring 501 used for biasing the substrate is not connected to the low potential VSS wiring 502 used for the operation power supply of the integrated circuit. The wiring 501 is supplied with the low potential VSS-SUB through the pad 503, and the wiring 502 is supplied with the low potential VSS through a pad 504 different from the pad 503. Note that the wiring 505 is a wiring having a high potential VCC. A high potential VCC is supplied to the wiring 505 through the pad 506.

  FIG. 35 is a schematic diagram schematically showing a state in which the chip shown in FIG. 34 is multi-tested. FIG. 35 shows only the power supply system.

  As shown in FIG. 35, the test apparatus 300 'has VCC generators 301A to 301D corresponding to the chips 1'A to 1'D, respectively. The high potential VCC and the low potential VSS generated by the VCC generators 301A to 301D are supplied to the chips 1'A to 1'D, respectively. The high potential VCC is used as a high potential power source for operating the integrated circuit, and the low potential VSS is used as a low potential power source for operating the integrated circuit.

  Further, the test apparatus 300 'has bias power supply terminals 302A to 302D for applying a bias potential to the substrate corresponding to the chips 1'A to 1'D, respectively. In the test apparatus 300 ', since the wafer 11 is P-type silicon, the bias power supply terminals 302A to 302D are connected to the test apparatus internal ground point GND. If an integrated circuit device formed on an N-type silicon wafer is to be tested, the bias power supply terminals 302A to 302D are connected to a VCC generator (not shown) provided in the test device 300 '. In this case, the VCC generator is preferably provided in addition to the VCC generators 301A to 301D for the integrated circuit dedicated to the bias potential.

  FIG. 36 is an equivalent equivalent circuit diagram of the state shown in FIGS. 36 and 35. In FIG. 36, the integrated circuits formed in the chips 1'A to 1'D are shown as loads R'A to R'D, respectively.

  As shown in FIG. 36, the state in which the chips 1'A to 1'D are being tested at the same time is a state in which current flows simultaneously through the loads R'A to R'D. The currents flowing through the loads R′A to R′D flow into the low potentials VSSA to VSSD, respectively. These low potentials VSSA to VSSD are separated from the bias potential VSS-SUB of the wafer 11 through a PN junction (PNJ). Moreover, the bias potential VSS-SUB is supplied from the power supply system different from the low potentials VSSA to VSSD by the test apparatus 300 '. For this reason, the ripples of the power supplies (VCCA, VSSA) supplied to the chip 1′A,..., The ripples of the power supplies (VCCD, VSSD) supplied to the chip 1′D, respectively. Each is independent. This is shown in FIG.

  FIG. 37 is a schematic diagram schematically showing power supply ripple of each chip shown in FIG.

  In FIG. 37, reference numeral 400′A is a power supply ripple of chip 1′A, reference numeral 400′B is a power supply ripple of chip 1′B, reference numeral 400′C is a power supply ripple of chip 1′C, reference Reference numeral 400′D indicates a ripple of the power source of the chip 1′D. When the chips 1′A to 1′D are tested one by one, the power supply ripples of the chips 1′A to 1′D are as indicated by reference numerals 400′A to 400′D. .

  In addition, since the power sources (VCCA to VCCD, VSSA to VSSD) of the chips 1′A to 1′D are separated from the bias potential (VSS-SUB) of the wafer 11 by the PN junction, the chips 1′A to 1 Even if 'D is tested at the same time, the ripple of the power source of each of the chips 1'A to 1'D is unlikely to be a harmonic as shown in FIG. Therefore, as shown in FIG. 37, the ripple of the power source of each of the chips 1'A to 1'D is almost unchanged.

  Due to such advantages, when the power supply voltage drops from 5 V to 3.3 V, from 3.3 V to 2.5 V,..., For example, the chip 1′C has a defect and the power supply of the chip 1′C is large. Even if ripples occur, the power sources of the other chips 1'A, 1'B, and 1'D are hardly affected. Therefore, it is possible to suppress a situation in which an operation failure occurs in other chips 1A, 1B, and 1D other than the defective chip 1′C and a situation in which the transistors in the chips 1A, 1B, and 1D are destroyed. .

  FIG. 38 is a plan view showing a state in which the semiconductor integrated circuit device chip according to the thirteenth embodiment of the present invention is formed on the wafer 11.

  In the chip 1 ′ illustrated in FIG. 38, the VSS wiring 502 is formed in a mesh shape, and the VSS-SUB wiring 501 is formed in an annular shape along the outer periphery of the VSS wiring 502. The VCC wiring 505 is omitted. This is to prevent complication of the drawing.

  As shown in FIG. 38, a pad 503 for supplying a potential VSS-SUB, a pad 504 for supplying a low potential VSS, and a high potential VCC are supplied to each of the plurality of chips 1 ′. The pad 506 is formed. In the chip 1 ′, the VSS-SUB wiring 501 is separated from the VSS wiring 502.

  FIG. 39 is a plan view of a packaged semiconductor integrated circuit device chip according to the thirteenth embodiment of the present invention.

  When packaging the chip 1 ′ according to the thirteenth embodiment, as shown in FIG. 39, the substrate bias pad 503 and the integrated circuit operating power supply pad 504 are connected to the lead terminal 507, respectively. good. The lead terminal 507 is a VSS terminal. As a result, the potentials of the low potential power supply of the substrate and the integrated circuit become the low potential VSS, respectively, and the substrate is biased to the low potential VSS. The substrate is biased to the potential VSS, and the integrated circuit operates normally.

  Note that FIG. 39 is an example, and the pad 503 and the pad 504 may be connected to separate lead terminals, and the low potential VSS may be supplied from the separate lead terminals.

  FIG. 40 is a system configuration diagram showing the configuration of a test system according to the fourteenth embodiment of the present invention.

  As shown in FIG. 40, in the test system according to the fourteenth embodiment, a test apparatus 300 ′ is used, and four chips 1′A to 1′D formed on one wafer 11 are simultaneously tested. To do. This also eliminates the situation where the ripple of the power supply becomes a harmonic. Therefore, the test system shown in FIG. 40 can obtain the same test accuracy as the persite test system having the four test stations 200A to 200D shown in FIG. In addition, the number of test stations 200 can be reduced as compared to the persite type test system, and the capital investment can be reduced as compared with the persite type test system.

  Further, if the same capital investment as that of the persite type test system is made, for example, if the number of test stations is the same as that of the persite type test system, the number of chips that can be tested at one time will be increased. That is, the test system according to the fourteenth embodiment has a higher processing capacity per equipment investment than the test system according to the twelfth embodiment.

  As described above, in the thirteenth and fourteenth embodiments, even when a plurality of chips formed on a single wafer are tested at the same time, the situation in which the ripple of the power source becomes a harmonic can be solved, and at the wafer stage It is possible to provide a semiconductor integrated circuit device capable of suppressing a decrease in yield of product inspection and a test system thereof.

  Next, a fifteenth embodiment of the invention is described.

  In the fifteenth embodiment, the test apparatus 300 ′ described in the thirteenth and fourteenth embodiments is improved so as to more strongly suppress the occurrence of power supply ripple that occurs during multi-test.

  FIG. 41 is a configuration diagram showing a configuration of a test apparatus according to the fifteenth embodiment. In FIG. 41, only the power supply system is shown.

  As shown in FIG. 41, the test apparatus 300 ″ includes VCC generators 301 </ b> A to 301 </ b> D corresponding to a plurality of chips. The VCC generator 301A supplies a high potential VCCA to a chip 1'A (not shown) via a high potential power supply terminal 303A and a low potential VSSA via a low potential power supply terminal 304A. Similarly, the VCC generator 301B supplies a high potential VCCB via a high potential power supply terminal 303B and a low potential VSSB via a low potential power supply terminal 304B to a chip 1'B (not shown). The VCC generator 301D supplies a high potential VCCD via a high potential power supply terminal 303D and a low potential VSSD via a low potential power supply terminal 304D to a chip 1'D (not shown).

  The test apparatus 300 '' includes power supply voltage detection circuits 305A to 305D and cutoff switches 306A to 306D provided between the VCC generators 301A to 301D and the power supply terminals 303A to 303D and 304A to 304D. Yes. Furthermore, it has a switch driver 309 that drives a detection voltage determination device 307, a CPU 308, and cutoff switches 306A to 306D that determine whether the detection voltages detected by the detection circuits 305A to 305D are within the normal range. .

  Next, the operation of the test apparatus 300 '' will be described.

  The detection circuits 305A to 305D detect fluctuations in the power supply voltage of the chips 1'A to 1'D when the chips 1'A to 1'D operate. The detection voltages detected by the detection circuits 305 </ b> A to 305 </ b> D are sent to the detection voltage determination device 307. The detection voltage determination device 307 determines whether or not the voltage fluctuation of the power supply voltage of the chips 1'A to 1'D is within a normal range. When it is determined that there is a voltage fluctuation outside the normal range, the determination device 307 outputs a signal notifying the CPU 308 of a chip having a voltage fluctuation outside the normal range. Here, it is assumed that the voltage fluctuation outside the normal range occurs in the chip 1'C. At this time, the determination device 307 outputs to the CPU 308 a signal notifying that the chip 1'C has a voltage fluctuation outside the normal range. The CPU 308 outputs a command (signal) for shutting off the power supply of the chip 1 ′ C to the switch driver 309. The switch driver 309 drives the cut-off switch 306C to cut off the power supply system that supplies the power supply voltage to the chip 1'C. The driven cutoff switch 306C disconnects the VCC generator 301C from the power supply terminals 303C and 304C. As a result, the power supply voltage is not supplied to the chip 1'C that has undergone voltage fluctuation outside the normal range, and its operation is stopped.

  According to such a test apparatus 300 ', for example, as shown in FIG. 37, when a large power supply ripple occurs in the simultaneously tested chip 1'C, the operation of the chip 1'C can be stopped. For this reason, the ripples of the power supplies of the other chips 1'A, 1'B, 1'D are further reduced.

  The test apparatus 300 ″ that can further reduce the ripple of the power source is a test that requires delicateness among test items of a semiconductor integrated circuit device, such as IDDQ (measurement of static current consumption during a function test). In this case, the accuracy of the test can be further increased by performing the above-described operation.

  Next, the sixteenth, seventeenth, eighteenth and nineteenth embodiments of the present invention will be described.

  The chip according to the thirteenth embodiment described above is a semiconductor integrated circuit device (system-on-silicon technology) in which a desired semiconductor device system constructed by a combination of a processor, SRAM, DRAM, Flash-EEPROM and the like is integrated on one chip. ). However, the chip according to the thirteenth embodiment, that is, a chip capable of improving the test accuracy in the multi-test, is not only a system-on-silicon technology, but also a processor chip, an SRAM chip, a DRAM chip, a Flash-EEPROM chip, or the like. Can also be used for functional products. These single-function products are coupled to each other on a circuit board to construct a desired semiconductor device system.

  Hereinafter, representative examples in which the chip according to the thirteenth embodiment is applied to a single-function semiconductor integrated circuit device include a processor (sixteenth embodiment), a DRAM (seventeenth embodiment), a NAND flash- The description will be made in the order of the EEPROM (eighteenth embodiment) and the D / A converter (19th embodiment). Of course, the present invention can also be applied to single-function semiconductor integrated circuit devices other than these, such as SRAM, analog products, and logic products.

  42A and 42B are views showing a processor according to a sixteenth embodiment of the present invention. FIG. 42A is a plan view, and FIG. 42B is a sectional view taken along line 42B-42B in FIG. 42A and 42B, a circuit block constituting the processor is divided into an internal voltage generator 51-2 for generating an internal voltage, a logic circuit 52-2 for constituting an arithmetic circuit, a register circuit, and the like. Signals processed inside the chip are output to the outside, and signals are roughly divided into three blocks of an I / O circuit 53-2 that inputs signals from the outside of the chip into the chip.

  As shown in FIGS. 42A and 42B, a large N-type well 22-2 is formed in the P-type silicon substrate 10. Three circuit blocks constituting the processor, that is, the internal voltage generator 51-2, the logic circuit 52-2, and the I / O circuit 53-2 are arranged in the large well 22-2.

  The N-type well 22-2 includes high-concentration P + type wells 23A-2 and 23B-2, high-concentration N + type wells 24A-2 and 24B-2 having a higher concentration than the N-type well 22-2, and P-type. Well 25-2 is formed. The P-type well 25-2 is further formed with a high-concentration N + type well 26-2 and a high-concentration P + type well 27-2 having a higher concentration than the P-type well 25-2.

  An external high potential power supply VCC is supplied as a bias potential to the N-type well 22-2. The P-type well 25-2 is supplied with an external low potential power supply VSS as a bias potential.

  The internal voltage generator 51-2 includes an NMOS (not shown) formed in the P + type well 23A-2 and a PMOS (not shown) formed in the N + type well 24A-2. A power supply VCC is supplied to the N + type well 24A-2 as a PMOS back gate bias and a PMOS source potential. The P + type well 23A-2 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The internal voltage generator 51-2 is operated by a potential difference (VCC-VSS) and generates a predetermined internal potential VDD '.

  The logic circuit 52-2 includes an NMOS (not shown) formed in the P + type well 27-2 and a PMOS (not shown) formed in the N + type well 26-2. The N + type well 26-2 is supplied with an internal potential VDD 'as a PMOS back gate bias and a PMOS source potential. The P + type well 27-2 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The logic circuit 52-2 is operated by a potential difference (VDD′−VSS) and performs predetermined arithmetic processing and the like.

  The I / O circuit 53-2 includes an NMOS (not shown) formed in the P + type well 23B-2 and a PMOS (not shown) formed in the N + type well 24B-2. A power supply VCC is supplied to the N + type well 24B-2 as a PMOS back gate bias and a PMOS source potential. The P + type well 23B-2 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The I / O circuit 53-2 is operated by a potential difference (VCC-VSS), and performs predetermined signal output and signal input.

  In particular, as shown in FIG. 42A, the power supply VCC is supplied to the VCC wiring 505 provided inside the chip via the pad 506, and the power supply VSS is provided inside the chip via the pad 504. Is supplied to the VSS wiring 502. A VSS-SUB wiring 501 for applying a substrate bias potential to the P-type substrate 10 is provided inside the chip separately from the VSS wiring 502. The VSS-SUB wiring 501 is supplied with a power supply VSS through a pad 503, particularly during actual use, as shown in FIG. 42B, and is identical in potential during a test in a wafer state. A power supply VSS-SUB for a substrate that is different from the power supply VSS in terms of level is supplied.

  Similar to the chips described in the thirteenth and fourteenth embodiments, such a processor has a substrate bias power supply system and an integrated circuit power supply system separately in the chip and is formed on the wafer. Even if a plurality of chips are tested simultaneously (multi-test), the power supply ripple of each chip can be reduced. Therefore, even if a multi-test is performed, a highly accurate test can be performed, and the yield in product inspection at the wafer stage can be improved.

  43A and 43B are views showing a DRAM according to a seventeenth embodiment of the present invention. FIG. 43A is a plan view, and FIG. 43B is a sectional view taken along line 43B-43B in FIG. 43 (A) and 43 (B), a circuit block constituting the DRAM includes an internal voltage generator 51-4 for generating an internal voltage, a memory cell 54-4 for storing information, and writing data into the memory cell. In addition, the memory peripheral circuit 55-4 and the I / O circuit 53-4 that are read from the memory cell are roughly divided into four blocks.

  As shown in FIGS. 43A and 43B, a large N-type well 22-4 is formed in the P-type silicon substrate 10. The four circuit blocks constituting the DRAM, that is, the internal voltage generator 51-4, the memory cell 54-4, the peripheral circuit 55-4, and the I / O circuit 53-4 are arranged in the large well 22-4. The

  In the N-type well 22-4, high-concentration P + type wells 23A-4 and 23B-4, high-concentration N + type wells 24A-4 and 24B-4, and P-type wells 25A-4 and 25B-4 are formed. . Further, a high concentration N + type well 26B-4 and a high concentration P + type well 27B-4 are further formed in the P type well 25B-4.

  As in the sixteenth embodiment, the N-type well 22-4 is supplied with the external high potential power supply VCC as a bias potential. The P-type well 25B-2 is supplied with an external low potential power supply VSS as a bias potential.

  The internal voltage generator 51-4 includes an NMOS (not shown) formed in the P + type well 23A-4 and a PMOS (not shown) formed in the N + type well 24A-4. A power supply VCC is supplied to the N + type well 24A-4 as a PMOS back gate bias and a PMOS source potential. The P + type well 23A-4 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The internal voltage generator 51-4 is operated by a potential difference (VCC-VSS) and generates an internal potential VDD 'having a positive value and an internal potential VBB having a negative value.

  In a current DRAM, a potential VPP for boosting a word line (not shown), a plate potential VPL applied to a plate electrode of a capacitor, and a bit line (not shown) are precharged before reading data. Although there are internal potentials such as a precharge potential VBL used sometimes, this is omitted in the seventeenth embodiment. Similarly, peripheral circuits using these internal potentials VPP, VPL, VBL are also omitted.

  The memory cell 54-4 is formed in the P-type well 25A-4. The memory cell 54-4 is a dynamic type. The dynamic memory cell 54-4 has a capacitor (not shown) for storing information as a charge, a source connected to the capacitor, a drain connected to a bit line (not shown), and a word line (not shown). ) And an NMOS (transfer transistor, not shown) having a gate connected thereto. An internal negative potential VBB is supplied to the P well 25A-4 as a back gate bias of an NMOS (transfer transistor).

  The peripheral circuit 55-5 includes an NMOS (not shown) formed in the P + type well 27B-4 and a PMOS (not shown) formed in the N + type well 26B-4. The N + type well 26B-4 is supplied with an internal potential VDD 'as a PMOS back gate bias and a PMOS source potential. The P + type well 27B-4 is supplied with an external back potential bias VSS as an NMOS back gate bias and an NMOS source potential. The peripheral circuit 55-4 is operated by a potential difference (VDD'-VSS).

  The I / O circuit 53-4 includes an NMOS (not shown) formed in the P + type well 23B-4 and a PMOS (not shown) formed in the N + type well 24B-4. A power supply VCC is supplied to the N + type well 24B-4 as a PMOS back gate bias and a PMOS source potential. The P + type well 23B-4 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The I / O circuit 53-4 is operated by a potential difference (VCC-VSS).

  Similarly to the sixteenth embodiment, as shown in FIG. 43A in particular, the VSS wiring 502 for supplying the power supply voltage to the DRAM formed in the N-type well 22-4 is provided on the P-type substrate 10. , Separated from the VSS-SUB wiring 501 for applying a bias potential.

  Therefore, as shown in FIG. 43B in particular, also in the DRAM according to the seventeenth embodiment, the potential VSS is supplied to the VSS wiring 502 and the potential to the VSS-SUB wiring 501 during the test in the wafer state. VSS-SUB can be supplied.

  In the seventeenth embodiment, as in the sixteenth embodiment, the DRAM power supply VSS formed in the N-type well 22-4 and the bias potential VSS of the P-type substrate 10 during the test in the wafer state. Since SUB can be provided separately, even if a plurality of chips formed on the wafer are tested at the same time, the power supply ripple of each chip can be reduced. Therefore, even if a multi-test is performed, a highly accurate test can be performed, and the yield in product inspection at the wafer stage can be improved.

  44A and 44B are views showing a Flash-EEPROM according to an eighteenth embodiment of the present invention. FIG. 44A is a plan view, and FIG. 44B is a cross-sectional view taken along line 44B-44B in FIG. is there. 44 (A) and 44 (B), a circuit block constituting the Flash-EEPROM includes an internal voltage generator 51-5 for generating an internal voltage, a memory cell 54-5 for storing information, and writing data into the memory cell. , And a memory peripheral circuit 55-5 to be read from the memory cell, and an I / O circuit 53-5.

  As shown in FIGS. 44A and 44B, the P-type silicon substrate 10 has a large N-type well 22-5. The four circuit blocks constituting the EEPROM, that is, the internal voltage generator 51-5, the memory cell 54-5, the peripheral circuit 55-5, and the I / O circuit 53-5 are arranged in the large well 22-5. The

  P-type wells 25A-5, 25B-5, 25C-5, and 25D-5 are formed in the N-type well 22-5. Among these P-type wells, a high-concentration N + type well 26B-5 and a high-concentration P + type well 27B-5 are formed in the P-type well 25B-5. Similarly, a high concentration N + type well 26C-5 and a high concentration P + type well 27C-5 are formed in the P type well 25C-5, and a high concentration N + type well 26D-5 is formed in the P type well 25D-5. A high concentration P + type well 27D-5 is formed.

  The bias potential of the N-type well 22-5 can be switched by three basic operation modes of the Flash-EEPROM. First, in the data write mode (WRITE), the N-type well 22-5 is biased to the external high potential power supply VCC or the internal power supply VDD 'as shown. In the data read mode (READ), the N-type well 22-5 is biased to the external high-potential power supply VCC or the internal power supply VDD 'as shown, as in the data write mode (WRITE). In the data erase mode (ERASE), the N-type well 22-5 is set to the potential VEE which is a positive potential higher than the power supply VCC.

  The P-type wells 25B-5, 25C-5, and 25D-5 are each biased to the external low potential power supply VSS.

  The internal voltage generator 51-5 includes an NMOS (not shown) formed in the P + type well 27B-5 and a PMOS (not shown) formed in the N + type well 26B-5. A power supply VCC is supplied to the N + type well 26B-5 as a PMOS back gate bias and a PMOS source potential. The P + type well 27B-5 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The internal voltage generator 51-5 is operated by a potential difference (VCC-VSS), and has an internal potential VDD ′ having a positive value, an internal potential VEE having a positive value higher than the power supply VCC, and an internal potential having a negative value. VBB is generated.

  In the current Flash-EEPROM, in particular, the NAND type, when writing data, a potential VPP applied to a word line (not shown) selected for writing, a potential VM applied to another word line not selected for writing, etc. Although there is an internal potential or a potential applied from the outside, this is omitted in the eighteenth embodiment. Similarly, the peripheral circuits using these potentials VPP and VM are also omitted.

  The memory cell 54-5 is formed in the P-type well 25A-5. The memory cell 54-5 is a nonvolatile type. The nonvolatile memory cell 54-5 is constituted by a variable threshold transistor that stores information by replacing it with a threshold voltage of the transistor. The variable threshold type transistor has a floating gate in the gate insulating film, and changes the threshold voltage according to the amount of electrons accumulated therein. Further, the memory cell 54-5 is a so-called unit cell in which 8 or 16 threshold variable transistors are connected in series, and is a NAND type. The unit cell has a source connected to a source line (not shown) and a drain connected to a bit line (not shown).

  The bias potential of the P-type well 25A-5 is switched by three basic operation modes of the Flash-EEPROM. First, in the data write mode (WRITE), the bias potential of the P-type well 25A-5 is set to the negative internal potential VBB. In the data read mode (READ), the power supply VSS is used. In the data erasing mode (ERASE), the potential is VEE.

  The peripheral circuit 55-5 includes an NMOS (not shown) formed in the P + type well 27C-5 and a PMOS (not shown) formed in the N + type well 26C-5. The N + type well 26C-5 is supplied with the internal potential VDD 'as the PMOS back gate bias and the PMOS source potential. The P + type well 27C-5 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The peripheral circuit 55-5 is operated by a potential difference (VDD'-VSS).

  The I / O circuit 53-5 includes an NMOS (not shown) formed in the P + type well 27D-5 and a PMOS (not shown) formed in the N + type well 26D-5. A power supply VCC is supplied to the N + type well 26D-5 as a PMOS back gate bias and a PMOS source potential. The P + type well 27B-5 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The I / O circuit 53-5 is operated by a potential difference (VCC-VSS).

  Similarly to the sixteenth and seventeenth embodiments, as shown in FIG. 44A in particular, the VSS wiring 502 for supplying the power supply voltage to the Flash-EEPROM formed in the N-type well 22-5 is This is separated from the VSS-SUB wiring 501 for applying a bias potential to the P-type substrate 10.

  In the Flash-EEPROM according to the eighteenth embodiment, as in the sixteenth and seventeenth embodiments, as shown in FIG. 44B, the VSS wiring 502 is connected during the test in the wafer state. The potential VSS can be supplied, and the potential VSS-SUB can be supplied to the VSS-SUB wiring 501.

  Therefore, since the power supply VSS of the Flash-EEPROM and the bias potential VSS-SUB of the P-type substrate 10 can be separately applied during the test in the wafer state, a highly accurate test can be performed even if the multi-test is performed. It is possible to improve the yield in product inspection at the wafer stage.

  45 is a view showing a D / A converter according to a nineteenth embodiment of the present invention. FIG. 45 (A) is a plan view, and FIG. 45 (B) is a sectional view taken along line 45B-45B in FIG. is there. 45A and 45B, the circuit blocks constituting the D / A converter are divided into an internal voltage generator 51-2, an analog circuit 56-6, a digital circuit 57-6, and an I / O circuit 53-6 is roughly divided into three blocks.

  As shown in FIGS. 45A and 45B, the P-type silicon substrate 10 has a large N-type well 22-6. The three circuit blocks constituting the D / A converter, that is, the internal voltage generator 51-6, the analog circuit 56-6, the digital circuit 57-6, and the I / O circuit 53-6 are each of the large well 22-6. Placed in.

  In the N type well 22-6, high concentration P + type wells 23A-6 and 23B-6, high concentration N + type wells 24A-6 and 24B-6, and P type wells 25A-6 and 25B-6 are formed. . In the P-type well 25A-6, a high concentration N + type well 26A-6 and a high concentration P + type well 27A-6 are further formed. In the P-type well 25B-6, a high concentration N + type well 26B-6 and a high concentration P + type well 27B-6 are formed.

  An external high potential power supply VCC is supplied as a bias potential to the N-type well 22-6. The P-type wells 25A-6 and 25B-6 are supplied with an external low potential power supply VSS as a bias potential.

  The internal voltage generator 51-6 includes an NMOS (not shown) formed in the P + type well 23A-6 and a PMOS (not shown) formed in the N + type well 24A-6. A power supply VCC is supplied to the N + type well 24A-6 as a PMOS back gate bias and a PMOS source potential. The P + type well 23A-6 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The internal voltage generator 51-6 is operated by a potential difference (VCC-VSS), and generates an internal potential VDD ′ for an analog circuit and an internal potential VDD ″ for a digital circuit.

  The analog circuit 56-6 includes an NMOS (not shown) formed in the P + type well 27A-6 and a PMOS (not shown) formed in the N + type well 26A-6. The N + type well 26A-6 is supplied with an internal potential VDD 'as a PMOS back gate bias and a PMOS source potential. The P + type well 27A-6 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The analog circuit 56-6 is operated by a potential difference (VDD′−VSS).

  The digital circuit 57-6 includes an NMOS (not shown) formed in the P + type well 27B-6 and a PMOS (not shown) formed in the N + type well 26B-6. The N + type well 26B-6 is supplied with the internal potential VDD ″ as the PMOS back gate bias and the PMOS source potential. The P + type well 27B-6 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The digital circuit 57-6 is operated by a potential difference (VDD ″ −VSS).

  The I / O circuit 53-6 includes an NMOS (not shown) formed in the P + type well 23B-6 and a PMOS (not shown) formed in the N + type well 24B-6. A power supply VCC is supplied to the N + type well 24B-6 as a PMOS back gate bias and a PMOS source potential. The P + type well 23B-6 is supplied with an external low potential power source VSS as an NMOS back gate bias and an NMOS source potential. The I / O circuit 53-6 is operated by a potential difference (VCC-VSS), and performs predetermined signal output and signal input.

  In particular, as shown in FIG. 45A, as in the sixteenth to eighteenth embodiments, the VSS wiring 502 for supplying the power supply voltage to the D / A converter formed in the N-type well 22-6 is as follows. , Separated from the VSS-SUB wiring 501 for applying a bias potential to the P-type substrate 10.

  In the D / A converter according to the nineteenth embodiment, as shown in FIG. 45 (B), in the same way as the sixteenth to eighteenth embodiments, during the test in the wafer state, the VSS wiring 502 Can be supplied with the potential VSS, and the VSS-SUB wiring 501 can be supplied with the potential VSS-SUB.

  Therefore, since the power supply VSS of the D / A converter and the bias potential VSS-SUB of the P-type substrate 10 can be given separately during the test in the wafer state, a highly accurate test can be performed even if a multi-test is performed. And the yield in product inspection at the wafer stage can be improved.

  Next, a twentieth embodiment of the invention is described.

  The twentieth embodiment is a semiconductor integrated circuit device that can reduce the ripple of the power source described above and can perform a highly accurate test even when a plurality of chips formed on one wafer are simultaneously tested. It is something to be offered.

  Among the circuit blocks constituting the integrated circuit, the circuit block that generates the ripple in the power supply most is an I / O circuit. Among the I / O circuits, in particular, the output circuit drives an external terminal (for example, a lead terminal shown in FIG. 39) of the semiconductor integrated circuit device almost directly. In other words, the output circuit causes a current to flow from the VCC wiring (for example, the VCC wiring 505 shown in FIG. 42A) wired in the chip to the external terminal, and charges the external terminal. Alternatively, a current is supplied from the external terminal to the VSS wiring (for example, the VSS wiring 502 shown in FIG. 42A) wired in the chip, and the external terminal is discharged. In particular, the capacity of the external terminal is larger than the capacity of the internal wiring of the integrated circuit. For this reason, the decrease in the potential of the VCC wiring or the increase in the potential of the VSS wiring that occurs when the output circuit drives the external terminal is considerably larger than when the internal circuit is driven. As a result, for example, power supply ripples appearing at the VCC pad 506 and the VSS pad 504 shown in FIG.

  In the twentieth embodiment, attention is paid to this situation, and an object is to further reduce the ripple of the power source appearing on the VCC pad 506 and the VSS pad 504.

  Hereinafter, the twentieth embodiment will be described taking a DRAM as an example.

  46A and 46B are views showing a DRAM according to the twentieth embodiment of the present invention. FIG. 46A is a plan view, and FIG. 46B is a cross-sectional view taken along line 46B-46B in FIG. 46A and 46B, the same parts as those in FIGS. 42A and 42B are denoted by the same reference numerals, and only different parts will be described.

  As shown in FIGS. 46A and 46B, the part of the DRAM according to the twentieth embodiment that is particularly different from the DRAM according to the seventeenth embodiment is an I / O circuit 53'-4. The I / O circuit 53'-4 is formed in the P-type well 25C-4 formed in the N-type well 22-4. The bias potential of the P-type well 25C-4 is supplied not from the VSS wiring 502 but from another power supply wiring. In the DRAM shown in FIGS. 46A and 46B, an example in which the power supply wiring is supplied from the wiring 551 having the negative internal potential VBB is shown. Negative internal potential VBB is generated by internal potential generation circuit 51-4 and applied to P-type well 25C-4 via wiring 551. This may be VSS, but at that time, in addition to the VSS wiring 502 and the VSS-SUB wiring 501, another VSS-WELL wiring is provided in the chip. During the test, the VSS wiring 502 and the VSS-SUB wiring 501 are provided. , It is desirable to apply different VSS level potentials to the VSS-WELL wirings.

  In the P-type well 25C-4, a high concentration N + type well 26C-4 and a high concentration P + type well 27C-4 are formed.

  The I / O circuit 53'-4 includes an NMOS (not shown) formed in the P + type well 27C-4 and a PMOS (not shown) formed in the N + type well 26C-4. A positive internal potential VCC is supplied to the N + type well 26C-4 as a PMOS back gate bias and a PMOS source potential. The positive internal potential VDD ″ is generated by the internal potential generation circuit 51-4, and is given to the N + type well 26C-4 via the wiring 552 different from the VCC wiring 505. The P + type well 27C-4 is supplied with a negative internal potential VBB as an NMOS back gate bias and an NMOS source potential. The I / O circuit 53-4 is operated by a potential difference (VDD ″ −VBB).

  In such a DRAM, when the I / O circuit 53'-4, particularly the output circuit, charges an external terminal (not shown), a current flows from the wiring 552 different from the VCC wiring 505 toward the external terminal. Further, when discharging the external terminal, a current is supplied to the wiring 551 different from the VSS wiring 502. As a result, the charging / discharging current does not flow directly from the VCC wiring 505 or directly into the VSS wiring 502. Therefore, the situation in which the output voltage of the I / O circuit 53'-4 drives the external terminal and the potential of the VCC wiring decreases or the potential of the VSS wiring increases is improved, and the VCC pad 506 is improved. , Power supply ripple appearing at the VSS pad 504 can be further reduced.

  In this way, the minute power supply ripple generated by the operation of the chip is further reduced, so that when testing multiple chips formed on a single wafer at the same time, a more accurate test can be performed. It can be carried out.

  Note that the I / O circuit included in the semiconductor integrated circuit device according to the twentieth embodiment is not only a DRAM product but also a variety of currently known semiconductors such as a processor, a Flash-EEPROM, a D / A converter, and an SRAM. Of course, it can be used for integrated circuit device products.

  Next, a twenty-first embodiment will be described.

  The twenty-first embodiment is an example in which the semiconductor integrated circuit device according to the twentieth embodiment is applied to a semiconductor integrated circuit device using system-on-silicon technology.

  FIG. 47 is a plan view of a semiconductor integrated circuit device according to the twenty-first embodiment of the present invention. In FIG. 47, the same parts as those in FIGS. 42A, 42B to 46A, 46B are denoted by the same reference numerals, and only different parts will be described.

As shown in FIG. 47, the semiconductor integrated circuit device according to the twenty-first embodiment is constructed by the combination of the processor, DRAM, Flash-EEPROM, and D / A converter described in the sixteenth to nineteenth embodiments. A semiconductor device system is integrated on one substrate 10. (Hereinafter referred to as a one-chip mixed semiconductor integrated circuit device.)
Further, the I / O circuit described in the twentieth embodiment is used as an I / O circuit of a one-chip mixed type semiconductor integrated circuit device.

  The I / O circuit 53'-2 is arranged in the processor block among the four functional blocks. A P-type well 25A-2 is formed in the N-type well 22-2 where the processor is formed, and an I / O circuit 53'-2 is formed in the P-type well 25A-2. The bias potential of the P-type well 25A-2 is supplied not from the VSS wiring 502 but from another power supply wiring. In the semiconductor integrated circuit device shown in FIG. 47, an example is shown in which another power supply wiring is supplied from a wiring 551 having a negative internal potential VBB. Negative internal potential VBB is generated by internal potential generation circuit 51-2 and applied to P-type well 25A-2 via wiring 551.

  The I / O circuit 53′-2 is similar to the I / O circuit 53′-4 described with reference to FIGS. 46A and 46B, and the detailed configuration thereof is illustrated in FIGS. ).

  In such a one-chip mixed semiconductor integrated circuit device, as in the twentieth embodiment, when the I / O circuit 53′-2, particularly the output circuit, charges an external terminal (not shown), the VCC wiring A current is supplied to the external terminal from a wiring 552 different from 505. Further, when discharging the external terminal, a current is supplied to the wiring 551 different from the VSS wiring 502. Therefore, the minute power supply ripple generated by the operation of the chip can be further reduced, and when a plurality of chips formed on a single wafer are tested simultaneously, a more accurate test can be performed. .

  By the way, as described above, in the test of the one-chip mixed type semiconductor integrated circuit device, there is a test for each functional block in addition to the test for the entire chip. Improvements in test accuracy should be achieved not only in tests on the entire chip but also in individual tests on each functional block.

  In a one-chip mixed type semiconductor integrated circuit device, functional blocks may be coupled to each other via an interface circuit (I / F circuit) formed inside the chip. The I / F circuits in this case are the I / O circuits 53-2, 53-4, 53-5, 53-6 shown in FIGS. 42 (A), (B) to 45 (A), (B). The same configuration as that described above may be used. However, it is expected that the influence of power supply ripple generated by each functional block is not small.

  In view of this situation, the I / F circuits 58′-2, 58′-4, 58′-5, and 58′-6 included in the one-chip mixed semiconductor integrated circuit device shown in FIG. The / O circuits 53′-2 and 53′-4 are separated from the VCC wiring 505 and the VSS wiring 502 in the same manner. By doing so, the ripple of the power generated by each functional block can be reduced.

  Therefore, it is possible to further reduce the ripple of the power supply generated by the operation of each function block. When testing each function block of multiple chips formed on one wafer, each function block Highly accurate test can be performed.

  Next, a twenty-second embodiment of the present invention is described.

  The twenty-second embodiment relates to a semiconductor integrated circuit device including an I / O circuit that can cope with several different levels of the power supply voltage VCC.

  The power supply voltage VCC of the current semiconductor product includes a product of 3.3V, mainly a highly integrated memory such as 64MDRAM, in addition to a product of 5V.

  In a semiconductor device system constructed by combining these semiconductor products, naturally, products having different power supply voltage levels are mixed on one circuit board. In a system constructed by mixing products with different power supply voltage levels, an interface circuit is mounted to connect the products. Products with different power supply voltage levels are coupled to each other via an interface circuit on the circuit board.

  However, in such a system, since the interface circuit is mounted, (1) it is difficult to reduce the size of the circuit board, and (2) signal (data) is exchanged via the interface circuit, so that signal delay is caused. (3) Since the interface circuit is purchased, the price of the system itself is increased.

  In order to solve such a situation, a technique for incorporating an interface function into a chip is now becoming mainstream. Briefly, the operating voltage of the I / O circuit is switched from 5 V (VCCA [5 V] −VSS [0 V]) to the operating voltage of the I / O circuit (VCCB [3.3 V] −VSS [0 V]). End up. In such an I / O circuit, when the operating voltage of the I / O circuit is 5V, the output amplitude is about 5V, and when the operating voltage is 3.3V, the output amplitude is about 3.3V.

  In a semiconductor product equipped with such an I / O circuit, the output amplitude of the I / O circuit is 5 V or 3.3 V, so that any of the products with a power supply voltage of 5 V and 3.3 V In addition, they can be coupled without an interface circuit.

  However, in such products, the I / O circuit operating voltage is 5V and the I / O circuit operating voltage is 3.3V. is there. The subtle changes in the input / output characteristics are in the negligible range at the time of interfacing between 5V and 3.3V, but will not be negligible in the future when interfacing between 3.3V and 2.5V. ,It is expected to be. This is because the operating voltage margin of the semiconductor integrated circuit device becomes severe as described above when the power supply voltage is lower than the current level.

  Furthermore, the data transfer speed in the system is expected to be much higher than the current situation. If the data transfer speed is improved, the specifications of the input / output characteristics will become stricter.

  Therefore, in the twenty-second embodiment, in a semiconductor integrated circuit device including an I / O circuit that can handle several different levels of the power supply voltage VCC, the power supply voltage is maintained without deteriorating the output characteristics of the I / O circuit. Provided is a semiconductor integrated circuit device which can be made substantially constant for each level of VCC.

  FIG. 48 is a diagram schematically showing a system configured using a semiconductor integrated circuit device according to the twenty-second embodiment of the present invention. FIG. 48 (A) shows a combination of products having the same power supply voltage level. FIG. 5B is a diagram illustrating a system in which products having different power supply voltage levels are combined.

  As shown in FIG. 48A, there is a processor 508A and a DRAM 508B which is handled as a memory by the processor 508A. The power supply voltages of the processor 508A and the DRAM 508B are 3.3V (VCC = 3.3V, VSS = 0V), respectively.

  An I / O circuit 53-4 and an internal circuit 59B are formed on the chip of the DRAM 508B. The internal circuit 59B includes, for example, the internal potential generation circuit 51-4, the memory cell 54-4, the peripheral circuit 55-5 and the like shown in FIGS. 43 (A) and (B). High potential VCC is applied to I / O circuit 53-4 and internal circuit 59B through VCC wiring 505, respectively.

  An I / O circuit 53 ″ according to the twenty-second embodiment and an internal circuit 59A are formed on the chip of the processor 508A. The internal circuit 59A includes, for example, the internal potential generation circuit 51-2, the logic circuit 52-2, etc. shown in FIGS. 42 (A) and (B). The internal circuit 59A is supplied with the high potential VCC through the VCC wiring 505A. The high potential VCC is applied to the I / O circuit 53 ″ through a VCC wiring 505B different from the VCC wiring 505A. VCC wiring 505A is connected to external power supply terminal 570, and VCC wiring 505B is connected to external power supply terminal 571 different from external power supply terminal 570.

  As shown in FIG. 48B, when the power supply voltage of the DRAM 508B is 2.5 V (VCCB = 2.5 V, VSS = 0 V), the I / O circuit 53 ″ of the processor 508A has a high potential VCCB. (2.5 V) is applied via a VCC wiring 505B different from the VCC wiring 505A. Note that a high potential VCCA (3.3 V) is applied to the internal circuit 59A through the VCC wiring 505A.

  Next, a specific structure and circuit of the I / O circuit 53 ″ will be described.

  49A and 49B are views showing a semiconductor integrated circuit device according to a twenty-second embodiment of the present invention. FIG. 49A is a plan view, and FIG. 49B is a sectional view taken along line 49B-49B in FIG. It is. Note that FIGS. 49A and 49B show only the vicinity of the I / O circuit 53 ″.

  As shown in FIGS. 49A and 49B, a large N-type well 22 is formed in the P-type silicon substrate 10. An I / O circuit 53 ″ and internal circuits (not shown) are each disposed in this large well 22.

  A P-type well 25 is formed in the N-type well 22. In the P-type well 25, a high concentration N + type well 26 and a high concentration P + type well 27 are formed.

  The N-type well 22 is supplied with an external high potential power supply VCCA as a bias potential. The P-type well 25 is supplied with an external low potential power supply VSS as a bias potential.

  The I / O circuit 53 ″ includes an NMOS (not shown) formed in the P + type well 27 and a PMOS (not shown) formed in the N + type well 26. The N + type well 26 is supplied with a potential Vbp as a PMOS back gate bias, and the P + type well 27 is supplied with a potential Vbn as an NMOS back gate bias. The I / O circuit 53 ″ is operated by a potential difference (VCCB−VSS).

  The values of the potentials Vbp and Vbn change depending on whether the operating voltage (VCCB-VSS, hereinafter referred to as interface voltage) of the I / O circuit 53 ″ is 3.3V or 2.5V. By changing the potentials Vbp and Vbn according to the level of the interface voltage of the I / O circuit 53 ″, the circuit threshold voltage of the I / O circuit 53 ″ is changed to when the interface voltage is 3.3V. And can be changed at 2.5V. In this way, by changing the circuit threshold voltage of the I / O circuit 53 ″ in accordance with the level of the interface voltage, a subtle change in input / output characteristics can be further reduced.

  For example, assuming that the circuit threshold voltage when the interface voltage is 3.3 V is “Vth = 1.0 V”, the circuit threshold voltage when the interface voltage is 2.5 V is lower than “Vth = 1.0 V”. make low. For example, “Vth = 0.7 V” is set. By doing so, in the input circuit, the detection of the level of “1” and “0” of the input signal having a voltage amplitude of about 2.5V is performed at the same timing as that of the voltage amplitude of about 3.3V. Can be done. In the output circuit, the internal signal “1” or “0” having a voltage amplitude of about 3.3 V is converted to “0” or “1” of the output signal having a voltage amplitude of about 2.5 V. Can be performed at the same timing as when the voltage amplitude is about 3.3V.

  Thus, according to the I / O circuit 53 ″ of the semiconductor integrated circuit device according to the twenty-second embodiment, the input / output characteristics when the interface voltage is 3.3V, and the input / output characteristics when the interface voltage is 2.5V. And the change in input / output characteristics of the I / O circuit 53 ″ can be further reduced.

  Further, if the change in the input / output characteristics of the I / O circuit 53 ″ according to the interface voltage becomes small, the power supply ripple generated by the I / O circuit 53 ″ when the interface voltage is 3.3 V, and the interface voltage The ripples of the power source generated by the I / O circuit 53 ″ when the voltage is 2.5 V are made uniform with each other. For this reason, when a plurality of chips formed on a single wafer are tested at the same time, for example, generation of higher harmonics that cannot be predicted can be suppressed, and a highly accurate test can be performed.

  By incorporating such an I / O circuit 53 ″ into the one-chip mixed semiconductor integrated circuit device described in the first to fifteenth and twenty-first embodiments, an interface circuit is not incorporated. Therefore, it is possible to connect to other semiconductor device products and electrical equipment having different power supply voltages, and the system can be easily expanded. Of course, even if the I / O circuit 53 ″ is incorporated in the single-function semiconductor integrated circuit device described in the sixteenth to twentieth embodiments, the same advantages can be obtained and the system can be easily constructed. . In the constructed system, the system can be easily expanded.

  Next, an example of a back gate bias potential setting circuit for generating the potentials Vbp and Vbn will be described.

  50A and 50B are diagrams showing a back gate bias potential setting circuit included in a semiconductor integrated circuit device according to the twenty-second embodiment of the present invention. FIG. 50A is a configuration diagram, and FIG. 50B is a power supply voltage and well bias potential. It is a figure which shows the relationship.

  As shown in FIG. 50A, the back gate bias potential setting circuit 60 includes a VCC level detection circuit 61 that detects whether the power supply VCC is 3.3V or 2.5V, and a detection signal from the detection circuit 61. Accordingly, it is composed of an N-type well (26) potential switching circuit 62 for switching the potential Vbp and a P-type well (27) potential switching circuit 63 for switching the potential Vbn.

  FIG. 50B shows the relationship between the value of the power supply VCC and the potentials Vbp and Vbn output from the voltage setting circuit 60.

  As shown in FIG. 50B, when the operating voltage VCCA of the internal circuit is 3.3V and the interface voltage VCCB is 2.5V, the setting signal CONT. V is set to “1” level. Setting signal CONT. When V is “1” level, the detection circuit 61 outputs a signal for activating the switching circuits 62 and 63. While the switching circuit 62 is active, the switching circuit 62 outputs a potential Vbp of about 4.5V. Similarly, while the switching circuit 63 is active, the switching circuit 63 outputs a potential Vbn of about −1.5V.

  When the internal circuit operating voltage VCCA and the interface voltage VCCB are both 3.3 V, the setting signal CONT. V is set to “0” level. Setting signal CONT. When V is “0” level, the detection circuit 61 deactivates the switching circuits 62 and 63. While the switching circuit 62 is inactive, the switching circuit 62 outputs a potential Vbp of about 3.3 V (= VCCB). Similarly, while the switching circuit 63 is inactive, the switching circuit 63 outputs a potential Vbn of about 0 V (= VSS).

  Note that each of the detection circuit 61 and the switching circuits 62 and 63 basically has a setting signal CONT. As shown in the relationship between input and output in FIG. This is a circuit for switching the value of the potential Vbp and the value of the potential Vbn depending on whether the level of V is “1” or “0”. Therefore, if the potential Vbp = 4.5 V and the potential Vbn = −1.5 V are generated by the internal potential generation circuit, the detection circuit 61 and the switching circuits 62 and 63 are formed by a combination of logic circuits. Can do.

  Further, the switching circuit 62 incorporates a booster circuit that boosts the interface potential VCCB (2.5 V or 3.3 V) or the power supply VCC (3.3 V), and while the switching circuit 62 is active, the interface potential VCCB or the power supply VCC may be boosted and the potential Vbp may be set to 4.5V. In this case, while the switching circuit 62 is inactive, the potential Vbp is set to 3.3 V using the interface potential VCCB or the power supply VCC.

  Similarly, a step-down circuit for stepping down the low potential power supply VSS (0V) is incorporated in the switching circuit 63, and while the switching circuit 63 is active, the low potential power supply VSS (0V) is stepped down to set the potential Vbp to -1.5V. good. In this case, while the switching circuit 63 is inactive, the potential Vbp is set to 0 V using the low potential power supply VSS.

  Next, an example of the circuit of the I / O circuit 53 ″ will be described.

  51 is a circuit diagram of an input circuit and an output circuit included in a semiconductor integrated circuit device according to the twenty-second embodiment of the present invention.

  As shown in FIG. 51, each of the output circuit 70 and the input circuit 71 is a CMOS type inverter.

  The output circuit 70 includes a PMOS 72 whose source is connected to the interface voltage VCCB, and an NMOS 73 whose drain is connected to the drain of the PMOS 72 and whose source is connected to the low-potential power supply VSS. The internal signal dout is supplied to the gate of the PMOS 72 and the gate of the NMOS 73, respectively. A connection node between the drain of the PMOS 72 and the drain of the NMOS 73 is connected to an output pad (not shown). When the internal signal dout is at “0” level, the PMOS 72 charges an external terminal (not shown) to the level of the interface voltage VCCB via the output pad. Further, when the internal signal dout is at “1” level, the NMOS 73 discharges the external terminal to the power supply VSS level via the output pad. In this way, the internal signal dout having a logic level of “1” and “0” is converted into an output signal Dout having a logic level of “0” and “1”, respectively.

  The input circuit 71 includes a PMOS 74 whose source is connected to the high-potential power supply VCCA, an NMOS 75 whose drain is connected to the drain of the PMOS 74, and whose source is connected to the low-potential power supply VSS. An input signal Din is supplied to the gate of the PMOS 74 and the gate of the NMOS 75 via an input pad (not shown). A connection node between the drain of the PMOS 74 and the drain of the NMOS 75 is an output node of the internal signal din. When the input signal Din is at “0” level, the PMOS 74 sets the level of the internal signal din to the level of the power supply VCCA. Further, when the input signal Din is at “1” level, the NMOS 75 sets the level of the internal signal din to the level of the power supply VSS. In this way, the logic levels of “1” and “0” of the input signal Din are detected and input to the internal circuit of the chip as internal signals din having the logic levels of “0” and “1”, respectively. .

  The cross-sectional structures of the PMOSs 72 and 74 and the NMOSs 73 and 75 are shown in FIGS.

  52 is a diagram showing a cross-sectional structure of the circuit shown in FIG. 51. FIG. 52A is a cross-sectional view of the output circuit, and FIG. 52B is a cross-sectional view of the input circuit.

  As shown in FIG. 52A, the PMOS 72 is formed in the N + type well 26 ′, and the potential Vbp is supplied to the back gate of the PMOS 72. The NMOS 73 is formed in the P + type well 27 ′, and the potential Vbn is supplied to the back gate of the NMOS 73.

  As shown in FIG. 52B, the PMOS 74 is formed in the N + type well 26 ″, and the potential Vbp is supplied to the back gate of the PMOS 74. The NMOS 75 is formed in the P + type well 27 ″, and the potential Vbn is supplied to the back gate of the NMOS 75.

  Incidentally, the P + type wells 27 ′ and 27 ″ are formed directly on the P type well 25. The power supply VSS is supplied to the P-type well 25, and the potential Vbn is supplied to each of the P + -type wells 27 'and 27' '. The potential Vbn may be a potential of −1.5 V as described with reference to FIG. At this time, a potential difference of 1.5 V is generated between the P-type well 25 and the P + -type wells 27 ′ and 27 ″. At this time, when a current flows from the P-type well 25 toward the P + type wells 27 ′ and 27 ″, the potential −1.5 V of the P + type wells 27 ′ and 27 ″ increases toward the potential of the power source VSS. To do. Such a situation can be solved by making the P-type well 25 have a high resistance and the P + -type wells 27 ′ and 27 ″ have a low resistance. Preferably, a resistor R having a drop voltage of about 1.5 V is parasitic between the P-type well 25 and the P + -type wells 27 ′ and 27 ″. The resistance values of the P-type well 25 and the P + -type wells 27 ′ and 27 ″ can be adjusted by adjusting the concentration of the P-type impurity. For example, the resistance value of a P-type well can be lowered by increasing the concentration of the P-type impurity, and conversely, it can be increased by decreasing the concentration.

  Note that the I / O circuit included in the semiconductor integrated circuit device according to the twenty-second embodiment includes not only a processor but also various semiconductor integrated devices currently known, such as a DRAM, a Flash-EEPROM, a D / A converter, and an SRAM. Needless to say, the present invention can also be applied to circuit device products and semiconductor integrated circuit device products using system-on-silicon technology.

  Next, a twenty-third embodiment of the present invention is described.

  FIGS. 53A and 53B are views showing a DRAM according to the twenty-third embodiment of the present invention, in which FIG. 53A is a plan view and FIG. 53B is a sectional view taken along line 53B-53B in FIG. In FIGS. 53A and 53B, the same parts as those in FIGS. 46A and 46B are denoted by the same reference numerals, and only different parts will be described.

  As shown in FIGS. 53A and 53B, the DRAM according to the twenty-third embodiment is particularly different from the DRAM according to the twentieth embodiment in that a large N-type well 22 is provided as a memory cell 54-4. N-type well 22A-4 for arranging the internal potential generating circuit 51-4, N-type well 22B-4 for arranging the internal potential generating circuit 51-4, peripheral circuit 55-4, and I / O circuit 53'-4 for arranging The N-type well 22C-4 is separated.

  Thus, the N-type well 22 may be separated for each circuit function. By separating the N-type well for each function of the circuit, it becomes difficult to be affected by the electrical noise of other circuits during the test, and a test with higher accuracy is possible.

  Next, a twenty-fourth embodiment of the present invention is described.

  54A and 54B are views showing a DRAM according to a twenty-fourth embodiment of the present invention, in which FIG. 54A is a plan view and FIG. 54B is a sectional view taken along line 54B-54B in FIG. In FIGS. 54A and 54B, the same parts as those in FIGS. 53A and 53B are denoted by the same reference numerals, and only different parts will be described.

  As shown in FIGS. 54A and 54B, the portions of the DRAM according to the twenty-fourth embodiment that are particularly different from the DRAM according to the twenty-third embodiment are given to the N-type wells 22A-4 and 22B-4. The bias potential to be applied and the bias potential applied to each N-type well 22C-4 have been separated.

  As described above, the N-type well 22 may be separated for each function of the circuit, and an optimum bias potential may be applied to each separated well. By providing an optimal bias potential for each isolated well, it is less susceptible to the electrical noise of other circuits during testing, and power supply ripple can be further reduced. High testing is possible.

  Such well structures according to the twenty-third and twenty-fourth embodiments can be used not only for DRAMs but also for various semiconductor products such as processors, Flash-EEPROMs, D / A converters, and SRAMs.

  Next, a Flash-EEPROM using well structures according to the twenty-third and twenty-fourth embodiments will be described as a twenty-fifth embodiment.

  55 is a view showing a Flash-EEPROM according to a twenty-fifth embodiment of the present invention. FIG. 55 (A) is a plan view, and FIG. 55 (B) is a sectional view taken along line 55B-55B in FIG. is there. In FIGS. 55A and 55B, the same parts as those in FIGS. 44A and 44B are denoted by the same reference numerals, and only different parts will be described.

  The Flash-EEPROM according to the twenty-fifth embodiment is particularly different from the Flash-EEPROM according to the eighteenth embodiment in that the large N-type well 22 is replaced with an N-type well 22A- for arranging the memory cell 54-5. 5. When separated into N-type well 22B-5 for disposing internal potential generating circuit 51-5, N-type well 22C-5 for disposing peripheral circuit 55-5 and I / O circuit 53-5 is there.

  In such a Flash-EEPROM, the N-type well 22 is separated for each function of the circuit. Therefore, as in the 23rd and 24th embodiments, the influence of the electrical noise of other circuits is affected during the test. It becomes difficult to receive. Therefore, a highly accurate test can be performed.

  Further, as shown in the well 25A-5, in the separated well, the bias potential can be switched regardless of other wells. For this reason, for example, in a test performed by operating the memory cell 54-5 using the peripheral circuit 55-5, the potential fluctuation of the well 25A-5 is hardly transmitted to the well 22C-5. Therefore, a highly accurate test can be performed during the above test.

  Next, a twenty-sixth embodiment of the invention is described.

  56A and 56B are views showing a DRAM according to a twenty-sixth embodiment of the present invention. FIG. 56A is a plan view, and FIG. 56B is a cross-sectional view taken along the line 56B-56B in FIG. In FIGS. 56A and 56B, the same portions as those in FIGS. 54A and 54B are denoted by the same reference numerals, and only different portions will be described.

  As shown in FIGS. 56A and 56B, the DRAM according to the twenty-sixth embodiment is different from the DRAM according to the twenty-third embodiment in that an I / O circuit 53′-4 is disposed. The N-type well is separated from the N-type well for arranging the peripheral circuit 55-4. In the drawing, the peripheral circuit 55-4 is disposed in the N-type well 22C-4, and the I / O circuit 53'-4 is disposed in the N-type well 22D-4. Further, the N-type well 22A-4 in which the memory cell 54-4 is formed is biased to the internal potential VDD ″ generated by the internal voltage generation circuit 51-4.

  As described above, the I / O circuit 53'-4 has a large power supply noise. By separating such a well in which the I / O circuit 53′-4 is arranged from other circuits, the other circuits are affected by the electrical noise generated from the I / O circuit 53′-4. It becomes difficult. This enables a test with higher accuracy.

  Further, the N-type well 22A-4 in which the memory cell 54-4 is formed is biased not to the external power supply VCC but to the internal potential VDD ″ generated by the internal voltage generation circuit 51-4. Thereby, the memory cell 54-4 can be made less susceptible to the ripple of the external power supply VCC, and the test of the memory cell 54-4 can be performed with high accuracy.

  In FIGS. 56A and 56B, the high potential side power source of the I / O circuit 53′-4 is the external power source VCC. However, as in the twentieth embodiment, the internal potential VDD ′. 'Also good. When the high potential side power supply of the I / O circuit 53′-4 is set to the internal potential VDD ″, the bias potential of the N-type well 22A-4 is biased to another internal potential different from the internal potential VDD ″. It is preferable to do. As a result, the memory cell 54-4 becomes less susceptible to the influence of electrical noise generated by the I / O circuit 53'-4, and the test accuracy is further improved.

  The well structure that separates the I / O circuit according to the twenty-sixth embodiment from other circuits is used not only for DRAMs but also for various semiconductor products such as processors, Flash-EEPROMs, D / A converters, and SRAMs. can do.

  Next, a twenty-seventh embodiment of the invention is described.

  The twenty-seventh embodiment relates to a Flash-EEPROM test, and more particularly to a Flash-EEPROM test that erases data by emitting electrons to a substrate.

  Flash-EEPROM that erases data by emitting electrons to the substrate includes, for example, a NAND-type Flash-EEPROM.

  NAND-type Flash-EEPROM integrates a memory cell having a floating gate and a control gate capacitively coupled to the channel through the floating gate. An amount of electrons corresponding to the data level is stored in the floating gate. The amount of electrons corresponding to the data level changes the threshold voltage of the memory cell according to the data level. The memory cell stores predetermined data by this threshold voltage.

  In the NAND type Flash-EEPROM, when erasing data, a voltage VSS is applied to the control gate, and both the N type substrate and the P type well formed on this substrate and forming the channel of the memory cell are used. Each gives a positive high voltage VEE. Thereby, the electrons accumulated in the floating gate are released to the well.

  Further, when data is written, a voltage VCC is applied to the substrate, a negative voltage VBB is applied to the well, a voltage is applied between the source and the drain, and a positive voltage VM is applied to the control gate to make the memory cell conductive. . In this state, a positive voltage VPP higher than the voltage VM is applied to the control gate of the memory cell selected for writing. As a result, electrons are injected into the floating gate.

  The memory cell for erasing / writing data in this way is erased according to the structurally parasitic capacitance such as the capacitance Ccf between the control gate and the floating gate and the capacitance Cfc between the floating gate and the channel. / Characteristics related to writing change. In recent memory cells, miniaturization is progressing until a subtle change in structurally parasitic capacitance due to “manufacturing fluctuation” has a great influence on the above characteristics. The above-described variation in subtle fluctuations is small in a local part called a chip, but becomes considerably large in a wafer on which this chip is integrated. For example, even if a conductive film or an insulating film is uniformly deposited / grown over the entire wafer, the film pressure and film quality are not actually uniform. For example, there is a large difference between the film pressure / film quality at the center of the wafer and the film pressure / film quality at the edge of the wafer.

  Therefore, recently, when data is written or erased, voltages such as voltages VPP, VEE, and VBB applied to the memory cell, the well in which the memory cell is formed, and the substrate on which the well is formed are The optimum value is set for each chip.

  However, in Flash-EEPROM in which the voltages VPP, VEE, VBB, etc. are set to optimum values for each chip, a test related to erasure (hereinafter referred to as erasure test) with a plurality of chips formed on a single wafer. Is abbreviated at the same time. That is, since the N-type silicon substrate is an N-type silicon wafer itself, only one voltage VEE should be set even if an erase test is performed simultaneously on a plurality of chips formed on one wafer. I can't. Therefore, in the Flash-EEPROM in which the voltage VEE is set to an optimum value for each chip, the erasure test is performed one by one for the chips formed on one wafer. For this reason, the test time per wafer becomes long and the throughput deteriorates.

  However, in the one-chip mixed semiconductor integrated circuit device described in the first to fifteenth and twenty-first embodiments and the flash-EEPROM described in the eighteenth and twenty-fifth embodiments, the flash-EEPROM is Even if the erase test is simultaneously performed on a plurality of chips formed on one wafer, the optimum voltage VEE can be set for each chip, which is formed in the well 22-5 formed on the substrate 10. .

  57A and 57B are views showing a flash-EEPROM multi-test method according to the twenty-fifth embodiment of the present invention. FIG. 57A is a plan view of a wafer on which a plurality of Flash-EEPROM chips are formed, and FIG. (A) It is sectional drawing which follows the 57B-57B line | wire in a figure.

  As shown in FIGS. 57A and 57B, different values of voltage VEE are applied to the respective wells 22-5. These different values of voltage VEE are optimum values set for each chip.

  According to such a multi-test method, the erase test of the Flash-EEPROM in which the voltage VEE is set to an optimum value for each chip can be performed simultaneously on a plurality of chips formed on one wafer. The test time per wafer can be shortened.

  In the Flash-EEPROM having the structure shown in FIGS. 57A and 57B, not only the voltage value but also the application time for applying the voltage VEE for each chip may be set to an optimum time. it can. Then, the erase test of the Flash-EEPROM in which the voltage VEE application time is set to the optimum time for each chip can be simultaneously performed on a plurality of chips formed on one wafer.

  It is also possible to set both the optimum voltage VEE and the optimum voltage VEE application time for each chip. Then, for each chip, the erase test of the Flash-EEPROM in which the voltage VEE value and the voltage VEE application time are respectively set to optimum times is simultaneously performed on a plurality of chips formed on one wafer. You can also.

  Such a multi-test method can be used not only for a Flash-EEPROM product but also for a single-chip mixed product in which the Flash-EEPROM is incorporated.

  As described above, according to the present invention, a single-chip embedded type that can accurately measure the characteristics of each of a plurality of functional circuits that are mixedly mounted on a single semiconductor chip and that have different functions from each other. A semiconductor integrated circuit device can be provided.

  In addition, it is possible to provide a one-chip mixed type semiconductor integrated circuit device that can extract and maximize the characteristics of a plurality of functional circuits having different functions from one another and mount them on one semiconductor chip.

  Further, it is possible to provide an inspection method for a one-chip mixed type semiconductor integrated circuit device that enables accurate measurement of characteristics of a plurality of functional circuits that are mixedly mounted on one semiconductor chip and have different functions.

  Furthermore, even when a test of a semiconductor integrated circuit device is performed simultaneously on a single wafer with a plurality of semiconductor integrated circuit devices, electrical interference between the semiconductor integrated circuit devices, particularly interference between power supply voltages, can be suppressed. A semiconductor integrated circuit device having a structure capable of measuring characteristics of each integrated circuit device with high accuracy can be provided.

  In addition, even when a static current consumption test of a semiconductor integrated circuit device is performed simultaneously on a single wafer using a plurality of semiconductor integrated circuit devices, the static current consumption characteristics of each semiconductor integrated circuit device can be measured with high accuracy. An inspection apparatus for a semiconductor integrated circuit device can be provided.

1A and 1B are diagrams showing a semiconductor integrated circuit device according to a first embodiment of the present invention, in which FIG. 1A is a plan view, FIG. 1B is a cross-sectional view taken along line 1B-1B in FIG. (C) The figure is a sectional view along line 1C-1C in (A). FIG. 2 is a plan view when the semiconductor integrated circuit device according to the first embodiment of the present invention is formed on a wafer. 3 is an enlarged view of the wafer shown in FIG. 2. FIG. 3 (A) is a plan view inside the two-dot chain line frame 3A in FIG. 2, and FIG. 3 (B) is along the line 3B-3B in FIG. Sectional view, (C) is a sectional view along line 3C-3C in (A) Figure FIG. 4 is a plan view when the semiconductor integrated circuit device according to the first embodiment of the present invention is tested. FIG. 5 shows a wafer probing test system. FIG. 6 is a sectional view of a semiconductor integrated circuit device according to the second embodiment of the present invention. 7 is a cross-sectional view of the well 22-2 shown in FIG. 8 is a cross-sectional view of the well 22-3 shown in FIG. 9A and 9B are cross-sectional views of the well 22-4 shown in FIG. 10A and 10B are cross-sectional views of the well 22-5 shown in FIG. FIG. 11 is a block diagram of the power supply system of the apparatus according to the second embodiment. 12A and 12B are diagrams showing the generation timing of the external power supply and the internal power supply. FIG. 12A is a diagram showing the generation timing during actual use, and FIGS. 12B and 12C are examples of the generation timing during testing. Illustration FIG. 13 is a sectional view of a semiconductor integrated circuit device according to the third embodiment of the present invention. 14A and 14B are cross-sectional views of the well 22-2 shown in FIG. FIG. 15 is a sectional view of a semiconductor integrated circuit device according to the fourth embodiment of the present invention. 16A and 16B are cross-sectional views of the well 22-4 shown in FIG. FIG. 17 is a sectional view of a semiconductor integrated circuit device according to the fifth embodiment of the present invention. 18A and 18B are cross-sectional views of the wells 22A-4 and 22B-4 shown in FIG. 17, respectively. FIG. 19 is a sectional view of a semiconductor integrated circuit device according to the sixth embodiment. 20A and 20B are cross-sectional views of the wells 22A-5 and 22B-5 shown in FIG. 19, respectively. 21A and 21B are views showing a semiconductor integrated circuit device according to a seventh embodiment of the present invention. FIG. 21A is a plan view, FIG. 21B is a sectional view taken along line 21B-21B in FIG. (C) The figure is a sectional view taken along line 21C-21C in (A). 22A and 22B are sectional views of a semiconductor integrated circuit device according to the eighth embodiment of the present invention. FIG. 23 is a cross-sectional view of the well 22-6 shown in FIGS. 22 (A) and 22 (B). 24 is a sectional view of the well 22-7 shown in FIGS. 22 (A) and 22 (B). 25A and 25B are views showing a semiconductor integrated circuit device according to a ninth embodiment of the present invention. FIG. 25A is a plan view, and FIG. 25B is a sectional view taken along line 25B-25B in FIG. (C) The figure is a sectional view taken along line 25C-25C in (A). FIG. 26 is a sectional view of a semiconductor integrated circuit device according to the tenth embodiment of the invention. 27 is a sectional view of the well 22-8 shown in FIG. FIG. 28 is a plan view when the semiconductor integrated circuit device according to the eleventh embodiment of the present invention is tested. FIG. 29 is a plan view showing a basic configuration of a semiconductor integrated circuit device chip according to the first to eleventh embodiments of the present invention. FIG. 30 is a schematic diagram schematically showing a state in which the chip shown in FIG. 29 is multi-tested. 31 is an equivalent circuit diagram of the state shown in FIG. 32 is a diagram showing the ripple of the power supply of each chip shown in FIG. FIG. 33 is a system configuration diagram showing the configuration of the test system according to the twelfth embodiment of the present invention. FIG. 34 is a plan view showing the basic structure of a semiconductor integrated circuit device chip according to a thirteenth embodiment of the present invention. FIG. 35 is a schematic diagram schematically showing a state in which the chip shown in FIG. 34 is multi-tested. FIG. 36 is an equivalent circuit diagram of the state shown in FIG. FIG. 37 is a diagram showing the ripple of the power supply of each chip shown in FIG. FIG. 38 is a plan view showing a state where a semiconductor integrated circuit chip according to a thirteenth embodiment of the present invention is formed on a wafer. FIG. 39 is a plan view of a semiconductor integrated circuit device chip according to a thirteenth embodiment of the present invention packaged. FIG. 40 is a system configuration diagram showing the configuration of a test system according to the fourteenth embodiment of the present invention. FIG. 41 is a block diagram showing the configuration of the test apparatus according to the fifteenth embodiment of the present invention. 42A and 42B are views showing a semiconductor integrated circuit device according to a sixteenth embodiment of the present invention. FIG. 42A is a plan view, and FIG. 42B is a sectional view taken along line 42B-42B in FIG. 43 is a view showing a semiconductor integrated circuit device according to a seventeenth embodiment of the present invention. FIG. 43 (A) is a plan view, and FIG. 43 (B) is a sectional view taken along line 43B-43B in FIG. 44A and 44B are views showing a semiconductor integrated circuit device according to an eighteenth embodiment of the present invention. FIG. 44A is a plan view, and FIG. 44B is a sectional view taken along line 44B-44B in FIG. 45A and 45B are views showing a semiconductor integrated circuit device according to a nineteenth embodiment of the present invention. FIG. 45A is a plan view, and FIG. 45B is a sectional view taken along line 45B-45B in FIG. 46A and 46B are views showing a semiconductor integrated circuit device according to a twentieth embodiment of the present invention. FIG. 46A is a plan view, and FIG. 46B is a sectional view taken along line 46B-46B in FIG. FIG. 47 is a plan view of a semiconductor integrated circuit device according to the twenty-first embodiment of the present invention. FIG. 48 schematically shows a system configured using a semiconductor integrated circuit device according to the twenty-second embodiment of the present invention. FIG. 48A shows a system in which products having the same power supply voltage level are combined. The figure which shows, (B) the figure which shows the system which combines the products where the level of power supply voltage differs 49A and 49B are views showing a semiconductor integrated circuit device according to a twenty-second embodiment of the present invention. FIG. 49A is a plan view, and FIG. 49B is a sectional view taken along line 49B-49B in FIG. FIG. 50 is a diagram showing a well bias potential switching circuit included in a semiconductor integrated circuit device according to a twenty-second embodiment of the present invention. FIG. 50 (A) shows a configuration diagram, and FIG. 50 (B) shows power supply voltage and well bias potential. Diagram showing relationship 51 is a circuit diagram of an input circuit and an output circuit included in a semiconductor integrated circuit device according to a twenty-second embodiment of the present invention. 52 is a diagram showing a cross-sectional structure of the circuit shown in FIG. 51, (A) is a cross-sectional view of the output circuit, and (B) is a cross-sectional view of the input circuit. 53 is a diagram showing a semiconductor integrated circuit device according to a twenty-third embodiment of the present invention. FIG. 53 (A) is a plan view, and FIG. 53 (B) is a sectional view taken along line 53B-53B in FIG. 54 is a view showing a semiconductor integrated circuit device according to a twenty-fourth embodiment of the present invention. FIG. 54 (A) is a plan view, and FIG. 54 (B) is a sectional view taken along line 54B-54B in FIG. 55 is a view showing a semiconductor integrated circuit device according to a twenty-fifth embodiment of the present invention. FIG. 55 (A) is a plan view, and FIG. 55 (B) is a sectional view taken along line 55B-55B in FIG. 56 is a view showing a semiconductor integrated circuit device according to a twenty-sixth embodiment of the present invention. FIG. 56 (A) is a plan view, and FIG. 56 (B) is a sectional view taken along line 56B-56B in FIG. FIG. 57 is a view showing a non-volatile memory multi-test method according to a twenty-seventh embodiment of the present invention. FIG. 57 (A) is a plan view of a wafer on which a plurality of nonvolatile memory chips are formed, and FIG. (A) Sectional view along line 57B-57B in the figure

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit chip, 2 ... Processor, 3 ... SRAM, 4 ... DRAM, 5 ... Flash-EEPROM, 6 ... D / A converter, 7 ... Analog circuit, 8 ... Logic circuit, 10 ... Isolation area (P-type silicon) Substrate), 11 ... wafer, 12 ... dicing line, 22 ... N type well, 23 ... P type well, 24 ... N type well, 25 ... P type well, 26 ... N type well, 27 ... P type well, 28 ... N-type well, 30 ... voltage generation circuit, 31 ... control circuit, 60 ... back gate bias potential setting circuit, 61 ... VCC level detection circuit, 62 ... N-type well potential switching circuit, 63 ... P-type well potential switching circuit, 70 ... Output circuit, 71 ... Input circuit, 72, 74 ... PMOS, 73, 75 ... NMOS, 100 ... Probe card, 101 ... Measurement unit, 102 ... Probe, 103 ... Contactor, 04 ... Pad, 200, 200A, 200B, 200C, 200D ... Test station, 300, 300 ', 300' '... Test equipment, 301A, 301B, 301C, 301D ... VCC generator, 302A, 302B, 302C, 302D ... Bias Power terminal, 303A, 303B, 303C, 303D ... Power terminal, 304A, 304B, 304C, 304D ... Power terminal, 305A, 305B, 305C, 305D ... Power supply voltage detection circuit, 306A, 306B, 306C, 306D ... Cutoff switch, 307 Detected voltage determination device 308 CPU 309 Switch driver 501 VSS-SUB wiring 502 VSS wiring 503 504 506 pad 505 VCC wiring 507 lead terminal

Claims (20)

A first conductivity type semiconductor substrate;
At least two first-conductivity-type first semiconductor regions formed in the semiconductor substrate;
A second semiconductor region of a first conductivity type insulated from the semiconductor substrate and formed in a first semiconductor region of a second conductivity type;
Separating and adjoining the at least two first-conductivity-type first semiconductor regions;
A semiconductor integrated circuit portion constituted by semiconductor elements formed in the first semiconductor region of the second conductivity type and the second semiconductor region of the first conductivity type;
In order to apply an operating voltage to the semiconductor integrated circuit unit, the first semiconductor region and the second semiconductor region have at least one high potential power terminal and low potential power terminal,
A bias potential is applied to the semiconductor substrate at the time of testing and when configuring a semiconductor integrated circuit part other than the region formed by separating and adjoining the at least two first-conductivity-type first semiconductor regions. A semiconductor integrated circuit device, comprising: a terminal for performing the operation. A first conductivity type semiconductor substrate;
At least two first-conductivity-type first semiconductor regions formed in the semiconductor substrate;
A second semiconductor region of a first conductivity type insulated from the semiconductor substrate and formed in a first semiconductor region of a second conductivity type;
Separating and adjoining the at least two first-conductivity-type first semiconductor regions;
A plurality of semiconductor elements formed in the first semiconductor region and the second semiconductor region and constituting a processor circuit;
A plurality of semiconductor elements formed in the other first semiconductor region and the other second semiconductor region and constituting a static memory circuit;
A high potential power supply terminal and a low potential power supply terminal for applying an operating voltage to the processor circuit and the static memory circuit;
A bias potential is applied to the semiconductor substrate at the time of testing and when configuring a semiconductor integrated circuit part other than the region formed by separating and adjoining the at least two first-conductivity-type first semiconductor regions. A semiconductor integrated circuit device, comprising: a terminal for performing the operation. A plurality of semiconductor elements formed in the first semiconductor region and the second semiconductor region and constituting a memory cell array circuit;
A plurality of semiconductor elements formed in the other first semiconductor region and the other second semiconductor region and constituting a memory peripheral circuit;
2. The semiconductor integrated circuit device according to claim 1, wherein a memory integrated circuit is formed by the memory cell array circuit and the memory peripheral circuit.   4. The semiconductor integrated circuit according to claim 3, wherein the memory cell array circuit is a Flash-EEPROM memory cell array circuit, and the memory peripheral circuit is a Flash-EEPROM memory peripheral circuit.   A bias potential is applied to the substrate independent of the high-potential power supply terminal and the low-potential power supply terminal, in addition to the region formed by separating and adjacent to the at least two first-conductivity-type first semiconductor regions. 5. The semiconductor integrated circuit device according to claim 1, wherein a terminal to be provided is provided on the semiconductor substrate of the first conductivity type. A first internal voltage generation circuit for generating a first internal voltage applied to the semiconductor integrated circuit portion, formed in at least one first semiconductor region of the second conductivity type;
5. The semiconductor integrated circuit device according to claim 1, further comprising a second internal voltage generation circuit for generating a second internal voltage. 6.   6. The semiconductor integrated circuit device according to claim 1, further comprising a power on / off circuit and a control circuit in at least one first conductive region of the second conductivity type.   6. The semiconductor integrated circuit device according to claim 1, further comprising a power supply on / off time circuit and a control circuit in at least one first semiconductor region of the second conductivity type. .   The at least one output terminal is provided in the said semiconductor integrated circuit part formed in the at least 1 1st semiconductor region of 2nd conductivity type, The Claim 1 thru | or 5 characterized by the above-mentioned. Semiconductor integrated circuit device.   6. The semiconductor integrated circuit according to claim 1, wherein a bias potential is independently applied to at least the first semiconductor region of the second conductivity type and the second semiconductor region of the first conductivity type. apparatus. A first conductivity type semiconductor substrate; a second conductivity type first well formed in the first conductivity type semiconductor substrate;
A second well of the first conductivity type formed in the first well;
A second well of a second conductivity type formed in the semiconductor substrate of the first conductivity type;
A fourth well of the first conductivity type formed in the third well;
Separating the first well and the third well adjacent to each other;
A plurality of semiconductor elements constituting a first functional circuit formed in the first well and the second well;
A plurality of semiconductor elements constituting a second functional circuit formed in the third well and the fourth well;
First power supply means for applying operating power to the first functional circuit;
Second power supply means for applying operating power to the second functional circuit;
A terminal for applying the semiconductor bias potential to the semiconductor substrate of the first conductivity type when the test and the semiconductor integrated circuit are configured;
A semiconductor integrated circuit device comprising:   12. The semiconductor integrated circuit device according to claim 11, wherein a memory cell array is constituted by the first functional circuit, and a memory peripheral circuit is constituted by the second functional circuit. 2. The memory cell array is a flash EEPROM memory cell array, and the memory peripheral circuit is a flash EEPROM memory peripheral circuit.
3. The semiconductor integrated circuit device according to 2.   12. The semiconductor integrated circuit device according to claim 11, wherein the first functional circuit forms a processor circuit, and the second functional circuit forms a static memory circuit. A fifth well of the second conductivity type formed in the first well;
A sixth well of the second conductivity type formed in the third well;
A plurality of semiconductor elements formed in the fifth and sixth wells;
The first functional circuit includes a plurality of semiconductor elements formed in the second well and the fifth well,
The said 2nd functional circuit is comprised by the some semiconductor element formed in the said 4th well and the said 6th well, The Claim 11 thru | or 14 characterized by the above-mentioned. Semiconductor integrated circuit device. A first internal voltage generating circuit for generating a first internal voltage applied to the first functional circuit, formed in the first well;
15. The device according to claim 11, further comprising a second internal voltage generation circuit that is formed in the third well and generates a second internal voltage applied to the second functional circuit. A semiconductor integrated circuit device according to claim 1.   15. The semiconductor integrated circuit device according to claim 11, further comprising a power on / off circuit and a control circuit in the first well and the third well.   15. The semiconductor integrated circuit device according to claim 11, further comprising a power on time / off time circuit and a control circuit in the first well and the third well.   16. The semiconductor integrated circuit device according to claim 11, wherein the first functional circuit and the second functional circuit each have an independent output terminal.   16. The semiconductor integrated circuit device according to claim 11, wherein a bias potential is independently applied to at least the first well, the second well, the third well, and the fourth well.

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