JP2005158150A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology in which a probe test using an existing circuit tester is made possible even if standby current for a chip increases. <P>SOLUTION: When multiple measurement areas (101,102) are set up, multiple step-down circuits (111,112) which can step down each of supply voltage externally supplied and a selection circuit (104) which can selectively supply output voltage for the step-down circuit to the corresponding measurement areas are arranged. The amount of current in the probe test is reduced by selectively supplying the output voltage for the step-down circuit to the corresponding measurement areas and separately performing the probe test to each of the measurement areas. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit and a technique for facilitating a probe test in the semiconductor integrated circuit, and more particularly to a technique effective when applied to a semiconductor memory device such as an SRAM (Static Random Access Memory).

  In a semiconductor integrated circuit, as a technique for blocking potential fluctuations caused by asynchrony between circuit blocks operating asynchronously and effectively preventing the generation of interference noise, a well is formed between each circuit block operating asynchronously. A technique is known in which a power supply line and a signal line are separated and wired separately and connected to each circuit block (see, for example, Patent Document 1). In this case, the potential fluctuation is not transmitted between the circuit blocks, and malfunctions due to interference noise and a decrease in operating speed are prevented.

  Further, in order to accurately control the potential of the power supply line shared by the plurality of memory blocks, the potential of the Vpp trunk line that is provided in common to the plurality of memory array banks and supplies the boosted potential is detected by the Vpp level detection circuit. Depending on the result, the boost pump circuit supplies current to the Vpp trunk line, and the position of the Vpp trunk line observed by the Vpp level detection circuit is made substantially equal from each memory block. A technique for reducing the influence of the activation state of the memory array bank when controlling the potential of the memory array is known (see, for example, Patent Document 2).

  Furthermore, in a semiconductor memory device having a plurality of memory cells spatially divided into a plurality of phenomenon regions, a noise source that is biased toward the power source on the upper side or the lower side, and vertically distributed on the left side and the right side. A technique is known for reducing the operation speed and increasing the speed of operation of the sense amplifier (for example, Patent Document 3). In this case, the memory cell array is divided into four regions, and an X decoder for addressing and activating the sections and a Y decoder arranged between the left and right quadrant regions are provided, and a plurality of quadrants are provided. The main power supply section is wired along the periphery of the region, and the power supplies wired above and below the semiconductor chip (also simply referred to as “chip”) are mainly used in the upper and lower quadrants.

Japanese Patent Laid-Open No. 9-331023 (FIG. 1) Japanese Patent Laid-Open No. 2001-67868 (FIGS. 12 and 13) JP-A-9-289293 (FIG. 1)

  The semiconductor integrated circuit is subjected to a probe test in a wafer state. In this probe test, power is supplied to the semiconductor chip from the tester through the probe, but the off-state current of the MOS transistor tends to increase as the process becomes finer. In particular, in an SRAM designed with priority given to high-speed operation, the off-current tends to increase in order to sufficiently secure the on-current of the single MOS transistor. In such an SRAM, when the standby current increases as the memory capacity increases, it is considered that the power supply current per chip exceeds the allowable value in the probe test. Probe test using tester becomes impossible.

  An object of the present invention is to provide a technique for enabling a probe test using an existing tester regardless of an increase in standby current of a chip.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, when having a plurality of circuit blocks whose operating power supply paths are separated from each other, a plurality of step-down circuits capable of stepping down the power supply voltage supplied from the outside, and the corresponding circuit block corresponding to the output voltage of the step-down circuit And a selection circuit which can be selectively supplied.

  According to the above means, the output voltage of the step-down circuit is selectively supplied to the corresponding circuit block, and the probe test is performed separately for each circuit block, thereby reducing the amount of current during the probe test. can do. This enables a probe test using an existing tester regardless of an increase in the standby current of the chip.

  At this time, it is possible to provide a plurality of power supply terminals provided corresponding to the plurality of step-down circuits, and for taking in the power supply voltage supplied to the corresponding step-down circuits from the outside. Further, a power supply terminal for taking in a common power supply voltage can be provided in the plurality of step-down circuits.

  When having a plurality of circuit blocks whose operation power supply paths are separated from each other, a plurality of step-down circuits capable of stepping down a power supply voltage supplied from the outside, a control circuit capable of controlling the operation of the step-down circuit, A test power supply voltage supply terminal capable of selectively supplying a power supply voltage to the plurality of circuit blocks in a state where voltage output from the step-down circuit is stopped by the control circuit can be provided.

  According to the above means, the power supply voltage is selectively supplied to the plurality of circuit blocks in a state where the voltage output from the step-down circuit is stopped by the control circuit, and the probe test is performed for each circuit block. By performing them separately, the amount of current during the probe test can be reduced. This enables a probe test using an existing tester.

  At this time, it is possible to provide a plurality of power supply terminals for taking in a power supply voltage supplied to the corresponding step-down circuit from the outside. Further, a power supply terminal for taking in a common power supply voltage can be provided in the plurality of step-down circuits.

  A rewiring region is interposed between the chip and the package substrate, and power wiring can be performed using this rewiring region.

  When the inter-power supply protection element is provided between the power supply terminals, the inter-power supply protection element includes a MOS transistor connected between the power supply terminals and an enable circuit capable of conducting the MOS transistor after the probe test. Can do.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, by selectively supplying the power supply voltage to a plurality of circuit blocks and performing the probe test separately for each circuit block, the amount of current during the probe test can be reduced. For this reason, a probe test using an existing tester is possible regardless of an increase in the standby current of the chip.

  FIG. 14 shows an SRAM (Static Random Access Memory) which is an example of a semiconductor integrated circuit according to the present invention. The SRAM 141 is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique.

  MUL0 to MUL7, MUR0 to MUR7, MLL0 to MLL7, and MLR0 to MLR7 are cell arrays in which memory cells are arranged in an array. This memory cell array is largely divided into four areas by interposing peripheral circuits described later. Distributed. MWD is a main word driver. CK / ADR / CNTL is an input circuit for clock signals, address signals, memory control signals, etc., DI / DQ is a data input / output circuit, I / O is an input / output circuit for mode switching signals, test signals, DC signals, etc. It is. In this example, an example of the center pad system is shown, and for this reason, the CK / ADR / CNTL circuit, the DI / DQ circuit, and the I / O circuit are located at the center of the chip. REG / PDEC is a predecoder, DLLL is a clock synchronization circuit, JTAG / TAP is a test circuit, and VG is an internal power supply voltage generation circuit. FUSE is a fuse circuit, and is used for memory array defect relief and the like. VREF is a reference voltage generation circuit that generates a reference voltage for taking in an input signal.

  In the SRAM 141, circuit blocks other than the memory cell arrays MUL0 to MUL7, MUR0 to MUR7, MLL0 to MLL7, and MLR0 to MLR7 are collectively referred to as the peripheral circuit unit 103 because they are arranged around the memory cell array. Of the memory cell arrays (MUL0 to MUL7, MUR0 to MUR7, MLL0 to MLL7, and MLR0 to MLR7) that are widely distributed in four areas through the peripheral circuit unit 103, the MUL0 to MUL7 and MUR0 to MUR7 are One memory array unit 101 is collectively referred to, and MLL0 to MLL7 and MLR0 to MLR7 are collectively referred to as a second memory cell array unit 102.

  FIG. 1 shows a relationship between a configuration example of the SRAM 141 and a power supply voltage supplied thereto.

  In the configuration shown in FIG. 1, the first memory array unit 101, the second memory cell array unit 102, and the peripheral circuit unit 103 are provided with dedicated step-down circuits 111, 112, and 113, respectively. The step-down circuits 111, 112, and 113 form internal power supply voltages VDDIi, VDDIj, and VDDIp, respectively, by stepping down the power supply voltage VDD taken in through the common power supply terminal 301. Although not particularly limited, the power supply voltage VDD is 1.5V, and the internal power supply voltages VDDIi, VDDIj, and VDDIp are 1 to 1.2V. The low level side of the operating power supply is the ground VSS. Further, in the configuration shown in FIG. 1, a selection circuit 104 for selectively activating the step-down circuits 111, 112, and 113 based on an internal power supply control signal is provided.

  Here, the first memory cell array unit 101 and the second memory cell array unit 102 are examples of circuit blocks in the present invention.

  FIG. 15 shows a configuration example of the step-down circuit 111.

  Although not particularly limited, the step-down circuit 111 includes a reference voltage generation circuit 151 that forms a reference voltage REF, and an output circuit 161 that is arranged in the subsequent stage and forms an internal power supply voltage VDDIi based on the reference voltage REF. . The output circuit 161 is configured as follows.

  A power supply voltage VDD is applied to the drain electrodes of the n-channel MOS transistors 156 and 157 via a current mirror type load. The source electrodes of n-channel MOS transistors 156 and 157 are coupled to ground VSS via n-channel MOS transistor 158. An output signal from the drain electrode of n channel type MOS transistor 156 is transmitted to the gate electrode of p channel type MOS transistor 159 in the subsequent stage. The source electrode of p channel type MOS transistor 159 is coupled to the gate electrode of n channel type MOS transistor 157. The power supply voltage VDD is applied to the source electrode of the p-channel MOS transistor 159, and the internal power supply voltage VDDIi is output from the drain electrode of the p-channel MOS transistor 159.

  Resistors 152 and 153 for dividing the reference voltage REF are connected in series. The n-channel MOS transistor 158 is biased by the output voltage of the series connection node of the resistors 152 and 153. An n-channel MOS transistor 160 is provided between the gate electrode of the n-channel MOS transistor 158 and the ground VSS. The operation of the n-channel MOS transistor 160 is controlled by the internal power control signal. That is, when the internal power supply control signal is at a high level, the n-channel MOS transistor 158 is turned on, and the gate electrode of the n-channel MOS transistor 158 is set to the ground VSS level. Is turned off. In this state, the internal power supply voltage VDDIi is not output. On the other hand, when the internal power supply control signal is at a low level, the n-channel MOS transistor 158 is biased by the output voltage from the series connection node of the resistors 152 and 153, thereby outputting the internal power supply voltage VDDIi. Is done.

  The other step-down circuits 112 and 113 are configured in the same manner as the step-down circuit 111.

  Next, the probe test of the SRAM 141 will be described.

  FIG. 13 shows a probe test apparatus used for the probe test of the SRAM 141. The probe test apparatus 130 is not particularly limited, but includes a stage 133 for placing the wafer 132, a tool (also referred to as a card) 134 provided with a needle 135 that can contact the wafer 132, and the tool 134. And a tester 131 for supplying various power signals and various control signals to the wafer 132 and processing various signals collected from the wafer 132 via the jig 134. A large number of SRAMs 141 are formed on the wafer 132 and cut into one chip in the dicing process of the probe test. A plurality of jigs 134 having different needle arrangement patterns and the like in relation to the measurement area are prepared, and can be appropriately replaced with one corresponding to the measurement area.

  FIG. 12 shows the flow of the probe test of the SRAM 141.

  First, the jig 134 corresponding to the measurement area is set (121) and used. Here, the measurement area refers to either the first memory cell array unit 101 or the second memory cell array unit 102 in the SRAM 141. That is, as the jigs 132, those corresponding to the measurement of the first memory cell array unit 101 and those corresponding to the measurement of the second memory cell array unit 102 are prepared, and the jigs corresponding to the measurement area are related. A tool 134 is set.

  FIG. 2 shows the relationship between the measurement area of the SRAM 141 and the applied power supply voltage. In the figure, “ON” means power supply voltage application.

  When the jig 134 corresponding to the measurement of the first memory cell array unit 101 is set, the step-down circuits 111 and 113 are activated by the selection circuit 104. As a result, the power supply voltages VDDIp and VDDIi are supplied to the SRAM 141, whereby the peripheral circuit unit 103 and the first memory cell array unit 101 are operated, and a probe test is performed on the first memory cell array unit 101. This probe test includes a test of whether or not predetermined pattern data is written and read by the tester 131 and is correctly performed. At this time, since the power supply voltage VDDIj is not supplied to the SRAM 141, the probe test of the second memory cell array unit 102 is not performed.

  Next, it is determined whether or not the test of all measurement areas has been completed (124). In this determination, when it is determined that the test of all measurement areas has not been completed (NO), the tool is replaced with a jig corresponding to the next measurement area, and the test for the measurement area is performed (121). ). That is, after the probe test for the first memory cell array unit 101 is completed, the probe test jig 134 for the second memory cell array unit 102 is replaced with a jig 134 for the probe test, and the step-down circuits 112 and 113 are activated by the selection circuit 104. As a result, the power supply voltages VDDIp and VDDIj are supplied to the SRAM 141 this time. As a result, the peripheral circuit unit 103 and the second memory cell array unit 102 are operated, and a probe test is performed on the second memory cell array unit 102. This probe test includes a test of whether or not predetermined pattern data is written and read by the tester 131 and is correctly performed. At this time, since the power supply voltage VDDIi is not supplied to the SRAM 141, the probe test of the first memory cell array unit 101 is not performed. If it is determined in step 123 that the test for all measurement areas has been completed (YES), the probe test according to the flowchart of FIG. 12 is terminated.

  According to the above example, the following operational effects can be obtained.

  That is, a power supply voltage is selectively supplied to the first memory cell array unit 101 and the second memory cell array unit 102 which are a plurality of measurement areas (circuit blocks), and the first memory cell array unit 101 and the second memory cell array unit 102 are supplied. By performing the probe test separately, the amount of current supplied from the tester 131 to the SRAM 141 is approximately ½ that when the probe test of the first memory cell array unit 101 and the second memory cell array unit 102 is performed simultaneously. can do. Therefore, if the memory cell array is divided into a plurality of memory cell array sections 101 and 102 and they are separately tested in this way, the probe test using the existing tester 131 can be performed regardless of the increase in the standby current of the chip. It is possible. In particular, in an SRAM designed to give priority to high-speed operation, the off-current tends to increase due to the necessity of sufficiently securing the on-current of the single MOS transistor, so the first memory cell array unit 101 and the second memory cell array unit The effect of separately performing the probe test with 102 is considered significant.

  FIG. 5 shows a relationship between another configuration example of the SRAM 141 and a power supply voltage supplied thereto.

  In the configuration shown in FIG. 5, power supply terminals 31-1, 31-2, 31-3 are provided, and the power supply voltages VDDi, VDDp, VDDj is taken in. The power supply voltages VDDi, VDDp, and VDDj are not particularly limited, but are set to 1.5V. Even in such a configuration, as in the case shown in FIG. 3, the current supplied from the tester 131 to the SRAM 141 by performing the probe test on the first memory cell array unit 101 and the second memory cell array unit 102 separately is This can be approximately ½ of the case where the probe test of the first memory cell array unit 101 and the second memory cell array unit 102 is performed simultaneously.

  FIG. 6 shows a relationship between another configuration example of the SRAM 141 and a power supply voltage supplied thereto.

  In the configuration shown in FIG. 6, the control circuit 105 for simultaneously deactivating the step-down circuits 111, 112, and 113 by the internal power supply control signal at the time of the probe test, and the power supply voltage dedicated for the probe test are captured. Power supply terminals 61-1, 61-2, 61-3 are provided. During the probe test, the step-down circuits 111, 112, 113 are simultaneously deactivated by the control circuit 105, and a power supply voltage dedicated to the probe test is supplied from the power supply terminals 61-1, 61-2, 61-3. It is captured. The jig 134 determines which of the power supply terminals 61-1, 61-2, and 61-3 is used to capture the power supply voltage. Basically, when the probe test of the first memory cell array 101 is performed, the power supply voltage is taken in via the power supply terminals 61-1 and 61-3, and the probe test of the second memory cell array 102 is performed. In this case, the power supply voltage is taken in via the power supply terminals 61-2 and 61-3.

  Even in such a configuration, the first memory cell array unit 101 and the second memory cell array unit 102 are separately subjected to the probe test, so that the current supplied from the tester 131 to the SRAM 141 is the first memory cell array unit 101 and the second memory cell array unit. This can be approximately ½ of the case where the probe test with the unit 102 is performed simultaneously.

  Note that the power terminals 13-1, 13-2, and 13-3 in FIG. 6 may be replaced with one power terminal. For example, as shown in FIG. 7, the power supply voltage taken from one power supply terminal 31 can be supplied to the step-down circuits 111, 112, and 113.

  When power supply reinforcement is performed by WPP (Wafer Process Package) wiring, the internal power supply voltages VDDi, VDDp, and VDDj may be short-circuited. In such a case, power supply to the first memory cell array unit 101 is Consider that the power supply to the second memory cell array unit 1 cannot be selectively performed. In that case, the probe test should be performed according to the following procedure.

  For example, the redistribution region is interposed between the chip 804 and the package substrate 802 as indicated by 803 in FIG. Rewiring is performed using the rewiring area 803. The redistribution region 803 and the package substrate 802 are coupled via a solder bump 805. In the rewiring area 803, the WPP wiring 806 is coupled to power terminals (metal pads) 31-1, 31-2, and 31-3 formed on the chip 804 and is coupled to the solder ball 805. In the package substrate 802, the solder ball 805 and the VDD plane 807 are coupled through a through hole (TH). VDD plane 807 is coupled to BGA solder ball 801. According to such a configuration, since the power supply is reinforced by the WPP wiring 806, the internal power supply voltages VDDi, VDDp, and VDDj can be stabilized. However, when the internal power supply voltages VDDi, VDDp, and VDDj are short-circuited by the WPP wiring, the power supply to the first memory cell array unit 101 and the power supply to the second memory cell array unit 1 are selectively performed. In such a case, the probe test according to the flowchart of FIG. 12 is performed before the rewiring region 802 is formed. After that, the WPP wiring 806 for power supply reinforcement is formed. Like that.

  As shown in FIG. 9, when the internal power supply voltages VDDi, VDDp, and VDDj are short-circuited by the WPP wiring, in other words, when the internal power supply voltages VDDi, VDDp, and VDDj are not reinforced. The probe test according to the flow of FIG. 12 can be performed before and after the formation of the rewiring region 802.

  Further, in the chip, as shown in FIG. 10, there are cases where inter-power supply protection elements 51 to 59 are interposed between the power supply terminals. The inter-power supply protection elements 57 to 59 that couple the internal power supply voltages VDDIi, VDDIj, and VDDIp affect the probe test and are configured as follows.

  FIG. 11 shows a configuration example of the inter-power supply protection element 57.

  The inter-power supply protection element 57 is formed by coupling an enable circuit 61 and a short-circuit portion 62. The enable circuit 61 can be easily configured by a fuse 611, an n-channel MOS transistor 612, and an inverter 613. Internal power supply voltage VDDIp is applied to fuse 611. An n-channel MOS transistor 612 is connected in series to the fuse 611. An internal power supply voltage VDDIp is supplied to the gate electrode of the n-channel MOS transistor 612. Inverter 613 is coupled to a serial connection node of fuse 611 and n-channel MOS transistor 612. The power supply voltage for operation of the inverter 613 is VDDIi. Then, the output signal of the inverter 613 is transmitted to the short circuit unit 62. The short-circuit portion 62 can be composed of an n-channel MOS transistor 621. In the n-channel MOS transistor 621, the internal power supply voltage VDDIi is applied to the drain electrode, and the internal power supply voltage VDDIj is applied to the source electrode. The output signal of the enable circuit 61 is supplied to the gate electrode of the n-channel MOS transistor 621. The inter-power supply protection elements 58 and 59 are configured in the same manner.

  In such a configuration, when the fuse 611 is not cut, the output signal of the inverter 613 is at a low level, so that the n-channel MOS transistor 621 is turned off. However, when the fuse 611 is cut, the output signal of the inverter 613 is set to the high level, so that the n-channel MOS transistor 621 is turned on. Therefore, the fuse 611 is not cut until the probe test is finished, and the fuse 611 is cut after the probe test is finished. By doing so, the internal power supply voltages VDDIi, VDDIj, and VDDIp are not short-circuited, so that the probe test shown in the flowchart of FIG. 12 can be performed. Since the inter-power supply protection elements 51 to 56 do not affect the probe test, the enable circuit 61 as shown in FIG. 11 is unnecessary, and the n-channel MOS transistor whose gate electrode is pulled up to a high level so as to be always turned on. Can only be configured.

  Further, as shown in FIG. 3, dedicated power supply terminals 11, 12, and 13 are provided for the first memory array unit 101, the second memory array unit 102, and the peripheral circuit unit 103, respectively, and the power supply voltage for operation is externally supplied. Even if the supply is controlled, the same effect as the above example can be obtained. That is, the first memory cell array unit 101, the second memory cell array unit 103, and the peripheral circuit unit 103 are externally supplied with external power supply voltages VDDi, VDDj, and VDDp through dedicated power supply terminals 11, 12, and 13, respectively. Is to be supplied. The external power supply voltages VDDi, VDDj, and VDDp are supplied to a step-down circuit (not shown), and the internal power supply voltages VDDIi, VDDIj, and VDDIp are obtained by being stepped down there.

  FIG. 4 shows the relationship between the measurement area and the applied power supply voltage.

  When the jig 134 corresponding to the measurement of the first memory cell array unit 101 is set, the power supply voltages VDDp and VDDi are supplied to the SRAM 141 through the jig 134, whereby the peripheral circuit unit 103 and the first One memory cell array unit 101 is operated, and a probe test is performed on the first memory cell array unit 101. This probe test includes a test of whether or not predetermined pattern data is written and read by the tester 131 and is correctly performed. At this time, since the power supply voltage VDDj is not supplied to the SRAM 141, the probe test of the second memory cell array unit 102 is not performed. After the probe test for the first memory cell array unit 101 is completed, the probe test jig 134 for the second memory cell array unit 102 is replaced, and the power supply voltages VDDp and VDDj are supplied to the SRAM 141 this time. As a result, the peripheral circuit unit 103 and the second memory cell array unit 102 are operated, and a probe test is performed on the second memory cell array unit 102. At this time, since the power supply voltage VDDi is not supplied to the SRAM 141, the probe test of the first memory cell array unit 101 is not performed.

  Even in such a configuration, the current supplied from the tester 131 to the SRAM 141 by the probe test of the first memory cell array unit 101 and the second memory cell array unit 102 is different from that of the first memory cell array unit 101 and the second memory cell array unit 102. This can be approximately ½ that when the probe test with the cell array unit 102 is performed simultaneously.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  In the above description, the case where the invention made by the present inventor is applied to the SRAM, which is the field of use behind it, has been described. However, the present invention is not limited to this and is applied to various semiconductor integrated circuits. be able to.

  The present invention can be applied on condition that at least an area to be measured is included.

FIG. 3 is a diagram illustrating a relationship between an SRAM, which is an example of a semiconductor integrated circuit according to the present invention, and a power supply voltage supplied thereto. FIG. 2 is an explanatory diagram of a relationship between a measurement area and an applied power supply voltage in the SRAM shown in FIG. 1. FIG. 2 is an explanatory diagram of a relationship between an SRAM having a configuration different from that shown in FIG. 1 and a power supply voltage supplied thereto. FIG. 4 is an explanatory diagram of a relationship between a measurement area and an applied power supply voltage in the SRAM shown in FIG. 3. FIG. 10 is a diagram illustrating a relationship between another configuration example of the SRAM and a power supply voltage supplied thereto. FIG. 10 is a diagram illustrating a relationship between another configuration example of the SRAM and a power supply voltage supplied thereto. FIG. 10 is a diagram illustrating a relationship between another configuration example of the SRAM and a power supply voltage supplied thereto. It is sectional drawing by which another structural example of the said SRAM is shown. It is sectional drawing by which another structural example of the said SRAM is shown. It is a block diagram of a configuration example of a main part in another configuration example of the SRAM. FIG. 11 is a circuit diagram illustrating a detailed configuration example of a main part in FIG. 10. It is a flowchart about the probe test of the SRAM. It is explanatory drawing of the apparatus used for the probe test of the said SRAM. 2 is an explanatory diagram of the overall layout of the SRAM. FIG. It is a circuit diagram of a configuration example of a step-down circuit included in the SRAM.

Explanation of symbols

11, 12, 13, 31, 31-1 to 31-3 power supply terminal 61-1 to 61-3 power supply terminal dedicated to probe test 101 first memory cell array unit 102 second memory cell array unit 103 peripheral circuit unit 104 selection circuit 105 Control circuit 111-113 Step-down circuit 802 Package substrate 803 Redistribution area 804 Chip

Claims (8)

A semiconductor integrated circuit having a plurality of circuit blocks whose operating power supply paths are separated from each other,
A plurality of step-down circuits provided for each of the circuit blocks, each capable of stepping down a power supply voltage supplied from the outside;
A selection circuit capable of selectively supplying the output voltage of the step-down circuit to the corresponding circuit block. 2. The semiconductor integrated circuit according to claim 1, further comprising a plurality of power supply terminals provided corresponding to the plurality of step-down circuits and for taking in a power supply voltage supplied to each corresponding step-down circuit from the outside. 2. The semiconductor integrated circuit according to claim 1, further comprising a power supply terminal for taking in a common power supply voltage to the plurality of step-down circuits. A semiconductor integrated circuit having a plurality of circuit blocks whose operating power supply paths are separated from each other,
A plurality of step-down circuits provided for each of the circuit blocks, each capable of stepping down a power supply voltage supplied from the outside;
A control circuit capable of controlling the operation of the step-down circuit;
A test power supply voltage supply terminal capable of selectively supplying a power supply voltage to the plurality of circuit blocks in a state where voltage output from the step-down circuit is stopped by the control circuit. Integrated circuit. 5. The semiconductor integrated circuit according to claim 4, further comprising a plurality of power supply terminals provided corresponding to the plurality of step-down circuits and for taking in a power supply voltage supplied to the corresponding step-down circuits from outside. 5. The semiconductor integrated circuit according to claim 4, further comprising a power supply terminal for taking in a common power supply voltage to the plurality of step-down circuits. 7. The semiconductor integrated circuit according to claim 1, wherein a rewiring region is interposed between the semiconductor chip and the package substrate, and power supply wiring is performed using the rewiring region. Including an inter-power protection element provided between the power terminals,
The inter-power supply protection element includes a MOS transistor connected between the power supply terminals,
8. A semiconductor integrated circuit according to claim 1, further comprising an enable circuit capable of conducting the MOS transistor after a probe test.

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