JP4018830B2 - Inspection method of semiconductor wafer - Google Patents

Inspection method of semiconductor wafer Download PDF

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Publication number
JP4018830B2
JP4018830B2 JP37671998A JP37671998A JP4018830B2 JP 4018830 B2 JP4018830 B2 JP 4018830B2 JP 37671998 A JP37671998 A JP 37671998A JP 37671998 A JP37671998 A JP 37671998A JP 4018830 B2 JP4018830 B2 JP 4018830B2
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Prior art keywords
inspection
unit
semiconductor wafer
chip
wiring
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JP2000195912A (en
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悦四 鈴木
重男 池田
俊司 阿部
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Yamaichi Electronics Co Ltd
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Yamaichi Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は多数のＩＣチップを保有する半導体ウエハのバーンイン検査等の検査方法に関する。
【０００２】
【従来の技術】
ウエハバーンイン検査は、例えば特開平７−２３１０１９号公報の図８に示されるように、半導体ウエハと多層配線基板間に多数の接触子を保有するフレキシブル基板を介在し、該フレキシブル基板上の接触子群を介して上記半導体ウエハ上の全ＩＣチップの外部接点たる電極端子群と配線基板上の電極パッド群とを接続し、検査装置本体から与えられる電源電圧及び信号を配線基板を経由し、更に上記電極パッド群と電極端子群を経由して半導体ウエハ上の全ＩＣチップに印加し、バーンイン検査を行なっている。
【０００３】
【発明が解決しようとする課題】
然るに、上記ウエハバーンイン検査において半導体ウエハ上の数百のＩＣチップを効率的に検査するためには、全ＩＣチップに対し一時に上記電源電圧を与えつつ、検査信号を入出力し検査するか、又は全ＩＣチップをグループ分け（群分け）してグループ毎に上記電源電圧を与えつつ検査信号を入出力し検査する必要があるが、この時全ＩＣチップ中、従って各ＩＣチップグループ中にショートＩＣチップが存在すると、このショートＩＣチップに過電流が流れて、他のＩＣチップに正常な電流が流れず、適正な検査を行ない難くする問題を招来する。
【０００４】
加えて検査装置本体から多層配線基板間における配線数が超過密になり、これが上記検査ユニットの技術的難点とされ、実用化を妨げる要因となっている。又検査装置本体から配線基板を経て各ＩＣチップへ至る線路距離が長くなり、検査の高速化を妨げノイズによる外乱が問題となっている。
【０００５】
即ち配線が長くなることにより、その電気容量が大きくなって信号がなまり、信号の高速化ができないことや、信号間の相互干渉や外部ノイズが問題になる。
【０００６】
【課題を解決するための手段】
本発明は上記問題を解決する手段として、半導体ウエハ上の多数のＩＣチップをグループ分けしてグループ毎のＩＣチップ群の検査を分担する単位中継検査ブロックを多数形成し、該各単位中継検査ブロックを介して半導体ウエハを形成している全ＩＣチップに個別に電源電圧を印加して過電流が流れたショートＩＣチップを特定する予備検査工程を実行する。
再述すると、上記グループ毎のＩＣチップ群の検査を分担する電子回路部品を有する単位中継検査ブロックを多数形成し、該各単位中継検査ブロックを上記半導体ウエハと検査装置本体と接続されるマザー配線基板との間に積層して並列接続し、該検査装置本体から該マザー配線基板と各単位中継検査ブロックを介して半導体ウエハを形成している全ＩＣチップに個別に電源電圧を印加し、上記各単位中継検査ブロックが上記マザー配線基板を介して過電流が流れたショートＩＣチップを特定するための異常信号を上記検査装置本体へ出力し同本体においてショートＩＣチップを記憶し特定する予備検査工程を実行する。
【０００７】
然る後該ショートＩＣチップを除外したＩＣチップに上記単位中継検査ブロックを介し、電源電圧を印加しつつ検査信号を入出力しバーンイン検査等の検査を行なう検査方法を提供するものである。
【０００８】
上記構成によって、ウエハバーンイン検査等の検査におけるショートＩＣチップを適切に除外して、ウエハレベルでのバーンイン検査の信頼性を向上した。
【０００９】
又各単位配線回路基板と各単位両面多点接続板とから成る各単位中継検査ブロックにてグループ分けされた各ＩＣチップ群への配線及び検査を分担するので、検査装置本体からの配線数は各単位中継検査ブロックに接続する最小限の配線で足り、検査装置本体から半導体ウエハ上の全ＩＣチップへの配線仕様を簡潔且つ合理的に設計でき、ひいては検査高速化や信頼性向上を図ることができる。
【００１０】
又上記検査を分担する単位中継検査ブロックを半導体ウエハ上への全ＩＣチップと極接近した距離に設置し検査を行えるので、ノイズ等の外乱要因を抑止し、検査の信頼性を一層向上できる。
【００１１】
【発明の実施の形態】
図１は半導体ウエハ１を示し、該半導体ウエハ１は平面設置された数百のＩＣチップ２を保有し、各ＩＣチップ２は外部接点たる数十〜数百の電極端子３を有し、従って数千〜数万の電極端子３が半導体ウエハ１の表面に配置されている。
【００１２】
他方上記半導体ウエハ１上の全ＩＣチップを複数群にグループ分けしてグループ毎の検査作業を分担する単位配線回路基板５を複数単位用意し、この各単位配線回路基板５と、半導体ウエハ１上のグループ分けされたＩＣチップ２との接続媒体となる単位両面多点接続板６を複数単位用意する。
【００１３】
上記単位配線回路基板５と単位両面多点接続板６とは一体積層体にして単位中継検査ブロック７を形成し、該単位中継検査ブロック７にて後述の単位配線分岐回路を形成する。
【００１４】
例えば両者５，６は接着剤にて貼り合わせ一体積層体にする。上記単位中継検査ブロック７を形成する単位配線回路基板５は多層配線回路基板から成り、その一方表面に検査装置本体８と協働して検査を分担する多数のバッファＩＣ９等の電子部品を搭載し、該バッファＩＣ９等の電子部品を上記単位両面多点接続板６を介して半導体ウエハ１上のグループ分けされた一群のＩＣチップ２の電極端子３に接続する配線パターン１０とバッファＩＣ９等の電子部品を検査装置本体８へ接続するための配線パターン１１を有する。
【００１５】
他方単位中継検査ブロック７を形成する単位両面多点接続板６は接続板の厚み方向において圧縮弾性を有する多数の接触子１２を保有し、各接触子１２の一端を半導体ウエハ１のグループ分けされた一群のＩＣチップ２の電極端子３に加圧接触する。接触子１２の他端は単位配線回路基板５のバッファＩＣ９の搭載面とは反対側の表面に配された電極パッド１４に加圧接触、或いは接合されている。
【００１６】
該電極パッド１４は配線パターン１０の一端部に形成され、同配線パターン１０の一部配線はその他端部において電極パッド１５が形成されており、この電極パッド１５はバッファＩＣ９等の電子部品の下面に配された電極端子に融着接続している。
【００１７】
又バッファＩＣ９等で構成された電子回路部品は必要に応じて単位配線回路基板５に形成された配線パターン１１によりマザー配線基板１６との接続用電極パッドに接続されている。
【００１８】
これによってバッファＩＣ９等の電子回路部品を配線パターン１０と接触子１２を介して半導体ウエハ１上のグループ分けされた一群のＩＣチップ２に接続する。又配線パターン１０の一部配線は直接マザー配線基板１６との接続用電極パッドに導通している。
【００１９】
即ち半導体ウエハ１と各単位配線回路基板５間に各単位両面多点接続板６を介在せしめ、両者１，５を接続する。
【００２０】
よって各単位中継検査ブロック７を半導体ウエハ１上のグループ分けされた各ＩＣチップ２群に接続する。
【００２１】
例えば半導体ウエハ１上のＩＣチップ２が２００個であると仮定すると、例えばこれを２０個づつの群にグループ分けし、この各グループの検査を上記各単位検査ブロック７が分担する。
【００２２】
換言すると各単位配線回路基板５は上記半導体ウエハ１上の全ＩＣチップ２中のグループ分けされたＩＣチップ群の検査を分担する。上記単位配線回路基板５と単位両面多点接続板６と半導体ウエハ１とは上記順序で重ねられ、三者間の電気的接続が図られる。
【００２３】
単位配線回路基板５と単位両面多点接続板６とを重ね貼り合せる等して一体積層体にし単位中継検査ブロック７を形成する場合には、接触子１２と電極パッド１４との加圧接触状態が事前に形成されており、この単位中継検査ブロック７を半導体ウエハ１に重ね加圧することによって接触子１２と電極端子３との加圧接触が得られる。
【００２４】
更に図２Ａに示すように、検査装置本体８と上記各単位中継検査ブロック７間を接続する、換言すると検査装置本体８と各単位配線回路基板５間の接続手段となるマザー配線基板１６を用意する。
【００２５】
このマザー配線基板１６は温度に対し収縮が少なく機械的強度の高いリジットなベース板１７の表面に配線層１８を一体に層着した複合板である。このリジットベース板１７はセラミック板、ガラス板、金属板等から成る。
【００２６】
上記マザー配線基板１６の配線層１８の表面に上記各単位中継検査ブロック７の各単位配線回路基板５の表面を重ね、図３に示すように、マザー配線基板１６に対し各単位中継検査ブロック７を、即ち各単位配線回路基板５を並列に接続する。
【００２７】
図２Ｂに示すように、上記マザー配線基板１６はその端部に配線層１８の端部に形成された多数の外部電極端子１９を有し、この外部電極端子１９を以って検査装置本体８と接続される。
【００２８】
上記各単位配線回路基板５は上記バッファＩＣ９やその他の電子部品を搭載した面域を除く表面において、例えば回路基板５の端部表面においてマザー配線基板１６に直接又は間接に貼り合わせる。
【００２９】
好ましくは上記各単位中継検査ブロック７の単位配線回路基板５の周囲表面を上記マザー配線基板１６の配線層１８に重ね一体積層体とする。即ち接着を介しての貼り合せ体か、螺子を介しての貼り合せ体にする。そして、単位配線回路基板５とマザー配線基板１６間には、一定の空間２０を設定し、この空間２０内にバッファＩＣ９を存置せしめる。
【００３０】
例えば単位配線回路基板５の中間部領域に上記空間２０を形成し、その周縁部表面をマザー配線基板１６の表面に貼り合せる。この貼り合せ面域にマザー配線基板１６の配線層１８と単位中継検査ブロック７の単位配線回路基板５間を接続する接触子２１を設ける。
【００３１】
即ち、単位配線回路基板５のマザー配線基板１６に対する重ね合せ面域に、基板厚み方向に圧縮弾性を有する上記接触子２１を配する。詳述すると、多数の接触子２１を保有する両面多点接続板２２を形成し、この接続板２２を上記マザー配線基板１６の配線層１８と、単位中継検査ブロック７の単位配線回路基板５との間に介在し重ね合せて、上記接触子２１による接触を図る。上記接続板２２はバッファＩＣ９等の電子部品の逃げを形成する窓を有し、この窓により上記空間２０を形成する。
【００３２】
上記接触子２１はその一端を上記配線層１８の電極パッドに加圧接触し、他端を上記単位配線回路基板５の配線パターン１１の端部に形成した電極パッドに加圧接触する。
【００３３】
これによって検査装置本体８と各単位中継検査ブロック７の各単位配線回路基板５（バッファＩＣ９等の電子回路部品）とは接触子２１と配線パターン１１を介して接続される。
【００３４】
以上のように、マザー配線基板１６と各単位中継検査ブロック７、即ちマザー配線基板１６と各単位両面多点接続板２２と各単位配線回路基板５と各単位両面多点接続板６とはこの順序で一体に重ね積層されて検査ユニットを形成する。
【００３５】
各単位中継検査ブロック７はマザー配線基板１６の表面に縦横に整列して且つ密集して並設される。
【００３６】
上記検査ユニットを準備して置くことにより、この検査ユニットを半導体ウエハ１に重ねることによってバーンイン検査等を繰り返し効率的に実行できる。
【００３７】
図３に示すように、検査装置本体８からのチップセレクト信号により、セレクトされた半導体ウエハ１上の全てのＩＣチップ２に対し、検査装置本体８からの電源電圧を個別に印加する。
【００３８】
この電源電圧はマザー配線基板１６と各単位中継検査ブロック７を経由して各ＩＣチップ２に個別に印加する。
【００３９】
上記電源電圧印加によって各ＩＣチップ２へ流入する電流が正常かどうかをチェックし、即ち過電流が流れるショートＩＣチップをチェックし、単位中継検査ブロック７及びマザー配線基板１６を介して異常信号を検査装置本体８に出力し、同本体８においてこのショートＩＣチップを記憶する。即ちショートＩＣチップを特定する。
【００４０】
以上のショートＩＣチップの特定を半導体ウエハ１上の全てのＩＣチップ２に対し行なう。ショートＩＣチップを特定し、爾後のバーンイン検査から除去する予備検査工程を設置し、この予備検査工程を経た後、上記ショートＩＣチップを除いた全ＩＣチップに改めて電源電圧を印加しつつ、検査信号の入出力を行なう。
【００４１】
この電源電圧及び検査信号は検査装置本体８からマザー配線基板１６及びこれに並列接続された各単位検査ブロック７を経由して各ＩＣチップ２に与えられる。 検査装置本体８はＩＣチップ群のグループ選択、即ち単位中継検査ブロック７の選択を指令し、且つチップセレクト信号によりグループ内のＩＣチップ２へ検査信号の入力を行なうか、同出力を行なうかを設定する。
【００４２】
上記各ＩＣチップ２への検査信号を各ＩＣチップ２のどのアドレスに入力（書込み）し、且つ出力（読み出し）するかは、検査装置本体８から指令されるアドレス信号を配線基板１６と単位中継検査ブロック７、即ち単位配線回路基板５を経由して各ＩＣチップ２に印加し、該当するアドレスを開き行なう。
【００４３】
上記各ＩＣチップ２からの出力信号は検査装置本体８に記録し、バーンイン検査等の検査を完了する。
【００４４】
上記の如くＩＣチップ２の近くに電子回路を形成できることから、例えばその電源入力部近くにコンデンサーを設ける、或いは同出力部に抵抗を設けることができ、検査の高速化や高信頼性を確保できる。
【００４５】
尚、上記バーンイン検査ユニットの形成にあたり、半導体ウエハ１と各単位両面接続板６間、又は単位配線回路基板５と各単位両面接続板２２間、又はマザー配線基板１６と各単位両面接続板２２間に、異方性導電ゴムシートの如き導電エラストマーを介在し、これらを上記検査ユニットとして一体に重ね付けすることができる。
【００４６】
上記単位配線回路基板５により形成される電子回路は、被検査半導体ウエハの種類やその検査内容によって様々に構築でき、又上記回路基板５は複数の回路基板で構成することができる。
【００４７】
【発明の効果】
本発明によれば、上記予備検査工程を設置することにより、半導体ウエハ上のショートＩＣチップを特定し、このショートＩＣチップを除外したバーンイン検査を行なうことができ、これによりバーンイン検査時にショートＩＣチップに過電流が流れて他のＩＣチップには正常な電流が流れず、適正な検査を行ない難くする問題を解決し、ウエハレベルでのバーンイン検査の信頼性を向上し、その実施を促進することができる。
【００４８】
又各単位中継検査ブロックにてグループ分けされた各ＩＣチップ群への配線及び検査を分担するので、検査装置本体と各単位中継ブロックを並列接続する最小限の配線で足り、検査装置本体から半導体ウエハ上の全ＩＣチップへの配線仕様を簡潔且つ合理的に設計でき、ひいては検査の信頼性向上を図ることができる。
【００４９】
更に単位両面多点接続板と半導体ウエハとの熱膨張差による接触子の位置ずれが、ブロック毎に分割することで緩和することができる。又ブロック毎にしたことで、メンテナンスが容易となる。
【００５０】
又上記検査を分担する単位中継検査ブロックを半導体ウエハ上への全ＩＣチップと極接近した距離に設置し検査を行えるので、ノイズ等の外乱要因を抑止し、検査の信頼性を一層向上できると同時に、高速検査を可能にする。
【図面の簡単な説明】
【図１】半導体ウエハを概示する平面図。
【図２】Ａは半導体ウエハの検査ユニットを概示する要部拡大断面図、Ｂはこの検査ユニットの検査装置本体との接続部を摘示する要部拡大断面図。
【図３】上記検査ユニットにより形成される検査回路を概示する図。
【符号の説明】
１ 半導体ウエハ
２ ＩＣチップ
３ 電極端子
５ 単位配線回路基板
６ 単位両面多点接続板
７ 単位中継検査ブロック
８ 検査装置本体
９ バッファＩＣ
１０ 配線パターン
１１ 配線パターン
１２ 接触子
１４ 電極パッド
１５ 電極パッド
１６ マザー配線基板
１７ リジットベース板
１８ 配線層
１９ 外部電極端子
２０ 空間
２１ 接触子
２２ 単位両面多点接続板[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inspection method such as burn-in inspection of a semiconductor wafer having a large number of IC chips.
[0002]
[Prior art]
In the wafer burn-in inspection, for example, as shown in FIG. 8 of Japanese Patent Application Laid-Open No. 7-23310, a flexible substrate having a large number of contacts is interposed between a semiconductor wafer and a multilayer wiring substrate, and the contacts on the flexible substrate are interposed. A group of electrode terminals that are external contacts of all the IC chips on the semiconductor wafer and a group of electrode pads on the wiring board through the group, and a power supply voltage and a signal supplied from the inspection apparatus main body are routed through the wiring board; A burn-in inspection is performed by applying to all IC chips on the semiconductor wafer via the electrode pad group and the electrode terminal group.
[0003]
[Problems to be solved by the invention]
However, in order to efficiently inspect hundreds of IC chips on the semiconductor wafer in the wafer burn-in inspection, the above-mentioned power supply voltage is applied to all IC chips at the same time, and inspection signals are input and output, Alternatively, it is necessary to divide all the IC chips into groups (grouping) and to input and output the inspection signal while applying the power supply voltage for each group. At this time, it is necessary to short-circuit in all the IC chips and therefore in each IC chip group. If an IC chip exists, an overcurrent flows through the short IC chip, and a normal current does not flow through other IC chips, causing a problem that it is difficult to perform an appropriate inspection.
[0004]
In addition, the number of wires between the inspection apparatus main body and the multilayer wiring board becomes excessively dense, which is regarded as a technical difficulty of the inspection unit and hinders practical use. Further, the line distance from the inspection apparatus main body to each IC chip through the wiring board becomes long, which hinders the speeding up of the inspection and causes disturbance due to noise.
[0005]
That is, as the wiring becomes longer, the electric capacity becomes larger and the signal becomes dull, which makes it impossible to increase the speed of the signal, mutual interference between signals, and external noise.
[0006]
[Means for Solving the Problems]
As a means for solving the above problems, the present invention forms a large number of unit relay inspection blocks that divide a large number of IC chips on a semiconductor wafer into groups and share the inspection of the IC chip group for each group. A pre-inspection step is performed in which the power supply voltage is individually applied to all the IC chips forming the semiconductor wafer via the pin to identify the short IC chip in which the overcurrent flows.
In other words, a large number of unit relay inspection blocks having electronic circuit parts that share the inspection of the IC chip group for each group are formed, and each unit relay inspection block is connected to the semiconductor wafer and the inspection apparatus main body. Laminated between and connected in parallel to the substrate, the power supply voltage is individually applied from the inspection apparatus body to all the IC chips forming the semiconductor wafer via the mother wiring substrate and each unit relay inspection block, Preliminary inspection process in which each unit relay inspection block outputs an abnormal signal for identifying a short IC chip in which an overcurrent has passed through the mother wiring board to the inspection apparatus body, and stores and identifies the short IC chip in the body. Execute.
[0007]
Thereafter, an inspection method for performing an inspection such as a burn-in inspection by inputting / outputting an inspection signal while applying a power supply voltage to the IC chip excluding the short IC chip through the unit relay inspection block is provided.
[0008]
With the above configuration, the reliability of burn-in inspection at the wafer level is improved by appropriately excluding short IC chips in inspection such as wafer burn-in inspection.
[0009]
Also, since each unit relay inspection block consisting of each unit wiring circuit board and each unit double-sided multipoint connection board shares the wiring and inspection to each IC chip group, the number of wirings from the inspection device body is The minimum wiring to connect to each unit relay inspection block is sufficient, and the wiring specifications from the inspection device body to all IC chips on the semiconductor wafer can be designed concisely and rationally. As a result, inspection speed and reliability can be improved. Can do.
[0010]
In addition, since the unit relay inspection block for sharing the inspection can be installed at a distance that is in close proximity to all the IC chips on the semiconductor wafer, the disturbance factor such as noise can be suppressed and the inspection reliability can be further improved.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a semiconductor wafer 1, which has several hundreds of IC chips 2 mounted on a plane, and each IC chip 2 has several tens to several hundreds of electrode terminals 3 as external contacts. Thousands to tens of thousands of electrode terminals 3 are arranged on the surface of the semiconductor wafer 1.
[0012]
On the other hand, all the IC chips on the semiconductor wafer 1 are grouped into a plurality of groups, and a plurality of unit wiring circuit boards 5 for sharing the inspection work for each group are prepared. A plurality of unit double-sided multipoint connection plates 6 serving as connection media with the grouped IC chips 2 are prepared.
[0013]
The unit wiring circuit board 5 and the unit double-sided multipoint connection plate 6 are integrally laminated to form a unit relay inspection block 7, and the unit relay inspection block 7 forms a unit wiring branch circuit described later.
[0014]
For example, both 5 and 6 are bonded together with an adhesive to form an integral laminate. The unit wiring circuit board 5 that forms the unit relay inspection block 7 is composed of a multilayer wiring circuit board, and on one surface thereof, electronic components such as a plurality of buffer ICs 9 that share the inspection in cooperation with the inspection apparatus body 8 are mounted. The wiring pattern 10 for connecting the electronic components such as the buffer IC 9 to the electrode terminals 3 of the grouped IC chips 2 on the semiconductor wafer 1 via the unit double-sided multipoint connection plate 6 and the electronic such as the buffer IC 9 A wiring pattern 11 for connecting the component to the inspection apparatus main body 8 is provided.
[0015]
On the other hand, the unit double-sided multipoint connection plate 6 forming the unit relay inspection block 7 has a large number of contacts 12 having compression elasticity in the thickness direction of the connection plate, and one end of each contact 12 is grouped into the semiconductor wafer 1. The electrode terminals 3 of the group of IC chips 2 are brought into pressure contact. The other end of the contact 12 is pressed or bonded to an electrode pad 14 disposed on the surface of the unit wiring circuit board 5 opposite to the mounting surface of the buffer IC 9.
[0016]
The electrode pad 14 is formed at one end of the wiring pattern 10, and an electrode pad 15 is formed at the other end of the partial wiring of the wiring pattern 10, and this electrode pad 15 is the lower surface of an electronic component such as the buffer IC 9. Are fused and connected to the electrode terminals.
[0017]
The electronic circuit components constituted by the buffer IC 9 and the like are connected to the electrode pads for connection with the mother wiring board 16 by wiring patterns 11 formed on the unit wiring circuit board 5 as necessary.
[0018]
Thus, electronic circuit components such as the buffer IC 9 are connected to the grouped IC chips 2 on the semiconductor wafer 1 via the wiring pattern 10 and the contact 12. A part of the wiring pattern 10 is directly connected to the electrode pad for connection to the mother wiring board 16.
[0019]
That is, each unit double-sided multipoint connection plate 6 is interposed between the semiconductor wafer 1 and each unit wiring circuit board 5, and both 1 and 5 are connected.
[0020]
Therefore, each unit relay inspection block 7 is connected to each grouped IC chip 2 group on the semiconductor wafer 1.
[0021]
For example, assuming that there are 200 IC chips 2 on the semiconductor wafer 1, for example, they are grouped into 20 groups, and the unit inspection blocks 7 share the inspection of each group.
[0022]
In other words, each unit wiring circuit board 5 shares the inspection of the grouped IC chips in all the IC chips 2 on the semiconductor wafer 1. The unit wiring circuit board 5, the unit double-sided multipoint connection plate 6 and the semiconductor wafer 1 are stacked in the above order, and electrical connection between the three is achieved.
[0023]
When the unit relay inspection block 7 is formed as an integral laminated body by overlapping the unit wiring circuit board 5 and the unit double-sided multipoint connection plate 6 or the like, the pressure contact state between the contact 12 and the electrode pad 14 Is formed in advance, and the unit 12 inspecting block 7 is overlapped and pressed on the semiconductor wafer 1 to obtain a pressure contact between the contact 12 and the electrode terminal 3.
[0024]
Further, as shown in FIG. 2A, a mother wiring board 16 is prepared for connecting the inspection apparatus main body 8 and each unit relay inspection block 7, in other words, connecting means between the inspection apparatus main body 8 and each unit wiring circuit board 5. To do.
[0025]
The mother wiring board 16 is a composite board in which a wiring layer 18 is integrally layered on the surface of a rigid base board 17 that has little mechanical shrinkage and high mechanical strength. The rigid base plate 17 is made of a ceramic plate, a glass plate, a metal plate, or the like.
[0026]
The surface of each unit wiring circuit board 5 of each unit relay inspection block 7 is overlaid on the surface of the wiring layer 18 of the mother wiring board 16, and each unit relay inspection block 7 is placed on the mother wiring board 16 as shown in FIG. That is, the unit wiring circuit boards 5 are connected in parallel.
[0027]
As shown in FIG. 2B, the mother wiring board 16 has a large number of external electrode terminals 19 formed at the end portions of the wiring layer 18 at the end portions thereof, and the inspection apparatus body 8 is provided with the external electrode terminals 19. Connected.
[0028]
Each unit wiring circuit board 5 is bonded directly or indirectly to the mother wiring board 16 on the surface excluding the surface area on which the buffer IC 9 and other electronic components are mounted, for example, on the end surface of the circuit board 5.
[0029]
Preferably, the peripheral surface of the unit wiring circuit board 5 of each unit relay inspection block 7 is overlapped with the wiring layer 18 of the mother wiring board 16 to form an integrated laminate. That is, a bonded body through bonding or a bonded body through screws is used. A fixed space 20 is set between the unit wiring circuit board 5 and the mother wiring board 16, and the buffer IC 9 is placed in this space 20.
[0030]
For example, the space 20 is formed in the intermediate region of the unit wiring circuit board 5, and the peripheral surface thereof is bonded to the surface of the mother wiring substrate 16. A contact 21 for connecting the wiring layer 18 of the mother wiring board 16 and the unit wiring circuit board 5 of the unit relay inspection block 7 is provided in the bonding surface area.
[0031]
That is, the contact 21 having compressive elasticity in the substrate thickness direction is disposed in the overlapping surface area of the unit wiring circuit board 5 with respect to the mother wiring board 16. More specifically, a double-sided multipoint connection board 22 having a large number of contacts 21 is formed, and the connection board 22 is connected to the wiring layer 18 of the mother wiring board 16 and the unit wiring circuit board 5 of the unit relay inspection block 7. The contact 21 is contacted and overlapped with each other. The connection plate 22 has a window that forms an escape for an electronic component such as the buffer IC 9, and the space 20 is formed by the window.
[0032]
One end of the contact 21 is in pressure contact with the electrode pad of the wiring layer 18, and the other end is in pressure contact with an electrode pad formed at the end of the wiring pattern 11 of the unit wiring circuit board 5.
[0033]
As a result, the inspection apparatus main body 8 and each unit wiring circuit board 5 (electronic circuit components such as the buffer IC 9) of each unit relay inspection block 7 are connected via the contact 21 and the wiring pattern 11.
[0034]
As described above, the mother wiring board 16 and each unit relay inspection block 7, that is, the mother wiring board 16, each unit double-sided multipoint connection board 22, each unit wiring circuit board 5, and each unit doublesided multipoint connection board 6 The inspection unit is formed by stacking together in order.
[0035]
The unit relay inspection blocks 7 are arranged vertically and horizontally on the surface of the mother wiring board 16 and closely arranged.
[0036]
By preparing and placing the above-described inspection unit, burn-in inspection and the like can be repeatedly and efficiently executed by overlapping this inspection unit on the semiconductor wafer 1.
[0037]
As shown in FIG. 3, the power supply voltage from the inspection apparatus body 8 is individually applied to all the IC chips 2 on the selected semiconductor wafer 1 by the chip select signal from the inspection apparatus body 8.
[0038]
This power supply voltage is individually applied to each IC chip 2 via the mother wiring board 16 and each unit relay inspection block 7.
[0039]
Check whether the current flowing into each IC chip 2 by applying the power supply voltage is normal, that is, check the short IC chip in which overcurrent flows, and check the abnormal signal via the unit relay inspection block 7 and the mother wiring board 16 The data is output to the apparatus main body 8 and the short IC chip is stored in the main body 8. That is, the short IC chip is specified.
[0040]
The above short IC chips are specified for all the IC chips 2 on the semiconductor wafer 1. A pre-inspection process that identifies short IC chips and removes them after burn-in inspection is installed. After this pre-inspection process, a test signal is applied to all IC chips except for the short IC chip while applying a power supply voltage again. I / O is performed.
[0041]
The power supply voltage and the inspection signal are given from the inspection apparatus main body 8 to each IC chip 2 via the mother wiring board 16 and each unit inspection block 7 connected in parallel thereto. The inspection apparatus main body 8 commands the group selection of the IC chip group, that is, the selection of the unit relay inspection block 7, and whether the inspection signal is input to the IC chip 2 in the group by the chip select signal or the same output is performed. Set.
[0042]
To which address of each IC chip 2 the inspection signal to each IC chip 2 is input (written) and output (read), the address signal commanded from the inspection apparatus body 8 is relayed to the wiring board 16 and unit relay. The voltage is applied to each IC chip 2 via the inspection block 7, that is, the unit wiring circuit board 5, and the corresponding address is opened.
[0043]
The output signal from each IC chip 2 is recorded in the inspection apparatus main body 8 to complete inspection such as burn-in inspection.
[0044]
Since an electronic circuit can be formed near the IC chip 2 as described above, for example, a capacitor can be provided near the power input portion, or a resistor can be provided at the output portion, so that high-speed inspection and high reliability can be ensured. .
[0045]
In forming the burn-in inspection unit, between the semiconductor wafer 1 and each unit double-sided connection board 6, or between the unit wiring circuit board 5 and each unit double-sided connection board 22, or between the mother wiring board 16 and each unit double-sided connection board 22. Further, a conductive elastomer such as an anisotropic conductive rubber sheet is interposed, and these can be integrally stacked as the inspection unit.
[0046]
The electronic circuit formed by the unit wiring circuit board 5 can be variously constructed according to the type of the semiconductor wafer to be inspected and the contents of the inspection, and the circuit board 5 can be composed of a plurality of circuit boards.
[0047]
【The invention's effect】
According to the present invention, by setting the preliminary inspection step, it is possible to specify a short IC chip on the semiconductor wafer and perform a burn-in inspection excluding the short IC chip, and thereby the short IC chip during the burn-in inspection. To solve the problem that normal current does not flow to other IC chips due to excessive current and makes it difficult to perform proper inspection, improve the reliability of burn-in inspection at the wafer level, and promote its implementation Can do.
[0048]
Also, since the wiring and inspection to each IC chip group divided into groups by each unit relay inspection block are shared, the minimum wiring that connects the inspection apparatus main unit and each unit relay block in parallel is sufficient, and the inspection apparatus main body to the semiconductor Wiring specifications to all the IC chips on the wafer can be designed concisely and rationally, and as a result, the reliability of inspection can be improved.
[0049]
Further, the positional deviation of the contact due to the thermal expansion difference between the unit double-sided multipoint connection plate and the semiconductor wafer can be alleviated by dividing each block. In addition, the maintenance is facilitated by performing each block.
[0050]
In addition, since the unit relay inspection block that shares the above inspection can be installed at a distance that is in close proximity to all the IC chips on the semiconductor wafer, it is possible to suppress disturbance factors such as noise and further improve the inspection reliability. At the same time, it enables high-speed inspection.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a semiconductor wafer.
FIG. 2A is an enlarged cross-sectional view of a main part schematically showing an inspection unit of a semiconductor wafer, and B is an enlarged cross-sectional view of a main part showing a connection part of the inspection unit with an inspection apparatus main body.
FIG. 3 is a diagram schematically showing an inspection circuit formed by the inspection unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 IC chip 3 Electrode terminal 5 Unit wiring circuit board 6 Unit double-sided multipoint connection board 7 Unit relay inspection block 8 Inspection apparatus main body 9 Buffer IC
DESCRIPTION OF SYMBOLS 10 Wiring pattern 11 Wiring pattern 12 Contactor 14 Electrode pad 15 Electrode pad 16 Mother wiring board 17 Rigid base board 18 Wiring layer 19 External electrode terminal 20 Space 21 Contact 22 Unit double-sided multipoint connection board

Claims (1)

半導体ウエハ上の多数のＩＣチップをグループ分けしてグループ毎のＩＣチップ群の検査を分担する電子回路部品を有する単位中継検査ブロックを多数形成し、該各単位中継検査ブロックを上記半導体ウエハと検査装置本体と接続されるマザー配線基板との間に積層して並列接続し、該検査装置本体から該マザー配線基板と各単位中継検査ブロックを介して半導体ウエハを形成している全ＩＣチップに個別に電源電圧を印加し、上記各単位中継検査ブロックが上記マザー配線基板を介して過電流が流れたショートＩＣチップを特定するための異常信号を上記検査装置本体へ出力し同本体においてショートＩＣチップを記憶し特定する予備検査工程を実行し、然る後該ショートＩＣチップを除外した全ＩＣチップに上記マザー配線基板と各単位中継検査ブロックを介し電源電圧を印加しつつ検査信号を入出力しバーンイン検査等の検査を行なうことを特徴とする半導体ウエハの検査方法。A large number of unit relay inspection blocks having electronic circuit parts that share the inspection of the IC chip group for each group are formed by grouping a large number of IC chips on the semiconductor wafer, and each unit relay inspection block is inspected with the semiconductor wafer. Stacked in parallel between the mother wiring board connected to the device body and connected in parallel to each IC chip forming the semiconductor wafer from the inspection device body via the mother wiring substrate and each unit relay inspection block A power supply voltage is applied to each unit relay, and each unit relay inspection block outputs an abnormal signal to the inspection apparatus main body to identify a short IC chip in which an overcurrent has passed through the mother wiring board. stores that perform particular pre inspection process, after which the short IC chip total IC chip on the mother circuit board and each unit excluding the Method of inspecting a semiconductor wafer, characterized by inspecting the input and output test signals while applying a power supply voltage via a relay test blocks such a burn-in test.
JP37671998A 1998-12-27 1998-12-27 Inspection method of semiconductor wafer Expired - Fee Related JP4018830B2 (en)

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