JP4004838B2 - Display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device that prevents malfunction of a data drive circuit or a scan drive circuit due to a delay of a level shifter circuit of a data drive start signal or a scan drive start signal input to a data drive circuit or a scan drive circuit.
[0002]
[Prior art]
A matrix type display device is a device that displays a large number of signal lines in a row direction and a column direction with respect to a display element, and displays images such as characters, symbols, and figures on the display element by driving the signal lines. .
[0003]
As the matrix display device, an FPD (flat panel display) such as an LCD (liquid crystal display), a PDP (plasma display panel), an EL (electroluminescence) display, or an FED (field emission display) is used. FPD has been used in various display devices in recent years because it can be made thinner and lighter than a conventional CRT (cathode ray tube).
[0004]
FIG. 7 is a block diagram showing a schematic configuration of a conventional matrix type display device. The matrix display device 100 includes a data signal line SL parallel to the column direction in the display unit. _m A large number of (1 ≦ m ≦ M) are arranged in the row direction, and the scanning signal lines GL are parallel to the row direction. _n Many (1 ≦ n ≦ N) are arranged in the column direction, and a display element 102 is provided via a switching element 101 at each intersection of the scanning signal line GL and the data signal line SL. Data signal line SL ₁ ~ SL _M Is connected to the data driving circuit 103 and the scanning signal line GL ₁ ~ GL _N Are connected to the scan driving circuit 104.
[0005]
In the matrix display device 100, the data driving circuit 103 includes data operation clock signals SCK and SCKB for driving the data driving circuit 103, a data driving start signal SSP for starting driving, and the data driving. Initialization signal RES and data signal line SL for initializing the circuit 103 ₁ ~ SL _M The video signal to be output is input.
[0006]
The scan driving circuit 104 initializes the scanning operation clock signals GCK1 and GCK2 for driving the scan driving circuit 104, the scan driving start signal GSP for starting driving, and the scan driving circuit 104. The initialization signal RES is input.
[0007]
The above signals, that is, SCK, SCKB, SSP, GCK1, GCK2, GSP, and RES are level-shifted by the level shifter circuit 105 and then input to the data driving circuit 103 and the scanning driving circuit 104. The reason why the level shifter circuit 105 is required is as follows.
[0008]
Input signals SCK, SCKB, SSP, GCK1, GCK2, GSP, and RES input to the matrix display device 100 are usually generated by an IC outside the matrix display device. For this reason, the voltage of these input signals is the same as the operating voltage of the IC at the time of input to the matrix display device 100.
[0009]
Further, the operating voltage of the IC is decreasing year by year, and even if an input signal that is a low voltage as it is is input to the data driving circuit 103 or the scanning driving circuit 104, these driving circuits do not operate. Therefore, each input signal input to the data driving circuit 103 and the scanning driving circuit 104 needs to be level-shifted by the level shifter circuit 105 to the operating voltages of the data driving circuit 103 and the scanning driving circuit 104.
[0010]
The configuration of the level shifter circuit 105 is shown in FIG. Each input signal input to the level shifter circuit 105 is level-shifted by each level shifter (RS) 106. Here, in order to distinguish the level-shifted signal from the signal before the level shift, “Z” is added to the end of the signal name before the level shift.
[0011]
The configuration of the level shifter 106 is shown in FIG. Each level shifter 106 includes P-channel transistors 201 and 202, N-channel transistors 203 and 204, and inverters 205 and 206. The output signal OUT of the level shifter 106 is a signal obtained by level-shifting the input signal IN of the level shifter 106, and the input voltages VDD and VSS become the high-side operating voltage and the low-side operating voltage of the data driving circuit 103 and the scan driving circuit 104. Voltage.
[0012]
As shown in FIG. 10, in the circuit operation in each level shifter 106 having the configuration shown in FIG. 9, the output signal OUT is VSS when the input signal IN is Low, and the output signal OUT is VDD when the input signal IN is High. However, there is a delay between the change of the input signal IN and the change of the output signal OUT.
[0013]
Next, the configuration of the data driving circuit 103 is shown in FIG. The data driving circuit 103 is an (M + 1) -stage D-type flip-flop DFF _m (1 ≦ m ≦ M + 1), M-stage AND gate AND _m (1 ≦ m ≦ M) and an M-stage switch 301.
[0014]
Each D flip-flop DFF _m The data input clock signal SCCKZ is input to the clock input terminal CK at the odd-numbered stage, and the clock signal SCKBZ is input to the even-numbered stage. The clock signal SCKBZ is an inverted signal of the clock signal SCCKZ. Each D-type flip-flop DFF _m The data drive start signal SSP is input to the data input terminal D in the first stage, and the output SQ of the D flip-flop in the previous stage is input in the second stage and thereafter. _m-1 Is entered.
[0015]
In addition, each D-type flip-flop DFF _m The initialization signal RESZ input to the reset terminal RES of the D-type flip-flops DFF of all the stages when the power is turned on _m Is a signal for initializing each D-type flip-flop DFF _m Is initialized, the output SQ _m Is Low.
[0016]
M-th AND gate AND _m The two systems of input terminals A and B have an m-th stage D-type flip-flop DFF. _m And the (m + 1) th stage D-type flip-flop DFF _{m + 1} The output signal at is input. Further, the mth stage switch 301 includes an mth stage AND gate AND. _m Output Y at _m Is input and output Y _m The switch 301 is turned on when is high.
[0017]
The data driving circuit 103 configured as described above has the data V as data operation clocks SCKZ and SCKBZ, a data driving start signal SSPZ, and a video signal VideoData. ₁ ~ V _M Is input, the circuit operation as shown in FIG. ₁ ~ SL _M And data V ₁ ~ V _M Are transferred sequentially.
[0018]
That is, first and first stage D-type flip-flop DFF ₁ When the data operation clock SCKZ becomes High while the input data drive start signal SSPZ is High, the output SQZ ₁ Is High. This output SQ ₁ After the data drive start signal SSPZ becomes Low, the data operation clock SCKZ becomes High again to become Low.
[0019]
At this time, the length of the data drive start signal SSP is set so that the high period of the SSPZ has substantially the same length as one cycle of the data operation clock SCKZ. For this reason, the output SQ ₁ The high period is also equal to one cycle of the data operation clock SCKZ. Output SQ ₁ Is the first AND gate AND ₁ And D-type flip-flop DFF at the next stage ₂ D terminal input to
[0020]
In addition, the m-th stage D-type flip-flop DFF after the second stage _m Is the input of the D terminal, that is, the output SQ of the previous stage _m-1 While D is High, the D-type flip-flop DFF _m When the data operation clock SCCKZ or SCKBZ input to the high level becomes high, the output SQ _m Is High. This output SQ _m Is the output SQ of the previous stage _m-1 After becoming low, the data operation clock SCKZ or SCKBZ becomes high again to become low.
[0021]
Thus, each stage of the D-type flip-flop DFF ₁ ~ DFF _{M + 1} Output SQ ₁ ~ SQ _{M + 1} Is obtained as the High period is equal to one cycle of the data operation clock SCKZ or SCKBZ, and the rising timing is generated every ½ cycle of the data operation clock SCCKZ or SCKBZ.
[0022]
The m-th AND gate AND _m Includes m-th and (m + 1) -th stage D-type flip-flops DFF _m , DFF _{m + 1} Output signal SQ at _m , SQ _{m + 1} Is entered. Therefore, AND gate AND of each stage ₁ ~ AND _M Output Y ₁ ~ Y _M Is obtained assuming that the High period is ½ period of the data operation clock SCKZ or SCKBZ and the rising timing is generated every ½ period of the data operation clock SCCKZ or SCKBZ.
[0023]
Each stage AND gate AND ₁ ~ AND _M Output Y ₁ ~ Y _M Since the switch 301 at each stage is turned ON in each High period, the data V in the video signal VideoData ₁ ~ V _M Is the data signal line SL every half cycle of the data operation clock SCCKZ or SCKBZ. ₁ ~ SL _M Are sent sequentially.
[0024]
Next, the configuration of the scan driving circuit 104 is shown in FIG. The scan driving circuit 104 has (N + 1) -stage RS flip-flop RSFF _n (1 ≦ n ≦ N + 1) and (N + 1) stages of AND gates 401 are included.
[0025]
Each RS flip-flop RSFF _n To the set input terminal S, the scanning drive start signal GSPZ is input in the first stage, and the output signal of the preceding AND gate 401 is input in the second and subsequent stages. Also, each RS flip-flop RSFF _n The reset input terminal R receives the output signal of the next-stage AND gate 401 except for the final stage. Final stage RS flip-flop RSFF _{N + 1} The reset input terminal R receives the output signal of the AND gate 401 of its own stage.
[0026]
Furthermore, each RS flip-flop RSFF _n The initialization signal RESZ input to the reset terminal RES of all the stages is an RS flip-flop RSFF at all stages when the power is turned on. _n Is a signal for initializing each RS flip-flop RSFF _n Output GQ when initialized _n Is Low.
[0027]
The two-stage input terminals of the n-th AND gate 401 have their own (n-th) stage RS flip-flop RSFF. _n Output GQ at _n And the scanning operation clock signal GCK1Z or GCK2Z. As for the scanning operation clock signals GCK1Z and GCK2Z, the clock signal GCK1Z is input to the odd-numbered AND gate 401, and the clock signal GCK2Z is input to the even-numbered AND gate 401. In addition, the scanning operation clock signals GCK1Z and GCK2Z have a High period shorter than a Low period and a phase shifted by 1/2 period within one period. That is, the scanning operation clock signals GCK1Z and GCK2Z are set so that the High periods are alternately generated but the High periods are not overlapped with each other.
[0028]
The scan driving circuit 104 configured as described above performs the circuit operation as shown in FIG. 14 when the scan operation clocks GCK1Z and GCK2Z and the scan drive start signal GSPZ are input, and the scan signal line GL. ₁ ~ GL _N Are driven sequentially. The scanning signal line GL in the final stage _{N + 1} Is provided as a dummy and is not actually driven.
[0029]
First, each stage RS flip-flop RSFF _n Output SQ _n Is low, each stage RS flip-flop RSFF _n The input to the reset input terminal R is Low. And the first stage RS flip-flop RSFF ₁ When the scanning drive start signal GSPZ that is input to the set input terminal S becomes high, the output GQ ₁ Becomes High.
[0030]
Above output GQ ₁ Is one input of the AND gate 401 in the first stage and the output GQ ₁ When the scanning operation clock GCK1Z becomes High while is high, the AND gate 401 at the first stage sets the output to High during the period when the scanning operation clock GCK1Z is High. The output of the AND gate 401 of each stage is the scanning signal line GL of the corresponding stage. ₁ ~ GL _N Drive signal.
[0031]
When the output from the AND gate 401 at the first stage becomes High, the output is the RS flip-flop RSFF at the next stage (second stage). ₂ RS type flip-flop RSFF ₂ Output GQ ₂ Is set to High. And the output GQ ₂ When the scanning operation clock GCK2Z becomes High while is high, the AND gate 401 at the second stage sets the output to High during the period when the scanning operation clock GCK2Z is High. Further, when the output from the AND gate 401 at the second stage becomes High, this output is the RS flip-flop RSFF at the next stage (third stage). _Three RS input flip-flop RSFF in the previous stage (first stage) ₁ At this point, the first stage RS flip-flop RSFF ₁ Output GQ ₁ Is Low.
[0032]
Thus, each stage RS flip-flop RSFF ₁ ~ RSFF _{N + 1} Output GQ ₁ ~ GQ _{N + 1} Is obtained as the High period is equal to one cycle of the scanning operation clock GCK1Z or GCK2Z, and the rising timing is generated every half cycle of the scanning operation clock GCK1Z or GCK2Z.
[0033]
In addition, the AND gate 401 in each stage includes an RS type flip-flop RSFF in its own stage. _n In the High period, the ON pulse (High period) of the input scanning operation clock signal is applied to the scanning signal line GL. ₁ ~ GL _N Output as a drive signal.
[0034]
Here, in each level shifter 106 used in the level shifter circuit 105 of the matrix type display device, as shown in FIG. 9, the P channel transistor 201 and the N channel are connected between the input terminal of the power supply VDD and the input terminal of the power supply VSS. Current always flows through the channel transistor 203. In addition, a current always flows through the P-channel transistor 202 and the N-channel transistor 204 between the input terminal of the power supply VDD and the input terminal of the input signal IN.
[0035]
This constantly flowing current is referred to as a steady current, and an increase in the steady current causes an increase in power consumption in the level shifter circuit 105, which is not preferable. For this reason, in order to reduce the steady current, the capability of the P-channel transistor and the N-channel transistor of FIG. 9 is weakened (specifically, the channel length of the transistor is made large or the channel width is made small). There is a method of connecting P-channel transistors and N-channel transistors in series as shown in FIG.
[0036]
[Problems to be solved by the invention]
However, in order to reduce the steady-state current generated in the level shifter 106, if the above-described configuration such as weakening the capability of the transistor or connecting the transistors in series is adopted, the signal after the level shift is compared with the signal before the level shift. The delay that occurs in the signal (see FIG. 10) increases.
[0037]
For this reason, when the above-described configuration for reducing the steady current is adopted for each level shifter 106 in the level shifter circuit 105, the data drive circuit 103 and the operation drive circuit 104 have a problem of causing a malfunction as described below. .
[0038]
First, the occurrence of malfunction in the data driving circuit 103 will be described with reference to FIG.
[0039]
In the operation illustrated in FIG. 16, the falling period of the data drive start signal SSPZ is increased, so that the High period of the data drive start signal SSPZ is longer than the High period of the data drive start signal SSP before the level shift. As a result, the data operation clock SCKZ rises twice during the high period of the data drive start signal SSPZ (once during normal operation).
[0040]
Therefore, in the data driving circuit 103, the first stage D-type flip-flop DFF ₁ Output SQ ₁ Is a period High for two cycles of the data operation clock SCKZ. The first stage D-type flip-flop DFF ₁ Output SQ ₁ Becomes high for two cycles, so that the D-type flip-flop DFF in the second and subsequent stages ₂ ~ DFF _{M + 1} Output SQ ₂ ~ SQ _{M + 1} Similarly, it becomes High for two cycles.
[0041]
Therefore, AND gate AND of each stage ₁ ~ AND _M Output Y ₁ ~ Y _M In FIG. 12, the High period is 1.5 times that of the normal operation shown in FIG. 12, and corresponds to 3/2 periods of the data operation clock SCKZ or SCKBZ.
[0042]
Thus, each stage of AND gate AND ₁ ~ AND _M Output Y ₁ ~ Y _M When the High period becomes 3/2 cycles of the data operation clock SCKZ or SCKBZ, correct data writing cannot be performed on each data signal line. For example, the first stage data signal line SL ₁ In the high period corresponding to the first half cycle, the original data V ₁ Is the data signal line SL ₁ Is transferred to the next data V in the High period corresponding to one period thereafter. ₂ And next-stage data V _Three Is the data signal line SL ₁ Malfunctions such that correct data is rewritten. A similar malfunction is caused by the data signal line SL in the second and subsequent stages. ₂ ~ SL _M Also occurs.
[0043]
Even when the rise delay of the data drive start signal SSPZ increases and the data drive start signal SSPZ does not become High at the rise of the data operation clock SCKZ, the first stage D-type flip-flop DFF ₁ Output SQ ₁ Does not become high, the data driving circuit 103 malfunctions. However, this malfunction is caused by the data drive start signal before the level shift so that the data drive start signal SSPZ becomes High before the rise of the data operation clock SCKZ even if the rise delay of the data drive start signal SSPZ becomes maximum. This can be avoided by setting the SSP input timing.
Next, the occurrence of a malfunction in the scan drive circuit 104 will be described with reference to FIG.
[0044]
In the operation illustrated in FIG. 17, the high delay period of the scan drive start signal GSPZ is longer than the high period of the scan drive start signal GSP before the level shift because the falling delay of the scan drive start signal GSPZ is increased. As a result, the High period of the scanning drive start signal GSPZ is the second scanning signal line GL. ₂ When the output to the output extends from the High to Low switching timing, the first stage RS flip-flop RSFF ₁ Set input signal (scanning drive start signal GSPZ) and reset input signal (scanning signal line GL) ₂ And the signal supplied to the signal) are simultaneously high.
[0045]
Here, the operation of the RS flip-flop becomes unstable when the set input and the reset input become High at the same time, and it is unknown whether the output of the RS flip-flop in this case is High or Low. It is. In the description of FIG. 17, when the reset input signal becomes High within the High period of the set input signal, it is assumed that the output of the RS flip-flop is not reset and remains High.
[0046]
At this time, the first stage RS flip-flop RSFF ₁ Is its output GQ ₁ The High period is a period including two pulses of the High period of the scanning operation clock GCK1Z. For this reason, the first-stage AND gate 401 outputs a two-pulse waveform to the scanning signal line GL1.
[0047]
Also, the n-th stage (second stage and later) RS flip-flop RSFF _n Set input signal (scan signal line GL of the previous stage _n-1 Signal) and a reset signal (scan signal line GL at the next stage) _{n + 1} When the signal (supplied to the signal) becomes High at the same time, the RS flip-flop RSFF _n If is not reset, as in the first stage, the nth stage RS flip-flop RSFF _n Output GQ _n Is a period including two pulses of the high period of the scanning operation clock GCK1Z or GCK2Z. For this reason, the AND gate 401 at each stage converts the waveform of two pulses into the scanning signal line GL. _n Malfunctions such as output to
[0048]
Also, each stage RS flip-flop RSFF _n When the reset input signal becomes High during the High period of the set input signal, the RS flip-flop RSFF _n Output GQ _n Assuming that is reset to Low, a malfunction as shown in FIG. 18 may occur.
[0049]
That is, the first stage RS flip-flop RSFF ₁ The scanning drive start signal GSPZ used as the set input and the signal used as the reset input (scanning signal line GL ₂ RS-type flip-flop RSFF when the signal) is simultaneously High. ₁ Even if the signal is reset, the scanning signal line GL ₂ When the scanning drive start signal GSPZ maintains the High period until the timing at which the signal supplied to High goes from Low to Low, as shown in FIG. 18, the RS flip-flop RSFF ₁ Output GQ ₁ Is reset once and then set again. As a result, the first stage RS flip-flop RSFF ₁ Output GQ ₁ The high period includes two pulses of the high period of the scanning operation clock GCK1Z, and the waveform of the two pulses is changed to the scanning signal line GL. ₁ Malfunctions such as being output to.
[0050]
Further, the rising delay of the scanning drive start signal GSPZ is large and the scanning drive start signal GSPZ does not become High at the rising edge of the scanning operation clock GCK1Z. That is, the RS flip-flop RSFF ₁ Output GQ ₁ Even when the signal does not become High, the scanning signal line GL ₁ The High period at the output of the signal becomes shorter, and the scan driving circuit 104 malfunctions. However, this malfunction is caused by the scan drive start signal GSP before being level-shifted so that the scan drive start signal GSPZ becomes High before the rise of the scan operation clock GCK1Z even if the rise delay of the scan drive start signal GSPZ is maximized. Can be avoided by setting the input timing
For this reason, in the conventional matrix display device, a configuration in which the power consumption of the level shifter circuit is reduced is applied only when the periods of the data drive start signal SSP and the scan drive start signal GSP to be used are large (not frequently changed). In the case where the period of the data drive start signal SSP and the scan drive start signal GSP is small, it is difficult to apply the above configuration for reducing the power consumption of the level shifter circuit.
[0051]
The present invention has been made to solve the above problems, and its purpose is to start data driving when a configuration is adopted in which steady current in a level shifter circuit is suppressed and power consumption of the level shifter circuit is reduced. An object of the present invention is to provide a matrix display device that can prevent malfunction due to delay of the signal SSP and the scan drive start signal GSP.
[0052]
[Means for Solving the Problems]
In order to solve the above problems, a display device of the present invention includes a display element, a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, and the data signal line and the scanning signal line. In a display device including a data drive circuit and a scan drive circuit to be driven, level shift means for level-shifting a data drive start signal input to the data drive circuit, and between the level shift means and the data drive circuit And a delay correction unit that corrects a delay generated in the data drive start signal by a level shift operation by the level shift unit.
[0053]
When the level shift means is designed to suppress the steady current generated in the level shift means and reduce its power consumption, the delay of the signal generated in the data drive start signal level-shifted by the level shift means Will increase. This delay of the data drive start signal causes a malfunction in the data drive circuit.
[0054]
On the other hand, according to the above configuration, the delay generated in the data drive start signal after the level shift is corrected by the delay correction unit, and the corrected data drive start signal is supplied to the data drive circuit. For this reason, in the data drive circuit, malfunction due to delay of the data drive start signal is prevented.
[0055]
As a result, the steady current of the level shift means can be sufficiently reduced without causing a malfunction of the data drive circuit.
[0056]
In the display device, it is preferable that the delay correction unit corrects a delay in OFF timing of the data drive start signal after the level shift.
[0057]
The delay that occurs in the data drive start signal due to the level shift in the level shift means is determined by setting the input of the data drive start signal before the level shift to an appropriate timing with respect to the ON timing delay. Can be avoided. For this reason, the delay correction means can prevent malfunction of the data drive circuit by correcting the delay of the OFF timing of the data drive start signal after the level shift. The OFF timing delay referred to here is a falling delay when the data drive start signal is high active, and a rising delay when the data driving start signal is low active.
[0058]
In the display device, it is preferable that the delay correction unit corrects the delay of the data drive start signal after the level shift by using a part of the signal generated in the data drive circuit.
[0059]
For example, in the case where the delay correction means forcibly reduces the falling edge of the data drive start signal (when High is active) in accordance with the rising or falling edge of another correction signal, the correction is performed. As the correction signal, a generated signal in the data driving circuit that rises or falls at a desired timing can be used.
[0060]
According to the above configuration, the delay correction unit corrects the delay of the data drive start signal after the level shift by using a part of the signal generated in the data drive circuit, so that a new correction signal is obtained. Therefore, it is possible to correct the delay of the data drive start signal without increasing the circuit scale.
[0061]
In order to solve the above problems, a display device of the present invention includes a display element, a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, the data signal line, and the scanning signal line. In a display device comprising a data drive circuit and a scan drive circuit for driving each of the above, a level shift means for level-shifting a scan drive start signal input to the scan drive circuit, and the level shift means and the scan drive circuit And a delay correction unit which is disposed between the delay unit and corrects a delay generated in the scanning drive start signal by a level shift operation by the level shift unit.
[0062]
When the level shift means is designed to suppress the steady current generated in the level shift means and reduce its power consumption, the signal delay generated in the scanning drive start signal level-shifted by the level shift means Will increase. This delay of the scan drive start signal causes a malfunction in the scan drive circuit.
[0063]
On the other hand, according to the above configuration, the delay correction means corrects the delay generated in the scan drive start signal after the level shift, and provides the scan drive start signal after correction to the scan drive circuit. For this reason, in the scanning drive circuit, malfunction due to the delay of the scanning drive start signal is prevented.
[0064]
As a result, the steady-state current of the level shift means can be made sufficiently small without causing a malfunction of the scanning drive circuit.
[0065]
In the display device, it is preferable that the delay correcting unit corrects a delay in OFF timing of the scanning drive start signal after the level shift.
[0066]
The delay that occurs in the scan drive start signal due to the level shift in the level shift means is set to an appropriate timing for the input of the scan drive start signal before the level shift with respect to the ON timing delay. Can be avoided. For this reason, the delay correcting unit corrects the OFF timing delay of the scan drive start signal after the level shift, thereby preventing the malfunction of the scan drive circuit. The OFF timing delay referred to here is a falling delay when the scanning drive start signal is High active, and a rising delay when the Scan driving start signal is Low active.
[0067]
In the display device, it is preferable that the delay correction unit corrects the delay of the scan drive start signal after the level shift by using a part of the signal generated in the scan drive circuit.
[0068]
For example, when the delay correcting means forcibly reduces the falling edge of the scanning drive start signal in accordance with the rising edge or the falling edge of another correction signal and corrects it, a desired timing is used as the correction signal. A generation signal in the scan driving circuit in which rising or falling occurs can be used.
[0069]
According to the above configuration, the delay correction unit corrects the delay of the scan drive start signal after the level shift using a part of the signal generated in the scan drive circuit, so that a new correction signal is obtained. Therefore, the delay of the scan drive start signal can be corrected without increasing the circuit scale.
[0070]
In the above display device, the display element, the plurality of data signal lines, the plurality of scanning signal lines, the data driving circuit, the scanning driving circuit, the level shifter unit, and the delay correcting unit may be formed on the same substrate. it can.
[0071]
According to the above configuration, the level shifter means and the delay correction means can be manufactured in the same process as the data drive circuit, the scan drive circuit, etc., and the manufacturing cost can be reduced compared with the case where the level shifter means and the delay correction means are provided outside the apparatus. Can do.
[0072]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.
[0073]
FIG. 2 shows a configuration of a matrix display device (display device) according to this embodiment.
[0074]
The matrix type display device 1 shown in FIG. 2 includes data signal lines SL parallel to the column direction in the display unit. _m A large number of (1 ≦ m ≦ M) are arranged in the row direction, and the scanning signal lines GL are parallel to the row direction. _n Many (1 ≦ n ≦ N) are arranged in the column direction, and a display element is provided at each intersection of the scanning signal line GL and the data signal line SL via a switching element. Data signal line SL ₁ ~ SL _M Is connected to the data driving circuit 2 and the scanning signal line GL ₁ ~ GL _N Are connected to the scanning drive circuit 3.
[0075]
The display unit, the data drive circuit 2, and the scan drive circuit 3 in the matrix display device 1 are the same as the display unit, the data drive circuit 103, and the scan drive circuit 104 in the conventional matrix display device 100 described with reference to FIG. It can be set as this structure. Therefore, detailed description of the display unit, the data drive circuit 2, and the scan drive circuit 3 is omitted here.
[0076]
In the matrix display device 1, the data driving circuit 2 includes data operation clock signals SCK and SCKB for driving the data driving circuit 2, a data driving start signal SSP for starting driving, and the data driving circuit 2 Initialization signal RES and data signal line SL for initializing ₁ ~ SL _M The video signal to be output is input.
[0077]
Further, the scan drive circuit 3 initializes the scan operation clock signals GCK1 and GCK2 for driving the scan drive circuit 3, the scan drive start signal GSP for starting the drive, and the scan drive circuit 3. The initialization signal RES is input.
[0078]
Of the above signals, the data operation clock signals SCK and SCKB, the data drive start signal SSP, the scan operation clock signals GCK1 and GCK2, the scan drive start signal GSP, and the initialization signal RES are actually the data drive circuit 2 Alternatively, the level is shifted by the level shifter circuit 4 before being input to the scanning drive circuit 32. Since the configuration of the level shifter circuit 4 is also the same as the conventional configuration described with reference to FIGS. 8 and 9, detailed description of the level shifter circuit 4 is omitted here. In the following description, in order to distinguish the signal after the level shift from the signal before the level shift, “Z” is added to the end of the signal name before the level shift.
[0079]
Further, in the matrix type display device 1 according to the present embodiment, as shown in FIG. 1, the data drive start signal SSPZ and the scan drive start signal GSPZ after the level shift are caused by the malfunction prevention circuit 5 as a cause of malfunction. The delay of the OFF timing of the signal is corrected. In the following description, the signal after being corrected by the malfunction prevention circuit 5 has a level to distinguish it from a signal before being level-shifted (that is, a signal that is first input to the matrix display device 1). “ZZ” is added to the end of the signal name before being shifted.
[0080]
In the present embodiment, both the data drive start signal SSPZ and the scan drive start signal GSPZ exemplify the case where they are High active, and the malfunction prevention circuit 5 corrects the delay of the fall of these signals.
[0081]
In the following description, the configurations of the data drive circuit 2 and the scan drive circuit 3 are the same as those in FIGS. 11 and 13, but in the data drive circuit 2, data drive start is performed instead of the data drive start signal SSPZ. The signal SSPZZ is input, and the scan drive circuit 3 receives the data drive start signal GSPZZ instead of the scan drive start signal GSPZ.
[0082]
Here, an outline of the operation of the malfunction prevention circuit 5 will be described below. First, the cause of the malfunction in the conventional matrix type display device 100 is that, for example, the operation of the data drive circuit, the fall delay of the data drive start signal SSPZ is increased, so that the high period of the data drive start signal SSPZ is high. This is because the rising edge of the data operation clock SCKZ is entered twice (see FIG. 16).
[0083]
Therefore, the malfunction prevention circuit 5 corrects the falling delay of the data drive start signal SSPZ to ensure that the data operation clock SCKZ rises only once during the High period of the data drive start signal SSPZ. That's fine. In other words, for the data driving circuit 2, after the data driving start signal SSPZ becomes High, the first stage D-type flip-flop DFF ₁ Output SQ ₁ Becomes high at the rising edge of the data operation clock SCKZ, the data drive start signal SSPZ is no longer required to be high at that time.
[0084]
That is, the malfunction prevention circuit 5 that corrects the data drive start signal SSPZ input to the data drive circuit 2 has a first stage D-type flip-flop DFF as shown in FIG. ₁ Output SQ ₁ And the output SQ ₁ When becomes high, the data drive start signal SSPZ is set to low. Further, in the malfunction prevention circuit 5 according to the present embodiment (when the data drive start signal SSPZ is corrected), in correcting the data drive start signal SSPZ to the data drive start signal SSPZZ, the first stage D-type flip-flop DFF ₁ Output SQ ₁ In addition, the final D-type flip-flop DFF _{M + 1} Output SQ _{M + 1} And receives an initialization signal RESZ. Output SQ _{M + 1} The role of the initialization signal RESZ will be described later.
[0085]
Next, a more specific configuration of the malfunction prevention circuit 5 will be described with reference to FIG. 3, and operations of the malfunction prevention circuit 5 and the data drive circuit 2 will be described with reference to FIG.
[0086]
As shown in FIG. 3, the malfunction prevention circuit 5 includes an RS flip-flop 51 and an AND gate 52. When the malfunction prevention circuit 5 is used for correcting the data drive start signal SSPZ, the data drive start signal SSPZ is input as the input signal IN, and the corrected data drive start signal SSPZZ is output as the output signal OUT.
[0087]
Further, in the RS flip-flop 51, the set input signal S is the first stage D-type flip-flop DFF of the data driving circuit 2. ₁ Output SQ at ₁ And the reset input signal R is the D-type flip-flop DFF at the final stage. _{M + 1} Output SQ at _{M + 1} Is used.
[0088]
The AND gate 52 receives the inverted output FFQB of the RS flip-flop 51 and the data drive start signal SSPZ as the input signal IN as two inputs, and the output of the AND gate 52 is an output signal OUT, that is, a correction. The subsequent data drive start signal SSPZZ is obtained. Furthermore, when the power is turned on, the RS flip-flop 51 sets its inverted output FFQB to High by the initialization signal RESZ (note that the output FFQ is not used in the RS flip-flop 51).
[0089]
As shown in FIG. 4, the operation of the malfunction prevention circuit 5 starts with a set input signal (output SQ in the RS flip-flop 51). ₁ ) And reset input signal (output SQ) _{M + 1} ) Are both low, the inverted output FFQB is high.
[0090]
Therefore, the AND gate 52 outputs the data drive start signal SSPZ as the other input as it is as the data drive start signal SSPZZ while the inverted output FFQB from the RS flip-flop 51 is High. That is, when the data drive start signal SSPZ becomes High, the corrected data drive start signal SSPZZ also becomes High at the same time.
[0091]
Next, the first stage D-type flip-flop DFF of the data driving circuit 2 ₁ When the first rising edge of the data operation clock SCKZ is input while the data drive start signal SSPZZ is High, the D-type flip-flop DFF ₁ Output SQ ₁ Becomes High.
[0092]
This output SQ ₁ Is the second stage D-type flip-flop DFF ₂ And the first AND gate AND ₁ And the set input in the RS flip-flop 51 of the malfunction prevention circuit 5. For this reason, the output SQ ₁ When becomes high, the inverted output FFQB of the RS flip-flop 51 becomes low, and the data drive start signal SSPZZ becomes low.
[0093]
The inverted output FFQB in the RS flip-flop 51 is the output SQ. ₁ Even after the signal becomes low, the low state is maintained. For this reason, even if a high state delay occurs in the data drive start signal SSPZ before correction, the data drive start signal SSPZZ after correction is output SQZ. ₁ Switches to Low as output becomes High, and the output SQ ₁ The low state is maintained even after becomes low.
[0094]
Therefore, the first stage D-type flip-flop DFF of the data driving circuit 2 ₁ When the second rising edge of the data operation clock SCKZ is input, the data drive start signal SSPZZ is surely switched to Low. Therefore, the D-type flip-flop DFF is triggered by the second rise of the data operation clock SCKZ. ₁ Output SQ ₁ Becomes Low, the first D-type flip-flop DFF ₁ Output SQ at ₁ Is the normal operation.
[0095]
Further, in the conventional example, the malfunction after the second stage is caused by the influence of the malfunction at the first stage. By preventing the malfunction at the first stage by the malfunction prevention circuit 5, the malfunction after the second stage is also eliminated. It is easy to understand.
[0096]
With the above operation, the data driving circuit 2 can perform a normal operation in one line scanning. However, after the operation is completed up to the final stage of the data driving circuit 2, even if the next data driving start signal SSPZ becomes High when the inverted output FFQB of the RS flip-flop 51 remains Low, the data driving start signal SSPZZ Does not become High, and the driving of the data driving circuit 2 cannot be started in the next line.
[0097]
For this reason, in the malfunction prevention circuit 5, the D-type flip-flop DFF at the final stage is set before the data drive start signal SSPZ at the time of scanning the next line becomes High. _{M + 1} Output SQ _{M + 1} As a result, the inverted output FFQB of the RS flip-flop 51 is set to High. In this way, when the data drive start signal SSPZ next becomes High, the corrected data drive start signal SSPZZ also becomes High, so that the drive of the data drive circuit 2 can be started.
[0098]
In the malfunction prevention circuit 5 in the above description, the first stage D-type flip-flop DFF is used as the set input signal of the RS-type flip-flop 51. ₁ Output SQ ₁ And output SQ ₁ The data drive start signal SSPZZ after correction is switched to Low at the rising edge.
[0099]
However, in order to prevent malfunction in the data driving circuit 2, it is only necessary that the corrected data driving start signal SSPZZ is Low at the second rising edge of the data operation clock SCKZ. That is, if the set input signal of the RS flip-flop 51 is a signal that switches from Low to High before the second rise of the data operation clock SCKZ, the output SQ ₁ Other signals can also be used.
[0100]
For example, in the example of FIG. 4, the second stage D-type flip-flop DFF ₂ Output SQ ₂ May be the set input signal of the RS flip-flop 51. Alternatively, the output Y of the AND gate may be used in addition to the output of the D-type flip-flop. In this case, the AND gate AND of the first stage is used. ₁ Output Y ₁ May be the set input signal of the RS flip-flop 51.
[0101]
In the malfunction prevention circuit 5, the final D-type flip-flop DFF is used as the reset input signal of the RS-type flip-flop 51. _{M + 1} Output SQ _{M + 1} And output SQ _{M + 1} The inverted output FFQB of the RS flip-flop 51 is switched to High at the rising edge.
[0102]
However, after the data drive start signal SSPZ becomes Low, even if the inverted output FFQB of the RS flip-flop 51 of the malfunction prevention circuit 5 is set to High, the corrected data drive start signal SSPZZ is maintained in the Low state. . Therefore, after the data drive start signal SSPZ becomes completely low, the RS flip-flop 5 may be reset at an arbitrary timing (the inverted output FFQB may be set to High). That is, the reset input signal of the RS flip-flop 51 is an output SQ if the signal is switched from Low to High after the data drive start signal SSPZ is completely Low. _{M + 1} Other signals can also be used.
[0103]
For example, in the example of FIG. 4, the output of the D-type flip-flops in the fourth and subsequent stages may be used as the reset input signal of the RS-type flip-flop 51. Alternatively, the output Y of the AND gate may be used in addition to the output of the D-type flip-flop. In this case, the output of the third-stage and subsequent AND gates may be used as the reset input signal of the RS-type flip-flop 51.
[0104]
Further, in the set input signal or the reset input signal of the RS flip-flop 51, an external signal may be used in addition to the signal generated by the data driving circuit 2.
[0105]
Next, an outline of the operation of the malfunction prevention circuit 5 when correcting the scanning drive start signal GSPZ will be described below. First, the cause of the malfunction in the scanning drive circuit 3 in the conventional matrix type display device 100 is that the falling delay of the scanning drive start signal GSPZ becomes large, so that the first stage RS flip-flop RSFF ₁ Set input signal (scanning drive start signal GSPZ) and reset input signal (scanning signal line GL) ₂ This is because there is a period in which the signal supplied to the signal (High) is simultaneously High (see FIG. 17).
[0106]
Therefore, the malfunction prevention circuit 5 corrects the falling delay of the scan drive start signal GSPZ, thereby correcting the first stage RS flip-flop RSFF. ₁ Set input signal (scanning drive start signal GSPZ) and reset input signal (scanning signal line GL) ₂ It is only necessary to prevent a period during which the signal supplied to the signal (High) is high at the same time. In other words, for the scan drive circuit 3, the scan drive start signal GSPZ becomes High, so that the first stage RS flip-flop RSFF ₁ Output GQ ₁ Becomes high, the scanning drive start signal GSPZ is no longer required to be high at that time.
[0107]
That is, the malfunction prevention circuit 5 that corrects the scan drive start signal GSPZ input to the scan drive circuit 3 has an RS flip-flop RSFF at the first stage as shown in FIG. ₁ Output GQ ₁ Output, and the output GQ ₁ When becomes high, the scanning drive start signal GSPZ is set to low. In addition, in the malfunction prevention circuit 5 according to the present embodiment (when the scan drive start signal GSPZ is corrected), the first stage RS flip-flop RSFF is used to correct the scan drive start signal GSPZ to the scan drive start signal GSPZZ. ₁ Output GQ ₁ In addition, RS flip-flop RSFF at the final stage _{M + 1} Output GQ _{M + 1} And receives an initialization signal RESZ. Output GQ _{M + 1} The role of the initialization signal RESZ will be described later.
[0108]
Next, operations of the malfunction prevention circuit 5 and the scan drive circuit 3 when the scan drive start signal GSPZ is corrected will be described with reference to FIGS.
[0109]
When the malfunction prevention circuit 5 is used for correcting the scanning drive start signal GSPZ, the RS flip-flop 51 receives the first input RS flip-flop RSFF of the scanning drive circuit 3 as shown in FIG. ₁ Output GQ at ₁ Is used, and the reset input signal R is the final stage RS flip-flop RSFF. _{N + 1} Output GQ at _{N + 1} Is used.
[0110]
The AND gate 52 receives the inverted output FFQB of the RS flip-flop 51 and the scanning drive start signal GSPZ as the input signal IN as two inputs, and the output of the AND gate 52 is the output signal OUT, that is, the correction. This becomes the later scanning drive start signal GSPZZ. Further, the RS flip-flop 51 sets its inverted output FFQB to High by the initialization signal RESZ when the power is turned on.
[0111]
As shown in FIG. 6, the operation of the malfunction prevention circuit 5 starts with a set input signal (output GQ) in the RS flip-flop 51. ₁ ) And reset input signal (output GQ) _{N + 1} ) Are both low, the inverted output FFQB is high.
[0112]
Therefore, the AND gate 52 outputs the scan drive start signal GSPZ, which is the other input, as it is as the scan drive start signal GSPZZ while the inverted output FFQB from the RS flip-flop 51 is High. That is, when the scan drive start signal GSPZ becomes High, the corrected scan drive start signal GSPZZ also becomes High at the same time.
[0113]
Next, the first stage RS flip-flop RSFF of the scan driving circuit 3 ₁ When the scanning drive start signal GSPZZ becomes High, the RS flip-flop RSFF is ₁ Output GQ ₁ Becomes High.
[0114]
This output GQ ₁ Are input to the first-stage AND gate 401 and set input to the RS flip-flop 51 of the malfunction prevention circuit 5. For this reason, the output GQ ₁ When becomes high, the inverted output FFQB of the RS flip-flop 51 becomes low, and the scanning drive start signal GSPZZ is set low.
[0115]
The inverted output FFQB in the RS flip-flop 51 is the output GQ. ₁ Even after the signal becomes low, the low state is maintained. For this reason, even if a high-state delay occurs in the scan drive start signal GSPZ before correction, the scan drive start signal GSPZZ after correction is output GQZ. ₁ Switches to Low when becomes High, and the output GQ ₁ The low state is maintained even after becomes low.
[0116]
Therefore, the first stage RS flip-flop RSFF of the scan driving circuit 3 ₁ , The reset input signal (scanning signal line GL ₂ When the signal (supplied to) becomes High, the set input signal (scanning drive start signal GSPZ) has already been switched to Low, and the set input signal and the reset input signal do not become High at the same time. First stage RS flip-flop RSFF ₁ Reset input signal (scanning signal line GL ₂ When the signal supplied to the high level becomes high, the RS flip-flop RSFF ₁ Makes sure that its output is Low, the first stage RS flip-flop RSFF ₁ Output GQ at ₁ Is the normal operation.
[0117]
Also in the scanning drive circuit 3, in the conventional example, the malfunction after the second stage occurs due to the influence of the malfunction at the first stage, and the malfunction at the first stage is prevented by the malfunction prevention circuit 5. It is easily understood that subsequent malfunctions are also eliminated.
[0118]
With the above operation, the scan driving circuit 3 can perform a normal operation in one line scanning. However, after the operation up to the final stage of the scanning drive circuit 3 is completed, if the inverted output FFQB of the RS flip-flop 51 remains Low, the scanning drive start signal GSPZZ is not changed even if the next scan drive start signal GSPZ becomes High. Does not become High, and driving of the scanning drive circuit 3 cannot be started in the next line.
[0119]
Therefore, in the malfunction prevention circuit 5, the RS flip-flop RSFF at the final stage is set before the scanning drive start signal GSPZ at the time of scanning the next line becomes High. _{N + 1} Output GQ _{N + 1} As a result, the inverted output FFQB of the RS flip-flop 51 is set to High. In this way, when the scan drive start signal GSPZ next becomes High, the corrected scan drive start signal GSPZZ also becomes High, so that the drive of the scan drive circuit 3 can be started.
[0120]
In the malfunction prevention circuit 5 in the above description, the first stage RS flip-flop RSFF is used as the set input signal of the RS flip-flop 51. ₁ Output GQ ₁ And output GQ ₁ The scan drive start signal GSPZZ after correction is switched to Low at the rising edge.
[0121]
However, in order to prevent a malfunction in the scan drive circuit 3, the corrected scan drive start signal GSPZZ is supplied to the first stage RS flip-flop RSFF. ₁ Reset input signal (scanning signal line GL ₂ It is only necessary that the signal to be low before the signal) is high. In other words, the set input signal of the RS flip-flop 51 includes the scanning signal line GL. ₂ If the signal is switched from Low to High before the rise of the signal supplied to the output GQ, the output GQ ₁ Other signals can also be used.
[0122]
For example, in the example of FIG. 6, the RS flip-flop RSFF at the second stage ₂ Output GQ ₂ Or the third stage RS flip-flop RSFF _Three Output GQ _Three May be the set input signal of the RS flip-flop 51. Alternatively, in addition to the output of the RS flip-flop, the output of the AND gate 401 or the like may be used. In this case, the output of the first-stage AND gate 401 (scanning signal line GL) ₁ May be used as the set input signal of the RS flip-flop 51.
[0123]
In the malfunction prevention circuit 5, the RS-type flip-flop RSFF at the final stage is used as the reset input signal of the RS-type flip-flop 51. _{N + 1} Output GQ _{N + 1} And output GQ _{N + 1} The inverted output FFQB of the RS flip-flop 51 is switched to High at the rising edge.
[0124]
However, after the scan drive start signal GSPZ becomes Low, even if the inverted output FFQB of the RS flip-flop 51 of the malfunction prevention circuit 5 is set to High, the corrected scan drive start signal GSPZZ is maintained in the Low state. . Therefore, after the scanning drive start signal GSPZ becomes completely low, the RS flip-flop 5 may be reset at an arbitrary timing (the inverted output FFQB may be set to High). That is, if the reset input signal of the RS flip-flop 51 is a signal that switches from Low to High after the scanning drive start signal GSPZ is completely Low, the output GQ _{N + 1} Other signals can also be used.
[0125]
For example, in the example of FIG. 6, the output of the RS flip-flops in the fourth and subsequent stages in the scan driving circuit 3 may be used as the reset input signal of the RS flip-flop 51 in the malfunction prevention circuit 5. Alternatively, the output of the AND gate or the like may be used in addition to the output of the RS flip-flop. In this case, the output of the third and subsequent AND gates may be used as the reset input signal of the RS flip-flop 51.
[0126]
Further, in the set input signal or the reset input signal of the RS flip-flop 51, an external signal may be used in addition to the signal generated by the scan driving circuit 3.
[0127]
In the description according to the present embodiment, the malfunction prevention circuit 5 is used for both the data drive start signal SSPZ and the scan drive start signal GSPZ. However, the present invention is not limited to this. It is obvious that the present invention includes those that use the malfunction prevention circuit 5 for only one of them.
[0128]
【The invention's effect】
As described above, the display device of the present invention is disposed between the level shift means for level-shifting the data drive start signal input to the data drive circuit, and between the level shift means and the data drive circuit. And a delay correction unit that corrects a delay generated in the data drive start signal by a level shift operation by the level shift unit.
[0129]
Therefore, the delay occurring in the data drive start signal after the level shift is corrected by the delay correction means, and the corrected data drive start signal is given to the data drive circuit. For this reason, in the data drive circuit, malfunction due to delay of the data drive start signal is prevented. As a result, there is an effect that the steady current of the level shift means can be made sufficiently small without causing a malfunction of the data driving circuit.
[0130]
In the display device, it is preferable that the delay correction unit corrects a delay in OFF timing of the data drive start signal after the level shift.
[0131]
The ON timing delay caused in the data drive start signal due to the level shift in the level shift means can be caused by malfunctioning the data drive circuit by setting the input of the data drive start signal before the level shift to an appropriate timing. Since this can be avoided, the delay correction means corrects the OFF timing delay of the data drive start signal after the level shift, and has the effect of preventing malfunction of the data drive circuit.
[0132]
In the display device, it is preferable that the delay correction unit corrects the delay of the data drive start signal after the level shift by using a part of the signal generated in the data drive circuit.
[0133]
Therefore, the delay correction means corrects the delay of the data drive start signal after the level shift by using a part of the signal generated in the data drive circuit, so that a new correction signal can be input. There is an effect that the delay of the data drive start signal can be corrected without increasing the circuit scale.
[0134]
Further, as described above, the display device of the present invention is disposed between the level shift means for level-shifting the scan drive start signal input to the scan drive circuit, and between the level shift means and the scan drive circuit. And a delay correction unit that corrects a delay generated in the scanning drive start signal by the level shift operation by the level shift unit.
[0135]
Therefore, the delay occurring in the scan drive start signal after the level shift is corrected by the delay correction means, and the corrected scan drive start signal is given to the scan drive circuit. For this reason, in the scanning drive circuit, malfunction due to the delay of the scanning drive start signal is prevented. As a result, there is an effect that the steady current of the level shift means can be made sufficiently small without causing a malfunction of the scanning drive circuit.
[0136]
In the display device, it is preferable that the delay correcting unit corrects a delay in OFF timing of the scanning drive start signal after the level shift.
[0137]
The ON timing delay caused in the scanning drive start signal due to the level shift in the level shift means can be caused by causing the scan drive circuit to malfunction by setting the input of the scan drive start signal before the level shift to an appropriate timing. Since this can be avoided, the delay correction means corrects the OFF timing delay of the scan drive start signal after the level shift, and thus has an effect of preventing malfunction of the scan drive circuit.
[0138]
In the display device, it is preferable that the delay correction unit corrects the delay of the scan drive start signal after the level shift by using a part of the signal generated in the scan drive circuit.
[0139]
Therefore, the delay correction unit corrects the delay of the scan drive start signal after the level shift using a part of the signal generated in the scan drive circuit, so that a new correction signal can be input. There is an effect that the delay of the scanning drive start signal can be corrected without increasing the circuit scale.
[0140]
In the above display device, the display element, the plurality of data signal lines, the plurality of scanning signal lines, the data driving circuit, the scanning driving circuit, the level shifter unit, and the delay correcting unit may be formed on the same substrate. it can.
[0141]
Therefore, the level shifter means and the delay correction means can be manufactured in the same process as the data driving circuit, the scanning driving circuit, etc., and the manufacturing cost can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a schematic configuration of a level shifter circuit and a malfunction prevention circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a matrix display device according to the present embodiment, including the level shifter circuit and the malfunction prevention circuit.
FIG. 3 is a block diagram showing the configuration of the malfunction prevention circuit applied when the malfunction prevention circuit is used for correction of a data drive start signal.
FIG. 4 is a timing chart showing operations of a malfunction prevention circuit and a data drive circuit in a matrix display device using the malfunction prevention circuit.
FIG. 5 is a block diagram showing the configuration of the malfunction prevention circuit when the malfunction prevention circuit is used for correcting a scanning drive start signal.
FIG. 6 is a timing chart showing operations of the malfunction prevention circuit and the scan drive circuit in the matrix type display device using the malfunction prevention circuit.
FIG. 7 is a block diagram showing a configuration of a conventional matrix display device.
FIG. 8 is a block diagram showing a schematic configuration of a level shifter circuit used in the matrix display device.
FIG. 9 is a circuit diagram showing a configuration of a level shifter constituting the level shifter circuit.
FIG. 10 is a waveform diagram showing input and output of a signal level-shifted by the level shifter.
FIG. 11 is a block diagram showing a schematic configuration of a data driving circuit used in the matrix display device.
FIG. 12 is a timing chart showing the normal operation of the data driving circuit in the conventional matrix display device.
FIG. 13 is a block diagram showing a schematic configuration of a scan driving circuit used in the matrix display device.
FIG. 14 is a timing chart showing the normal operation of the scan driving circuit in the conventional matrix display device.
FIG. 15 is a circuit diagram showing a configuration of a level shifter constituting the level shifter circuit when designed to suppress steady current.
FIG. 16 is a timing chart showing an operation example when the data driving circuit in the conventional matrix type display device malfunctions.
FIG. 17 is a timing chart showing an operation example when a scan driving circuit in the conventional matrix type display device malfunctions.
FIG. 18 is a timing chart showing another operation example when the scan driving circuit in the conventional matrix type display device malfunctions.
[Explanation of symbols]
1 Matrix type display device (display device)
2 Data drive circuit
3 Scanning drive circuit
4 Level shifter circuit (level shift means)
5 Malfunction prevention circuit (delay correction means)

Claims (5)

In a display device comprising a display element, a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, and a data driving circuit and a scanning driving circuit for driving the data signal line and the scanning signal line, respectively.
Level shift means for level-shifting a data drive start signal input to the data drive circuit;
A delay correction unit that is disposed between the level shift unit and the data drive circuit and corrects a delay generated in the data drive start signal by a level shift operation by the level shift unit ;
The delay correction means corrects the delay of the off timing of the data drive start signal after the level shift, and the state changes before the rise of the second data operation clock after the data drive start signal becomes active. A flip-flop that changes an output according to a change in the state of the signal; and a logic gate that deactivates the data drive start signal according to a change in the output of the flip-flop. Display device.   The display device according to claim 1, wherein the delay correction unit corrects a delay of the data drive start signal after the level shift using a part of a signal generated in the data drive circuit. In a display device comprising a display element, a plurality of data signal lines and a plurality of scanning signal lines for driving the display element, and a data driving circuit and a scanning driving circuit for driving the data signal line and the scanning signal line, respectively.
Level shift means for level-shifting the scan drive start signal input to the scan drive circuit;
A delay correction unit that is disposed between the level shift unit and the scan drive circuit and corrects a delay generated in the scan drive start signal by a level shift operation by the level shift unit ;
The delay correction means corrects the delay of the off timing of the scan drive start signal after the level shift, and the state changes before the second scan operation clock rises after the scan drive start signal becomes active. A flip-flop that changes an output according to a change in the state of the signal; and a logic gate that deactivates the scan drive start signal according to a change in the output of the flip-flop. Display device. 4. The display device according to claim 3 , wherein the delay correction unit corrects a delay of the scan drive start signal after the level shift using a part of the signal generated in the scan drive circuit. Display elements, a plurality of data signal lines, a plurality of scanning signal lines, a data driving circuit, the scan driving circuit, a level shifter unit, and one of claims 1 to 4 delay correction means is characterized in that it is formed on the same substrate A display device according to any one of the above.

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