JP4003508B2 - Image composition apparatus and image composition method - Google Patents

Description

[0001]
[Field of the Invention]
The present invention relates to an image synthesizing apparatus and an image synthesizing method for synthesizing a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal indicating a synthesis position.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a large number of various video equipments are used in broadcasting stations depending on applications. Examples of such video equipment include, for example, a number of camera devices that capture video and output video signals, a switcher device that selects video to be broadcast as a program from video signals output from each camera device, and video signals Special effect devices that give various special effects can be mentioned.
[0003]
Among these, the special effect device is also called a DVE (Digital Video Effect) device, and by performing various digital processes on the video signal, for example, the video is rotated, enlarged / reduced, deformed, or moved. It has a function to perform various video changes accompanied with. The special effect device is very expensive because it has a function of imparting a variety of special effects to images.
[0004]
By the way, in a broadcasting station, for example, text such as a telop or a title is combined with video captured by a camera device, or video captured by another camera device is used as so-called picture-in-picture processing. Various image composition processes such as reduction and composition are performed. The video to be synthesized with the original video in this way is generally called “key”, and such image synthesis processing is generally called keying processing.
[0005]
Such image composition processing has been conventionally performed by a keyer device 500 as shown in FIG. As shown in FIG. 14, the keyer device 500 is a video signal including a background signal that is a video signal including a background image and an image to be combined (that is, an image to be combined and an image that is the contents of characters). A key fill signal and a key source signal which is a signal including mask information indicating an area to be combined are input.
[0006]
The keyer device 500 includes a first adder that adds the background signal and the key source signal, a first multiplier that multiplies the key fill signal by a predetermined constant K, and an output from the first adder. And a second multiplier for adding outputs from the first multiplier and the second multiplier. The constant K is an arbitrary value between 0 and 1 inclusive. The keyer device 500 performs the above-described processing to synthesize the background signal and the key fill signal based on the key source signal, and outputs a video signal in which the background image and the synthesis target image are synthesized.
[0007]
In FIG. 14, an independent keyer device 500 is illustrated as an apparatus for synthesizing an image based on a key source signal. However, in practice, a function realized by this keyer device 500 includes, for example, a plurality of keyer devices 500. It may be mounted on a switcher device that selectively outputs a video signal output from a camera device.
[0008]
[Problems to be solved by the invention]
By the way, in an actual broadcasting station, characters such as a telop and a title to be combined with a background image are created in advance by a computer device or the like, and a key source signal output from the computer device or another camera to be combined A scene occurs in which the key source signal generated according to the video signal from the apparatus is combined by the keyer apparatus as the program progresses.
[0009]
At this time, when a character such as a telop or a title created in advance or a video from another camera device is combined with a video (that is, a background image) output from the camera device, for example, the performer's face or other characters are added to these characters. It is assumed that an undesirable video is output due to overlapping characters and the like. Therefore, an operation of shifting the position of the key (video to be combined) within the screen is necessary as necessary so that the main part of the video does not overlap.
[0010]
However, in the conventional keyer device 500, since the images are synthesized by the simple process as described above, an operation of shifting the key position cannot be performed. For this reason, conventionally, for example, as shown in FIG. 14, a special effect device 501 is prepared in front of the keyer device 500, and the special effect device 501 shifts the key position by processing the key source signal and the key fill signal. The method is adopted.
[0011]
However, it is extremely inefficient and uneconomical to prepare a multi-function and expensive special effect device 501 simply for the purpose of shifting the key position. For this reason, it is strongly desired to realize the key position operation easily and at low cost.
[0012]
Therefore, the present invention has been made in view of the above-described conventional situation, and when synthesizing the first video signal and the second video signal based on the key source signal, it is possible to reduce the cost by a very simple method. An object of the present invention is to provide an image composition apparatus and an image composition method capable of realizing the key position operation.
[0013]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided an image composition device for synthesizing a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal indicating a synthesis position. In the apparatus, key source delay means for delaying and outputting the key source signal by a predetermined amount of time, the first video signal and the second video signal based on the key source signal delayed by the key source delay means By synthesizing with the video signal, by controlling the amount of time to be delayed by the signal synthesizing means for outputting the video signal including the image obtained by synthesizing the synthesis target image with the background image and the key source delay means And a control means for controlling the synthesis position of the second video signal.
[0014]
According to a ninth aspect of the present invention, there is provided an image synthesizing method for synthesizing a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal indicating a synthesis position. In the image composition method, a key source delay step for outputting the key source signal after delaying the key source signal by a predetermined amount of time, and the first video signal and the first signal based on the key source signal delayed by the key source delay step. By combining the two video signals, a signal synthesis step for outputting a video signal including an image obtained by synthesizing the synthesis target image with the background image and a time amount to be delayed in the key source delay step are controlled. And a control step for controlling the synthesis position of the second video signal.
[0015]
According to the present invention configured as described above, the synthesis position of the second video signal can be controlled by an extremely simple operation of delaying the key source signal by a predetermined amount of time.
[0016]
According to a second aspect of the present invention, in addition to the configuration of the first aspect, the image synthesizing apparatus includes a blanking interval and / or a folding region generated by the delay included in the key source signal output from the key source delay unit. Masking means for masking is further provided, and the signal synthesizing means synthesizes the first video signal and the second video signal based on the key source signal masked by the masking means.
[0017]
An image composition method according to a tenth aspect includes, in addition to the configuration according to the ninth aspect, a blanking interval and / or a folded region generated by the delay included in the key source signal output by the key source delay step. A masking step for masking is further included. In the signal synthesis step, the first video signal and the second video signal are synthesized based on the key source signal masked by the masking step.
[0018]
Thus, when the first video signal and the second video signal are synthesized, the blanking interval included in the key source signal and the influence of the aliasing area caused by delaying the key source signal are eliminated. Normal composition processing can be performed across the screen.
[0019]
According to a third aspect of the present invention, in addition to the configuration of the first aspect, the key source delay unit includes a memory unit that temporarily holds the contents of the key source signal, and a write and read operation with respect to the memory unit. And a memory control means for controlling the memory, and outputs the key source signal delayed by a predetermined amount of time by reading the content written in the memory means with a delay by the memory control means.
[0020]
According to an eleventh aspect of the present invention, in addition to the configuration of the ninth aspect, in the key source delay step, the contents of the key source signal are written to the memory means and temporarily held in the key source delay step. The key source signal delayed by a predetermined amount of time is output by reading out the content written in.
[0021]
In this case, for example, a conventional image synthesizing apparatus that realizes image movement by the frame buffer method requires a memory size of 3 fields, whereas a memory means prepares a memory size of a maximum of 2 fields. Just enough. Therefore, it is possible to reduce the amount of memory mounted and reduce the cost.
[0022]
According to a fourth aspect of the present invention, in addition to the configuration of the third aspect, the memory control unit stops writing to the memory unit during a blanking interval included in the key source signal.
[0023]
According to a twelfth aspect of the present invention, in addition to the configuration of the eleventh aspect, in the key source delay step, writing to the memory means is stopped for the blanking interval included in the key source signal. .
[0024]
As a result, blanking sections such as a horizontal blanking section and a vertical blanking section of the key source signal that are not required at the time of image synthesis are not written in the memory means, so that only the amount corresponding to the blanking section is prepared in the memory means. The memory size can be reduced and the cost can be further reduced.
[0025]
According to a fifth aspect of the present invention, in addition to the configuration of the first aspect, the key source delay means includes a first delay unit that delays the key source signal in units of horizontal lines of the image, and A second delay unit that delays the key source signal output from the first delay unit for each pixel of the image, and the first delay unit temporarily holds the content of the key source signal. Memory means and first memory control means for controlling writing to and reading from the first memory means, and the first memory control means has the above-described blanking interval included in the key source signal. The writing to the first memory means is stopped, and the contents written in the first memory means are read out with a delay in units of horizontal lines of the image. Second memory means for temporarily holding the contents of the key source signal output from the delay unit, and second memory control means for controlling writing to and reading from the second memory means, The memory control means reads the content written in the second memory means with a delay in units of pixels of the image.
[0026]
According to a thirteenth aspect of the image composition method, in addition to the configuration of the ninth aspect, the key source delay step writes the key source signal to the first memory means and temporarily holds the key source signal. A line delay step for reading out the contents written in the first memory means with a delay in units of horizontal lines of the image while stopping writing to the first memory means for the blanking interval included in A pixel delay step in which the contents of the key source signal read in the delay step are written and temporarily stored in the second memory means, and the contents written in the second memory means are read out in units of pixels of the image. And have.
[0027]
As a result, it is possible to reduce the memory size of the first memory means without writing blanking sections such as a horizontal blanking section and a vertical blanking section included in the key source signal to the first memory means. On the other hand, the complexity of writing and reading control caused by not writing the blanking interval to the memory means in this way is eliminated, and the key source signal is transmitted over the entire screen by an arbitrary amount of time by a simple memory control method. Can be delayed.
[0028]
According to a sixth aspect of the present invention, in addition to the configuration of the first aspect, the image synthesizing apparatus performs an interpolation process on an image included in the key source signal input to the signal synthesizing unit, thereby converting the key source signal into an image. Interpolation filter means for delaying by a pixel unit or less is further provided.
[0029]
In addition to the configuration of claim 9, the image composition method according to claim 14 performs the interpolation process on the image included in the key source signal used for the composition process in the signal composition step, thereby performing the key source. An interpolation step is further included for delaying the signal by less than a pixel unit of the image.
[0030]
As a result, the deviation between the key source signal and the second video signal can be adjusted with high accuracy in units of pixels or less, and high-quality image composition can be realized.
[0031]
According to a seventh aspect of the present invention, in addition to the configuration of the first aspect, the image synthesizing apparatus further includes a matte signal generating unit that generates a matte signal having a predetermined luminance component and chromaticity component, and the signal synthesizing unit includes: The mat signal generated by the mat signal generating means is synthesized as the second video signal.
[0032]
An image composition method according to a fifteenth aspect further includes a matte signal generation step for generating a matte signal having a predetermined luminance component and a chromaticity component in addition to the configuration according to the ninth aspect. In, the mat signal generated in the mat signal generation step is synthesized as a second video signal.
[0033]
Thereby, a predetermined luminance component and chromaticity component can be given to the key included in the key source signal, and this key can be synthesized with the background image included in the first video signal.
[0034]
According to an eighth aspect of the present invention, in addition to the configuration of the first aspect, the key fill delay means for delaying the key fill signal input from the outside by a predetermined amount and outputting the key fill signal, and the key fill delay means Key fill control means for controlling the synthesis position of the key fill signal by controlling the amount of time to be delayed, and the signal synthesis means synthesizes the key fill signal output from the key fill delay means as a second video signal. To do.
[0035]
According to a sixteenth aspect of the present invention, in addition to the configuration of the ninth aspect, the key fill delay step of delaying a key fill signal input from the outside by a predetermined amount of time and outputting the delayed key fill signal, and the key fill delay step And a key fill control step for controlling the synthesis position of the key fill signal by controlling the amount of time to be delayed. In the signal synthesis step, the key fill signal delayed by the key fill delay step is used as a second video signal. To synthesize.
[0036]
As a result, the key fill signal input as the second video signal can be delayed in the same manner as the key source signal, and the composition target image is shifted to an arbitrary position in the screen by a very simple configuration and method. Is possible.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention relates to an image synthesizing apparatus and an image synthesizing method for synthesizing a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal including information indicating a synthesis position. . And in this invention, when shifting a synthetic | combination position to arbitrary positions in a screen, it implement | achieves by delaying a key source signal only by predetermined amount of time, It is set as the structure which employs the so-called delay system. Therefore, in the following, an outline of the principle that enables the composition position to be shifted by this delay method will be described first.
[0038]
(1) Outline of principle of delay method
The key source signal is a signal that forms one frame by two fields of an odd field and an even field, and is a signal that forms image information for one screen by one frame, like other general video signals. .
[0039]
Therefore, as shown in FIG. 1, a memory having a size capable of holding a maximum of two fields of key source signals is prepared, and the input key source signals are sequentially stored in the memory. Then, the key source signal stored in the memory is read out with a delay by a time amount corresponding to a desired shift amount, thereby shifting the image information included in the key source signal to an arbitrary position in one screen. be able to.
[0040]
Specifically, for example, in FIG. 1, when the first field, the third field, and the fifth field are odd fields, and the second field and the fourth field are even fields, this corresponds to the first field. By delaying the key source signal within one field, the key information included in the key source signal can be shifted to an arbitrary position within the screen within the first field (odd field). Further, by delaying the key source signal in the first field within the next one field, the key information included in the key source signal is shifted to an arbitrary position within the screen within the second field (even field). Can do. Therefore, by delaying the key source signal by a maximum of two fields, the key information included in the key source signal is displayed in the screen over two fields (that is, one frame) of the odd field and the even field. It can be shifted to any position.
[0041]
On the other hand, for example, in the frame buffer system adopted for the purpose of manipulating an image with a conventional special effect device (DVE device) or the like, as shown in FIG. 2, a memory sufficient to store a video signal for one field each. First to third memories M1, M2, and M3 having sizes are prepared. Then, as shown in FIG. 3, the input video signal is sequentially stored for each field in the first to third memories M1, M2, and M3.
[0042]
In the frame buffer method, in order to shift the position of the image existing in the first field over one screen, as shown in FIG. 3, the video signals corresponding to the first and second fields are respectively displayed in the first and second fields. After writing to the second memories M1 and M2, it is necessary to perform a read process from the first memory M1 while writing a video signal corresponding to the third field to the third memory M3. That is, in the frame buffer method, it is necessary to prepare a memory size for three fields.
[0043]
Therefore, the delay method employed in the present invention can shift the position of the image information included in the key source signal with a smaller memory size compared to the frame buffer method employed conventionally.
[0044]
In addition, in the conventional frame buffer method, even if the image included in the video signal is moved by, for example, several pixels or several lines, a memory size of three fields is required. However, in the delay method, It has the advantage that it is sufficient to prepare a memory size corresponding to the maximum amount to move the image. That is, in the delay method, for example, when moving an image by several pixels or several lines, it is sufficient to prepare a memory size that temporarily holds a key source signal corresponding to the amount of movement. is there.
[0045]
In the delay method, an operation is performed in which an input key source signal is written in a memory and temporarily held, and then read in the order of writing after being delayed by a predetermined time. Therefore, when implementing this delay operation, a FIFO (First In First Out) type semiconductor memory that has been widely used in the past can be used. Such a semiconductor memory is extremely low cost and small in size as compared with a memory required for the frame buffer method, and can be used with a simple circuit configuration.
[0046]
In the delay method, when moving the position of the image information included in the key source signal, a series of key source signals are delayed in time, so that the delay is caused by a blanking interval or a delay included in the key source signal. An unnecessary area such as a folded area may appear at an unintended position on the screen. For this reason, it is desirable to prepare a circuit for removing such an unnecessary area. Details of this point will be described later.
[0047]
(2) Overall configuration of the keyer device
Next, as a specific embodiment of the present invention, a keyer device 10 having the configuration shown in FIG. 4 adopting the basic principle based on the delay method described above will be described. The keyer device 10 receives a background signal as a first video signal including a background image and a key fill signal as a second video signal including a synthesis target image. The keyer device 10 receives a key source signal including information indicating a synthesis position of the second video signal, and synthesizes the first video signal and the second video signal based on the key source signal. The apparatus performs a process of outputting a video signal including an image in which a synthesis target image is synthesized with a background image, that is, a so-called keying process.
[0048]
Here, the key source signal is a video signal including image information including characters such as titles and telops, and the key fill signal is a video signal including an image displayed inside these characters. Also, for example, when inserting other video into the video that is the background image, such as when performing so-called picture-in-picture processing, a video signal including the video to be inserted is input as the key fill signal, and the key source As a signal, a video signal indicating a region to be inserted (a video signal serving as mask information) is input. In addition, the keyer device 10 is a video signal having a predetermined luminance component and chromaticity component for the purpose of only adding a desired color or the like without adding a video to a character such as a title or a telop. A matte signal generating circuit is provided, and this matte signal can be selected as the second video signal.
[0049]
In the following description, the keyer device 10 which is a device exclusively performing the above-described keying process will be described as an example of the configuration of the present invention. The functions realized by the keyer device 10 are other video equipment such as a switcher device. It may be configured to be mounted on.
[0050]
As shown in FIG. 4, the keyer device 10 outputs a first A / D converter 20 that performs digital conversion processing on an input key source signal, and a first A / D converter 20 that outputs the key source signal. A key source delay circuit 21 that outputs a key source signal after being delayed by a predetermined amount of time, and a delay equal to or less than a pixel unit of an image by performing pixel interpolation processing on the key source signal output from the key source delay circuit 21 And a first masking circuit 23 that performs a process of removing unnecessary areas on the image included in the key source signal output from the first interpolator 22. ing. The first A / D converter 20, the key source delay circuit 21, the first interpolator 22, and the first masking circuit 23 are provided for the purpose of performing delay processing on the key source signal. In other words, a key source signal delay circuit system is configured.
[0051]
The keyer device 10 also applies a second A / D converter 24 that performs digital conversion processing to the input key fill signal, and the key fill signal output from the second A / D converter 24 for a predetermined time. A key fill delay circuit 25 that outputs the signal after being delayed by an amount, and a second interpolator 26 that applies a pixel interpolation process to the key fill signal output from the key fill delay circuit 25 to provide a delay equal to or less than the pixel unit of the image. And a second masking circuit 27 that performs a process of removing unnecessary areas on the image included in the key fill signal output from the second interpolator 26. The second A / D converter 24, the key fill delay circuit 25, the second interpolator 26, and the second masking circuit 27 are provided for the purpose of performing a delay process on the key fill signal. A key fill signal delay circuit system is configured.
[0052]
The keyer device 10 also includes a third A / D converter 28 that performs digital conversion processing on the input background signal, a mat signal generation circuit 29 that generates and outputs a mat signal, and a key fill signal delay. A selector 30 that selects which one of the key fill signal output from the circuit system and the mat signal output from the mat signal generation circuit 29 is used as the second video signal to be synthesized, and the background signal and selection A mixer circuit 31 for synthesizing the signal selected by the unit 30 based on the key source signal output from the key source signal delay circuit system, and an analog conversion process for the video signal output from the mixer circuit 31 A D / A converter 32 and a control circuit 33 for controlling the operation of each part constituting the keyer device 10 are provided.
[0053]
In this example, it is assumed that the signal input / output to / from the keyer device 10 is an analog signal, and various signal processing in the keyer device 10 is performed by digital processing. If the signal type matches the type of signal processing in the keyer device 10, the first to third A / D converters 20, 24, 28 and the D / A converter 32 are omitted as appropriate. May be configured.
[0054]
Further, the keyer device 10 includes a mat signal generation circuit 29, and either the mat signal output from the mat signal generation circuit 29 or the key fill signal output from the key fill signal delay circuit system is to be synthesized. The selector 30 can select whether to use the second video signal.
[0055]
Since the keyer device 10 has such a configuration, for example, even when a key fill signal is not input, the keyer device 10 combines a title, a telop, or the like input as a key source signal with a single color. It is possible to perform a simple synthesis process. However, the mat signal generation circuit 29 and the selector 30 may be omitted, and the mat signal may be input from the outside as a key fill signal even when the above-described combining process is performed.
[0056]
The mixer circuit 31 converts the background signal as the first video signal including the background image and the second video signal (that is, the key fill signal or the matte signal) selected as the synthesis target by the selector 30 into the key source signal. Synthesis processing is performed based on the key source signal output from the delay circuit system.
[0057]
The mixer circuit 31 includes, for example, a first adder that inverts the key source signal, a first multiplier that multiplies the second video signal by the key source signal K, and a first adder. A second multiplier that multiplies the output and the first video signal, and a second adder that adds the outputs from the first multiplier and the second multiplier. The key source signal K is normalized to 0 or more and 1 or less. By this normalization, for example, when the key source signal is 8 bits wide, the value 0 becomes “0.0” and the value 255 becomes “1.0”. The output from the first adder can be expressed as [1-K].
[0058]
The mixer circuit 31 synthesizes the first video signal and the second video signal based on the key source signal by the adder and the multiplier, thereby the background image included in the first video signal and the second video signal. It is configured to output a video signal including an image synthesized with a synthesis target image included in the video signal. Note that the mixer circuit 31 is not limited to being configured by an adder or a multiplier as described above as long as a similar function can be realized, and has a function of performing image synthesis processing by various digital circuits or analog circuits. It may be realized.
[0059]
The control circuit 33 has a function of controlling the operation of each unit by outputting various control signals to each unit constituting the keyer device 10. The control unit 33 is configured by a semiconductor chip such as a CPU (Central Processing Unit). Although not shown, the control circuit 33 is connected to an operation switch for inputting an operation from the user. The control circuit 33 performs control of delay applied to the key source signal and key fill signal, control of the mat signal generated by the mat signal generation circuit 29, control of synthesis processing in the mixer circuit 31, and the like according to a request from the user. Do.
[0060]
By the way, the keyer device 10 has the key source signal delay circuit system and the key fill signal delay circuit system as described above. The key source signal and the key fill signal are independently provided by the respective delay circuit systems. It is possible to delay by a predetermined amount of time. As a result, the keyer device 10 can independently move the information indicating the combining position included in the key source signal and the combining target image included in the key fill signal to arbitrary positions on the screen.
[0061]
However, the keyer device 10 can eliminate the need for the key fill signal delay circuit system when the composition target image included in the key fill signal is not controlled to move within the screen.
[0062]
Further, in the keyer device 10, the key source signal delay circuit system and the key fill signal delay circuit system have the same configuration, and have the same functions and effects.
[0063]
For the above reasons, in the following, each part will be described with particular attention to the key source signal delay circuit system, and the key fill signal delay circuit system will be described. It will be omitted.
[0064]
Each part constituting the key fill signal delay circuit system, the second A / D converter 24, the key fill delay circuit 25, the second interpolator 26, and the second masking circuit 27 are each a key source signal delay circuit. It corresponds to each part constituting the system, the first A / D converter 20, the key source delay circuit 21, the first interpolator 22, and the first masking circuit 23.
[0065]
(3-1) First configuration example of key source delay circuit
In the following, a specific configuration example of the key source delay circuit 21 among the components constituting the key source signal delay circuit system will be described with reference to the first configuration example shown in FIG.
[0066]
For example, as shown in FIG. 5, the key source delay circuit 21 includes a memory 50 configured by a semiconductor memory element, and a counter 51 that outputs a write address (Write address) and a read address (Read address) to the memory 50. And can be configured.
[0067]
The memory 50 has a memory capacity sufficient to temporarily hold pixel information corresponding to the maximum delay applied to the key source signal. That is, when the information related to the composite position included in the key source signal is moved in the horizontal direction of the screen by, for example, 10 pixels, the memory 50 needs to have sufficient memory capacity to temporarily hold the pixel information for 10 pixels. For example, when moving in the vertical direction of the screen by 5 lines, the memory 50 needs to have a sufficient memory capacity to temporarily hold pixel information for 5 lines.
[0068]
The counter 51 sequentially counts up the write address and the read address at a predetermined cycle, and outputs the write address and the read address to the memory 50. The memory 50 writes the input key source signal to the write address specified by the counter 51, and sequentially outputs the contents stored at the read address specified by the counter 51. At this time, the access to the same address in the memory 50 is in the order in which the write process is performed after the data read process is performed.
[0069]
Here, for example, a case where the key source signal (output signal) output with respect to the input key source signal (input signal) is delayed by n pixels will be described more specifically. In this case, as shown in FIG. 6, the write address and the read address output by the counter 51 are counted up from “1” to “n”, respectively. Then, in the memory 50, the area indicated by the hatched portion in the figure in the input signal is temporarily held, and the held contents are read out with a delay of n pixels as shown in FIG. Become. That is, the output signal is output with a delay of n pixels with respect to the input signal.
[0070]
For the reason described above, in order to move the key information included in the key source signal to an arbitrary position in the screen, the key source delay circuit 21 causes the key source signal to be transmitted for a maximum of one frame (that is, two fields). It suffices if it can be delayed by (min). Therefore, the memory size of the memory 50 provided in the key source delay circuit 21 needs to be prepared as long as it is sufficient to temporarily hold the key source signals for two fields.
[0071]
(3-2) Second configuration example of key source delay circuit
[0072]
In the first configuration example of the key source delay circuit 21 described above, all input key source signals are temporarily stored in the memory 50 sequentially. However, the actual key source signal includes a blanking section such as a horizontal blanking section or a vertical blanking section, and this blanking section becomes unnecessary for the image composition processing. For this reason, in the first configuration example, an unnecessary blanking section included in the key source signal is also written in the memory 50, which causes a slight waste from the viewpoint of the efficiency of using the memory area.
[0073]
Therefore, hereinafter, a second configuration example of the key source delay circuit 21 in which this point is improved will be described with reference to FIG.
[0074]
The key source delay circuit 21 according to the second configuration example has a basic configuration equivalent to that of the first configuration example illustrated in FIG. 5, while the blanking included in the input signal as illustrated in FIG. 7. Address control is performed so that the section is not written in the memory 50. In FIG. 7, the horizontal blanking interval that appears in the input signal for each line of the screen is indicated by a bold line. The counter 51 receives a write inhibit signal whose signal level is high at a period corresponding to the horizontal blanking interval. While the signal level of the write inhibit signal is high, the counter 51 sets the write address. It is configured not to count up.
[0075]
In the example shown in FIG. 7, it is assumed that the input signal is output after being delayed by n pixels as in the case shown in FIG. 6, and the counter 51 counts up the write address between 1 and n. It shall be. If, for example, the value of the write address is “a” when the write inhibit signal becomes high during the address count-up, the value of the write address is not increased while the write inhibit signal is high. That is, during this time, writing to the memory 50 is not performed. Then, when the signal level of the write inhibit signal returns to low, the counter 51 resumes counting up the write address from the value “a + 1”, assuming that the unnecessary blanking interval has ended.
[0076]
Since the key source delay circuit 21 in the present example configured as described above is configured to stop writing to the memory 50 in the blanking interval included in the key source signal, only the blanking interval is included. The memory size prepared in the memory 50 can be reduced.
[0077]
(3-3) Third configuration example of key source delay circuit
[0078]
By the way, in the second configuration example of the key source delay circuit 21 described above, the write operation to the memory 50 is stopped during the period corresponding to the blanking interval, and thus the read operation from the memory 50 is appropriately controlled. Thus, it is necessary to prevent a problem such as reading from an address that has not yet been written. In order to realize such address control, complicated logic circuits and address processing are required.
[0079]
Therefore, in the following, a third configuration example of the key source delay circuit 21 capable of realizing the delay of the key source signal with a simple configuration without requiring a complicated logic circuit and address processing will be described with reference to FIG. .
[0080]
As shown in FIG. 8, the key source delay circuit 21 according to the third configuration example includes a first memory 60 that performs delay processing on the input key source signal in units of image lines, and the first memory 60. A first counter 61 that outputs a write address and a read address for the memory 60; a second memory 62 that applies a delay process to the key source signal read from the first memory 60 in pixel units of the image; And a second counter 63 for outputting a write address and a read address for the second memory. That is, in the key source delay circuit 21 according to this example, the first memory 60 and the first counter 61 constitute a line delay unit that delays the key source signal in units of image lines. The memory 62 and the second counter 63 constitute a pixel delay unit that delays the key source signal in units of pixels within one line of the image.
[0081]
In the line delay unit, as described in the second configuration example, the write inhibit signal whose signal level becomes high corresponding to the blanking interval included in the key source signal is sent to the first memory 60 and the first memory 60. As shown in FIG. 9, the writing to the first memory 60 is stopped during the period when the signal level of the write signal is high. As a result, the writing process is performed on the first memory 60 only in the period indicated by the hatched portion in FIG. 9, that is, in the period in which an effective signal is included in the input signal instead of the blanking period. In FIG. 9, the horizontal blanking interval that appears in the input signal for each line of the screen is indicated by a bold line.
[0082]
In this line delay unit, the write inhibit signal also functions as a read inhibit signal that inhibits reading from the first memory 60, and the signal level of the read inhibit signal (that is, the write inhibit signal) is high. During the period, the reading process from the first memory 60 is stopped. As a result, the reading process is performed from the first memory 60 only during the period indicated by the hatched portion in FIG.
[0083]
The reading process from the first memory 60 is configured to be read with a delay in units of one line of the screen by being address-controlled by the first counter 61. More specifically, for example, the signals written to the first memory 60 at time A shown in FIG. 9 are delayed by one line, two lines, or three lines from this time, respectively. The data is read at B, time C, or time D, and is not read at an intermediate time.
[0084]
As described above, since the line delay unit is limited to the process of delaying the key source signal in units of lines, the signal level is controlled at the same timing when the writing process and the reading process with respect to the first memory 60 are controlled. A write inhibit signal and a read inhibit signal that become high can be used, and these inhibit signals can be shared. Since the writing process and the reading process for the first memory 60 are performed based on the prohibition signal, it is not necessary to provide a complicated logic circuit and address control, and the key source signal is expressed in line units with a very simple configuration. Can be delayed.
[0085]
In the line delay unit, the unnecessary blanking period included in the key source signal is not written to the first memory 60, so that the memory size required for the first memory 60 is reduced. can do.
[0086]
On the other hand, in the pixel delay unit provided in the subsequent stage of the line delay unit, the key source signal is delayed in units of pixels within one line of the image. That is, in the key source delay circuit 21 according to the third configuration example, after the key information included in the key source signal is moved in units of lines in the vertical direction in the screen by the delay processing in the line delay unit, the pixel delay is performed. The key information is moved in the horizontal direction within the screen in units of pixels by the processing in the unit.
[0087]
When the key source delay circuit 21 is configured as described above, the maximum movement amount of the key information in the line delay unit is (2 fields-1 line), and the maximum movement amount of the key information in the pixel delay unit is one line. It becomes. Here, since the ratio of the horizontal blanking interval in the key source signal is about 15% in most signal formats, the line delay unit should reduce the memory size by at least the horizontal blanking interval. Is possible. Therefore, the total memory size M required for the first memory 60 and the second memory 62 in the key source delay circuit 21 according to the third configuration example is expressed as shown in Equation 1 below for convenience. be able to.
M = (2 fields-1 line) × (1-0.15) + (1 line) (Formula 1)
[0088]
That is, as in this example, the key source delay circuit 21 has a two-stage configuration including a line delay unit and a pixel delay unit, and performs a delay process in units of lines and pixels, respectively, while stopping the writing process for the blanking interval. By doing so, it is possible to reduce about 15% of the memory size required to hold the key source signals for (2 fields-1 line). Although this memory size reduction effect is not so large as a reduction amount, for example, when the first memory 60 is configured using a standard FIFO type semiconductor memory, one semiconductor memory is sufficient. There may be a significant advantage from the viewpoint of mounting whether there is a need for two memory sizes or two memory sizes.
[0089]
The pixel delay unit only needs to perform delay processing within a maximum of one line, and the memory size required for the second memory 62 is a memory size that can temporarily hold a key source signal for one line at maximum. It is enough to prepare. However, the pixel delay unit may be capable of performing delay processing with one or more n lines.
[0090]
(4) Interpolation process in interpolator
Next, pixel interpolation processing in the first interpolator 22 among the respective parts constituting the key source signal delay circuit system in the keyer device 10 will be described.
[0091]
In the keyer device 10, the key information can be moved to an arbitrary position in the screen in units of image pixels by the key source delay circuit 21, but the first interpolator 22 is controlled by the key source delay circuit 21. This is provided for the purpose of moving the key information included in the key source signal in units of pixels or less by applying delay processing in units of pixels or less to the delayed key source signal.
[0092]
The keyer device 10 may be configured without the first interpolator 22. However, by providing the first interpolator 22, the key information included in the key source signal can be increased. It becomes possible to perform a moving operation with high accuracy. As a result, the key source signal and the key fill signal can be positioned with higher accuracy, and the image composition process can be performed. In particular, when these key source signal and key fill signal are input as analog signals, there is almost always a slight shift between the signals. It is extremely effective to adjust the position. In addition, the high-precision alignment operation realized by the first interpolator 22 is also effective when the key positions are aligned with high accuracy with respect to the background image included in the background signal.
[0093]
As the pixel interpolation process performed by the first interpolator 22, various conventionally known interpolation processes can be adopted. In the following, an example of this pixel interpolation process will be described with reference to FIGS. This will be specifically described with reference to FIG.
[0094]
Here, each pixel (pixel) included in the key source signal input to the first interpolator 22 is schematically shown as shown in FIG. In the following, regarding the process of moving the pixel located at the point A shown in FIG. 10 to the position of the point A ′, information on the pixels at the four points (points A, B, C, D) located near the pixel at the point A Based on the above, consider the case of performing a so-called 2 × 2 linear interpolation process.
[0095]
At this time, when it is assumed that a point A ″ that is symmetric with respect to the point A ′ with respect to the point A has a positional relationship as shown in FIG. 11 with respect to the other points A, B, C, and D, Information about the pixel at the point A ″ is obtained by the following equation 2.
A ″ = ((6 × A + 2 × B) × 3 + (6 × D + 2 × C) × 5) / 64 (Formula 2)
[0096]
Next, an operation for replacing the information related to the pixel at the point A with the information related to the virtual pixel at the point A ″, that is, an operation shown in Expression 3 below is performed.
[0097]
A = A '' (Formula 3)
[0098]
Thereby, the pixel of the point A is moved to the position of the point A ′. Then, by performing this series of processing on all the pixels included in the key source signal, the image represented by the rectangle indicated by the solid line in FIG. 10 reaches the position represented by the rectangle indicated by the dotted line in FIG. It is moved with a movement amount of less than a pixel unit.
[0099]
In the above description, the pixel interpolation process in the first interpolator 22 has been described by taking an example of an interpolation process using 4 points. Various conventionally known interpolation processes may be employed. The first interpolator 22 may adopt a method of performing interpolation without referring to information on other pixels for each pixel, but performing interpolation with reference to information on other pixels. Thus, the frequency characteristics can be improved. The first interpolator 22 can be constituted by various interpolation filter circuits that have been widely used conventionally.
[0100]
(5) Masking process in the masking circuit
Next, masking processing in the first masking circuit 23 among the respective parts constituting the key source signal delay circuit system in the keyer device 10 will be described below.
[0101]
In the keyer device 10, the key source signal is delayed by the key source delay circuit 21, thereby moving the position of the key information included in the key source signal. For this reason, as shown in FIG. 12, the key source signal after the delay process has a horizontal blanking period or a vertical blanking period included in the key source signal, or a folded area caused by delaying the key source signal. It becomes. In FIG. 12, an effective screen area of the image included in the key source signal is represented by a rectangle surrounded by a dotted line in the figure, and a folded area caused by a delay is indicated by a hatched portion.
[0102]
These blanking sections and aliasing areas that appear on the screen after the delay process are not only unnecessary in the image composition process, but also the parts other than the key information used in the image composition process appear in the effective screen area. There is a risk that it will be difficult to perform correctly.
[0103]
Therefore, the keyer device 10 is provided with a first masking circuit 23 for the purpose of removing these unnecessary areas by masking. In the first masking circuit 23, a folded portion where an unnecessary portion appears is calculated based on the amount of movement performed on the key source signal by the delay processing, and the key source signal is calculated for the calculated folded portion. A process for setting the value to “0” (that is, a process for setting no key) may be performed.
[0104]
The second masking circuit 23 having the same function as the first masking circuit 23 may perform the same processing as described above. However, the second masking circuit 23 calculates the calculated aliasing. A process for setting the key fill signal to black (that is, a process for setting no image to be combined) is performed on the part. However, the second masking circuit 23 is not necessarily provided.
[0105]
Here, the actual masking process in the first masking circuit 23 will be described with reference to FIG. FIG. 13 is a schematic diagram focusing on the time axis, focusing on the processing performed for each line of the image. As shown in FIG. 13, the first masking circuit 23 compares the key source signal before the delay process with the key source signal after the delay process, and considers the delay amount and an unnecessary section such as a blanking section. Thus, a masking signal indicating a region to be masked is generated. In FIG. 13, a portion of the key source signal excluding the blanking interval is illustrated by a white rectangular portion, and a region to be masked indicated by the masking signal is illustrated by a bold line. Then, by setting the value of the portion indicated by the masking signal in the delayed key source signal to “0”, the key source signal with this portion masked is output.
[0106]
The keyer device 10 includes the first masking circuit 23 that performs the masking process as described above, thereby effectively removing unnecessary parts such as a blanking section and a turn-back area included in the key source signal after the delay process. Therefore, it is possible to prevent unintentional composition from being performed during the image composition process, and normal composition processing can be realized over all the screens.
[0107]
Note that the masking processing employed in the first masking circuit 23 is not limited to the above-described method, and other various methods can be employed. Further, the first masking circuit 23 can be easily realized by combining various types of circuits that have been widely known.
[0108]
(6) Supplement
In the above description, the key source delay circuit 21, the first interpolator 22, and the first masking circuit 23 have been described in detail with a focus on the key source signal delay circuit system in the keyer device 10. The key fill delay circuit 25, the second interpolator 26, and the second masking circuit 27 that are provided in the key fill signal delay circuit system corresponding to the part can have the same configuration. The same action / effect can be expected for the key fill signal.
[0109]
However, in the keyer device 10, the key fill signal delay circuit system is not necessarily provided. For example, when the composition target image included in the key fill signal is not controlled to move in the screen, or for example, characters such as a telop or a title are used as key information. The key fill signal delay circuit system is omitted when the key source signal including the signal is input and the mat signal generated by the mat signal generating circuit 29 is synthesized with the background signal based on the key information. It is good also as the structure which carried out.
[0110]
【The invention's effect】
According to the present invention, the synthesis position of the second video signal can be controlled by an extremely simple operation of delaying the key source signal by a predetermined amount of time. Such a delay operation can be realized by temporarily holding the key source signal and extracting it after a predetermined time. For example, the delay operation is realized by a delay circuit using a general-purpose FIFO (First In First Out) type semiconductor memory. be able to. For this reason, for example, it is not necessary to use a dedicated ASIC (Application Specific Integrated Circuit) or the like, and a relatively small semiconductor memory can be used at a low cost. Further, the present invention shifts the position of the key included in the key source signal within the screen by a so-called delay method, so that only the memory size for two fields is required at most, and the memory size for three fields is required. Compared to the frame buffer method, the cost can be reduced from the viewpoint of memory size.
[Brief description of the drawings]
FIG. 1 is a schematic diagram for explaining a basic principle of a delay method employed in the present invention.
FIG. 2 is a schematic diagram for explaining a configuration of a memory required in a frame buffer method compared with a delay method employed in the present invention.
FIG. 3 is a schematic diagram for explaining a memory utilization method in a frame buffer method compared with a delay method employed in the present invention.
FIG. 4 is a schematic functional block diagram showing a configuration example of a keyer device shown as an embodiment of the present invention.
FIG. 5 is a schematic diagram showing a first configuration example of a key source delay circuit provided in the keyer device.
FIG. 6 is a schematic diagram for explaining delay processing performed on a key source signal by a first configuration example of a key source delay circuit provided in the keyer device;
FIG. 7 is a schematic diagram for explaining delay processing performed on a key source signal by a second configuration example of a key source delay circuit provided in the keyer device;
FIG. 8 is a schematic diagram showing a third configuration example of a key source delay circuit provided in the keyer device.
FIG. 9 is a schematic diagram for explaining line delay processing performed on a key source signal by a third configuration example of a key source delay circuit provided in the keyer device;
FIG. 10 is a schematic diagram for explaining pixel interpolation processing in an interpolator provided in the keyer device.
FIG. 11 is a schematic diagram for explaining pixel interpolation processing in an interpolator provided in the keyer device.
FIG. 12 is a schematic diagram for explaining that a masking process is required in a masking circuit provided in the keyer device.
FIG. 13 is a schematic diagram for explaining an example of masking processing in a masking circuit provided in the keyer device.
FIG. 14 is a schematic diagram for explaining an apparatus configuration conventionally used when performing image composition processing.
[Explanation of symbols]
10 Keyer Device, 21 Key Source Delay Circuit, 22 First Interpolator, 23 First Masking Circuit, 25 Key Fill Delay Circuit, 26 Second Interpolator, 27 Second Masking Circuit, 29 Matt Signal Generation Circuit , 30 selector, 31 mixer circuit, 33 control unit, 50 memory, 51 counter, 60 first memory, 61 first counter, 62 second memory, 63 second counter

Claims (16)

In an image synthesis device that synthesizes a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal indicating a synthesis position.
The memory means having a size corresponding to the maximum movement amount defined within two fields is used, and the key source signal is delayed and output by a predetermined amount of time arbitrarily specified within the range of the maximum movement amount. A key source delay means;
By synthesizing the first video signal and the second video signal based on the key source signal delayed by the key source delay means, an image in which the synthesis target image is synthesized with the background image is obtained. Signal synthesizing means for outputting a video signal including:
An image synthesizing apparatus comprising: control means for controlling a synthesis position of the second video signal by controlling an amount of time delayed by the key source delay means. Masking means for masking a blanking interval and / or a folded area caused by the delay included in the key source signal output from the key source delay means,
2. The image synthesizing apparatus according to claim 1, wherein the signal synthesizing unit synthesizes the first video signal and the second video signal based on the key source signal masked by the masking unit. . The key source delay means further comprises memory control means for controlling writing and reading to the memory means , and delays the contents of the key source signal written in the memory means by a predetermined amount of time by the memory control means. The image synthesizing device according to claim 1, wherein the image synthesizing device is read out. 4. The image synthesizing apparatus according to claim 3, wherein the memory control means stops writing to the memory means for a blanking interval included in the key source signal. The key source delay means includes a first delay unit that delays the key source signal in units of horizontal lines of the image, and a second delay unit that delays the key source signal output from the first delay unit in units of pixels of the image. And a delay portion of
The first delay unit includes first memory means for temporarily holding the contents of the key source signal, and first memory control means for controlling writing and reading to the first memory means,
The first memory control means stops writing to the first memory means for the blanking interval included in the key source signal and changes the contents written in the first memory means to a horizontal line of an image. Read delayed by unit,
The second delay unit includes a second memory unit that temporarily holds a content of the key source signal output from the first delay unit, and a second memory unit that controls writing and reading to the second memory unit. Memory control means,
2. The image synthesizing apparatus according to claim 1, wherein the second memory control means reads the content written in the second memory means with a delay in units of pixels of the image. An interpolation filter means for delaying the key source signal by a pixel unit or less by performing interpolation processing on an image included in the key source signal input to the signal synthesizing means. The image composition apparatus according to 1. Matte signal generating means for generating a matte signal having a predetermined luminance component and chromaticity component,
2. The image synthesizing apparatus according to claim 1, wherein the signal synthesizing unit synthesizes the mat signal generated by the mat signal generating unit as a second video signal. Key fill delay means for delaying the key fill signal input from the outside by a predetermined amount of time, and outputting,
Further comprising key fill control means for controlling the synthesis position of the key fill signal by controlling the amount of time delayed in the key fill delay means,
2. The image synthesizing apparatus according to claim 1, wherein the signal synthesizing unit synthesizes the key fill signal output from the key fill delay unit as a second video signal. In an image synthesis method for synthesizing a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal indicating a synthesis position.
The memory means having a size corresponding to the maximum movement amount defined within two fields is used, and the key source signal is delayed and output by a predetermined amount of time arbitrarily designated within the range of the maximum movement amount. A key source delay step;
By synthesizing the first video signal and the second video signal based on the key source signal delayed by the key source delay step, an image obtained by synthesizing the synthesis target image with the background image is obtained. A signal synthesis step of outputting a video signal including:
And a control step of controlling a synthesis position of the second video signal by controlling an amount of time delayed in the key source delay step. A masking step for masking a blanking interval and / or a folded region caused by the delay included in the key source signal output by the key source delay step;
10. The image composition according to claim 9, wherein, in the signal synthesis step, the first video signal and the second video signal are synthesized based on the key source signal masked in the masking step. Method. The key source delay step, according to claim 9, characterized in that for outputting a key source signal delayed by a predetermined amount of time by reading by delaying the contents of the written the key source signal to said memory means Image composition method. 12. The image synthesizing method according to claim 11, wherein, in the key source delay step, writing to the memory means is stopped for the blanking interval included in the key source signal. The key source delay step writes the key source signal to the first memory means and temporarily holds it, and stops writing to the first memory means for the blanking interval included in the key source signal, A line delay step for reading out the contents written in the first memory means by delaying in units of horizontal lines of the image, and the contents of the key source signal read in the line delay step are written in the second memory means. 10. The image synthesizing method according to claim 9, further comprising: a pixel delay step of temporarily holding and reading out the contents written in the second memory means with a delay for each pixel of the image. The method further includes an interpolation step of delaying the key source signal by a pixel unit or less by performing an interpolation process on an image included in the key source signal used for the synthesis process in the signal synthesis step. The image composition method according to claim 9. A mat signal generating step for generating a mat signal having a predetermined luminance component and chromaticity component;
10. The image synthesizing method according to claim 9, wherein in the signal synthesizing step, the mat signal generated in the mat signal generating step is synthesized as a second video signal. A key fill delay step for outputting a key fill signal input from outside by delaying a predetermined amount of time; and
A key fill control step of controlling a composite position of the key fill signal by controlling an amount of time delayed in the key fill delay step,
10. The image synthesizing method according to claim 9, wherein in the signal synthesizing step, the key fill signal delayed by the key fill delay step is synthesized as a second video signal.

Images