JP2003298934A - Image compositing apparatus and image compositing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize the positioning a key to composite on a background image at a low cost by a simple method. <P>SOLUTION: In the case that a mixer circuit 31 applies composition processing to a background signal including a background image and a key fill signal including a composition object image on the basis of a key source signal, a key source delay circuit 21 delays the key source signal by a prescribed time amount. Thus, the position of the key can be moved corresponding to the delayed time. The moving operation of the key position by delaying the key source signal as above can be realized with a fewer memory size in comparison with that of a frame buffer system. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image synthesizing apparatus and image for synthesizing a first video signal including a background image and a second video signal including a synthesis target image based on a key source signal indicating a synthesis position. It relates to a synthetic method.

[0002]

2. Description of the Related Art Conventionally, a large number of various video equipments have been used in broadcasting stations according to their applications. Examples of such video equipment include, for example, a number of camera devices that capture video and output video signals, a switcher device that selects video to be broadcast as a program from the video signals output from each camera device, and video signals. A special effect device that gives various special effects to

Of these, the special effect device is a DVE (Digi
tal video effect) device, which performs various digital processing on video signals to rotate, enlarge / reduce, or transform the video, or perform various video changes accompanied by movement. have. The special effect device is very expensive because it has a function of imparting various kinds of special effects to images in this way.

By the way, in a broadcasting station, characters such as a telop and a title are combined with a video image taken by a camera device, or a so-called picture
As the in-picture process, various image combining processes such as reducing and combining images captured by other camera devices are performed. The image to be combined with the original image in this way is generally called a "key", and such an image combining process is generally called a keying process.

Conventionally, such an image synthesizing process is performed by a keyer device 500 as shown in FIG. In the keyer device 500, as shown in FIG.
A background signal, which is a video signal including a background image, a key fill signal, which is a video signal including an image to be combined (that is, an image to be combined or an image that is the contents of characters), and so-called mask information indicating an area to be combined. A key source signal, which is a signal including the key source signal, is input.

The keyer device 500 includes a first adder for adding a background signal and a key source signal, a first multiplier for multiplying a key fill signal by a predetermined constant K, and a first adder. A constant (1-
K), a second multiplier, a first multiplier and a second multiplier
And a second adder for adding the outputs from the multipliers. The constant K is an arbitrary value between 0 and 1 inclusive. The keyer device 500 performs the above-described processing to synthesize the background signal and the key fill signal based on the key source signal, and outputs a video signal in which the background image and the synthesis target image are synthesized.

In FIG. 14, an independent keyer device 500 is illustrated as a device for synthesizing an image based on a key source signal, but in reality, the function realized by this keyer device 500 is For example, it may be mounted on a switcher device that selectively outputs video signals output from a plurality of camera devices.

[0008]

By the way, in an actual broadcasting station, characters such as telops and titles to be combined with a background image are created in advance by a computer device or the like, and a key source signal output from this computer device is generated. Alternatively, a situation occurs in which a key source signal generated in accordance with a video signal from another camera device to be combined is combined by the keyer device as the program progresses.

At this time, when characters such as telops and titles created in advance or images from other camera devices are combined with the image output from the camera device (that is, the background image), the characters such as the face of the performer are combined with these characters. It is expected that unfavorable images will be output due to overlapping of characters and other characters. Therefore, it is necessary to shift the positions of the keys (images to be combined) on the screen as necessary so that the main parts of the images do not overlap.

However, in the conventional keyer device 500, since the images are combined by the above-described simple process, it is not possible to perform an operation such as shifting the key position. Therefore, conventionally, for example, as shown in FIG. 14, the special effect device 5 is provided before the keyer device 500.
01 is prepared, and the special effect device 501 processes the key source signal and the key fill signal to shift the position of the key.

However, it is extremely inefficient and uneconomical to prepare a multifunctional and expensive special effect device 501 for the purpose of only shifting the key position. Therefore, it is strongly desired to realize the key position operation simply and at low cost.

Therefore, the present invention has been made in view of the above-mentioned conventional circumstances, and when synthesizing the first video signal and the second video signal based on the key source signal,
It is an object of the present invention to provide an image synthesizing apparatus and an image synthesizing method capable of realizing a key position operation at an extremely simple method and at low cost.

[0013]

According to a first aspect of the present invention, there is provided an image synthesizing device for a key for indicating a synthesizing position of a first video signal including a background image and a second video signal including a synthesizing target image. In an image synthesizing device for synthesizing based on a source signal, a key source delay means for delaying and outputting the key source signal by a predetermined amount of time, and the key source signal delayed based on the key source signal delayed by the key source delay means. 1
Of the video signal and the second video signal to output a video signal including an image in which the background image is combined with the image to be combined, and a delay in the key source delay unit. And a control means for controlling the composite position of the second video signal by controlling the amount of time to be performed.

According to a ninth aspect of the present invention, there is provided an image synthesizing method in which a first video signal including a background image and a second video signal including a synthesizing target image are based on a key source signal indicating a synthesizing position. In the image synthesizing method of synthesizing by the above, the first video signal is generated based on a key source delay step of delaying and outputting the key source signal by a predetermined amount, and a key source signal delayed by the key source delay step. And by combining the second video signal with
A signal combining step of outputting a video signal including an image in which the background image is combined with the combination target image, and a combination position of the second video signal by controlling the amount of time delayed in the key source delay step. And a control step for controlling.

According to the present invention configured as described above,
The combining position of the second video signal can be controlled by an extremely simple operation of delaying the key source signal by a predetermined amount of time.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the image synthesizing apparatus is caused by a blanking interval and / or a delay included in the key source signal output from the key source delay means. The signal synthesis means further comprises masking means for masking the folded region, and the signal synthesis means synthesizes the first video signal and the second video signal based on the key source signal masked by the masking means.

An image synthesizing method according to claim 10 is
In addition to the configuration according to claim 9, further comprising a masking step of performing a masking process on a blanking interval included in the key source signal output by the key source delaying step and / or a folding region caused by a delay,
In the signal synthesizing step, the first video signal and the second video signal are synthesized based on the key source signal masked by the masking step.

Thus, when the first video signal and the second video signal are combined, the blanking interval included in the key source signal and the influence of the folding region caused by delaying the key source signal are eliminated. By doing so, the normal synthesizing process can be performed over the entire screen.

According to a third aspect of the present invention, in addition to the configuration of the first aspect, the key source delay means includes a memory means for temporarily holding the contents of the key source signal, and the memory means. A memory control means for controlling writing and reading is provided, and the content written in the memory means is delayed and read by the memory control means to output a key source signal delayed by a predetermined amount of time.

An image synthesizing method according to claim 11 is
In addition to the configuration according to claim 9, in the key source delay step, the contents of the key source signal are written into the memory means and temporarily held, and the contents written in the memory means are delayed and read out. The key source signal delayed by a predetermined amount of time is output.

In this case, there are three conventional image synthesizing apparatuses which realize the movement of images by a frame buffer method, for example.
While it requires the memory size for fields,
It suffices to prepare a memory size for a maximum of 2 fields in the memory means. Therefore, it is possible to reduce the mounting amount of the memory as compared with the related art and reduce the cost.

According to a fourth aspect of the present invention, in addition to the configuration according to the third aspect, the memory control means stops writing to the memory means for a blanking interval included in the key source signal. To do.

An image synthesizing method according to claim 12 is
In addition to the structure described in claim 11, in the key source delay step, writing to the memory means is stopped for a blanking interval included in the key source signal.

As a result, the blanking intervals such as the horizontal blanking interval and the vertical blanking interval of the key source signal, which are unnecessary when synthesizing the images, are not written in the memory means, so that only the memory means corresponding to the blanking interval is written. It is possible to reduce the size of the memory prepared for, and further reduce the cost.

According to a fifth aspect of the present invention, in addition to the structure of the first aspect, the key source delay means delays the key source signal in units of horizontal lines of an image. And a second delay unit that delays the key source signal output from the first delay unit in pixel units of an image, and the first delay unit temporarily holds the content of the key source signal. And a first memory control means for controlling writing and reading with respect to the first memory means, wherein the first memory control means is a blanking interval included in the key source signal. With regard to the above, while stopping the writing to the first memory means, the contents written in the first memory means are delayed and read in units of horizontal lines of the image, and the second delay is performed. Includes second memory means for temporarily holding the content of the key source signal output from the first delay section, and second memory control means for controlling writing and reading to and from the second memory means. The second memory control means delays and reads the content written in the second memory means in pixel units of the image.

An image synthesizing method according to claim 13 is
In addition to the configuration according to claim 9, in the key source delay step, the key source signal is written and temporarily held in the first memory means, and the blanking interval included in the key source signal is the first one. A line delay step of delaying and reading the contents written in the first memory means in units of horizontal lines of an image while stopping writing to the memory means, and contents of the key source signal read in the line delay step. The second
And a pixel delay step of reading out the contents written in the second memory means with a delay in pixel units of the image.

With this, it is possible to reduce the memory size of the first memory means without writing the blanking intervals such as the horizontal blanking interval and the vertical blanking interval included in the key source signal in the first memory means. On the other hand, it is possible to eliminate the complication of writing and reading control which is caused by not writing the blanking section in the memory means in this way, and the key source signal can be arbitrarily set over the entire screen by a simple memory control method. It can be delayed by the amount of time.

According to a sixth aspect of the present invention, in addition to the configuration of the first aspect, the image synthesis apparatus performs interpolation processing on an image included in a key source signal input to the signal synthesis means to obtain the key source. It further comprises interpolation filter means for delaying the signal by pixel units or less of the image.

An image synthesizing method according to claim 14 is
In addition to the configuration according to claim 9, an interpolation step of delaying the key source signal by a pixel unit or less of an image by performing an interpolation process on an image included in a key source signal used for the combining process in the signal combining step. Further has.

Thus, the shift between the key source signal and the second video signal can be adjusted with high precision in units of pixels or less, and high quality image synthesis can be realized.

An image synthesizing apparatus according to a seventh aspect of the present invention further comprises, in addition to the configuration according to the first aspect, a matting signal generating means for generating a matting signal having a predetermined luminance component and chromaticity component. The synthesizing means synthesizes the matte signal generated by the matte signal generating means as a second video signal.

An image synthesizing method according to claim 15 is
In addition to the configuration according to claim 9, there is further provided a mat signal generation step of generating a mat signal having a predetermined luminance component and chromaticity component, and in the signal combination step,
The matte signal generated in the matte signal generating step is combined as a second video signal.

With this, it is possible to add a predetermined luminance component and chromaticity component to the key included in the key source signal, and combine this key with the background image included in the first video signal.

According to an eighth aspect of the present invention, in addition to the configuration of the first aspect, the image synthesizing device further comprises a key fill delay means for delaying a key fill signal input from the outside by a predetermined amount of time and outputting the key fill signal. And a key fill control means for controlling a synthesis position of the key fill signal by controlling an amount of time delayed by the delay means, wherein the signal synthesis means outputs the key fill signal output from the key fill delay means to a second image. Combine as a signal.

An image synthesizing method according to claim 16 is
In addition to the configuration according to claim 9, the key fill signal is controlled by controlling a key fill delay step of delaying and outputting a key fill signal input from the outside by a predetermined amount of time and an amount of time delayed in the key fill delay step. Further comprising a key fill control step for controlling the synthesis position of
The key fill signal delayed by the key fill delay step is combined as a second video signal.

As a result, the key fill signal input as the second video signal can be delayed in the same manner as the key source signal, and the composition target image can be displayed at an arbitrary position on the screen by an extremely simple structure and method. It becomes possible to shift to.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention includes a first video signal including a background image and a second video signal including a synthesis target image.
The image synthesizing apparatus and the image synthesizing method for synthesizing the image signal of 1) based on a key source signal including information indicating a synthesizing position. In the present invention, the key source signal is delayed by a predetermined amount of time when the combined position is shifted to an arbitrary position on the screen, which is a so-called delay system. Therefore, in the following, first, an outline of the principle by which the combined position can be shifted by this delay method will be described.

(1) General Principle of Delay Method The key source signal is a signal that constitutes one frame by two fields of an odd field and an even field, like other general video signals. It is a signal that constitutes image information for the screen.

Therefore, as shown in FIG. 1, a memory having a size capable of holding the key source signal for up to 2 fields is prepared, and the inputted key source signal is sequentially stored in this memory. Keep it. Then, the key source signal stored in the memory is read out by delaying by the amount of time corresponding to the desired shift amount,
The image information included in this key source signal can be shifted to an arbitrary position within one screen.

Specifically, for example, in FIG. 1, when the first field, the third field, and the fifth field are odd fields, and the second field and the fourth field are even fields, the first field By delaying the key source signal corresponding to the field within one field, the key information included in this key source signal can be shifted to any position on the screen within the first field (odd field). Also, by delaying the key source signal in the first field in the next one field, the key information included in the key source signal is shifted to an arbitrary position in the screen in the second field (even field). You can Therefore, by delaying the key source signal by a maximum of 2 fields, the key information contained in the key source signal is distributed over the two fields of the odd field and the even field (that is, one frame) and the It can be moved to any position.

On the other hand, for example, a conventional special effect device (DVE)
As shown in FIG. 2, in the frame buffer method adopted for the purpose of manipulating an image in a device or the like, first to third memories each having a memory size sufficient to store a video signal for one field, as shown in FIG. M1, M2 and M3 are prepared. Then, as shown in FIG. 3, the input video signal is sequentially stored in the first to third memories M1, M2, M3 for each one field.

In the frame buffer method, in order to shift the position of the image existing in the first field over one screen, as shown in FIG. 3, the video signals corresponding to the first field and the second field are respectively changed to the first field. 1 Nobi second memory M1, M
After writing to the second field, it is necessary to perform an operation of reading from the first memory M1 while writing the video signal corresponding to the third field to the third memory M3. That is, in the frame buffer method, it is necessary to prepare a memory size for 3 fields.

Therefore, the delay method adopted in the present invention can shift the position of the image information included in the key source signal with a smaller memory size as compared with the conventionally used frame buffer method.

Further, in the conventional frame buffer system,
Even if the image included in the video signal is moved by, for example, a few pixels or a few lines, a memory size of 3 fields is required.
It has an advantage that it is sufficient to prepare a memory size corresponding to the maximum amount of moving an image. That is, in the delay method, for example, when moving an image by a few pixels or a few lines, it is sufficient to prepare a memory size that temporarily holds a key source signal corresponding to the moving amount. is there.

In the delay method, the input key source signal is written in the memory, temporarily held, and then delayed by a predetermined time and read in the written order. Therefore, when realizing this delay operation, a FIFO (First In
First Out) type semiconductor memory can be used. Such a semiconductor memory is extremely low in cost and small in size as compared with a memory required in the frame buffer system, and can be used with a simple circuit configuration.

In the delay method, a series of key source signals are delayed in time when the position of the image information included in the key source signal is moved, so that the blanking interval and the blanking interval included in the key source signal are delayed. It is conceivable that an unnecessary area such as a folded area caused by the delay may appear at an unintended position on the screen. Therefore, it is desirable to prepare a circuit or the like for removing such an unnecessary area. This point will be described in detail later.

(2) Overall Structure of Keyer Device Next, the following will describe a specific embodiment of the present invention.
The keyer device 10 configured as shown in FIG. 4 by adopting the above-mentioned basic principle of the delay system will be described. A background signal is input to the keyer device 10 as a first video signal including a background image, and a key fill signal is input as a second video signal including a compositing target image.
Further, the keyer device 10 is input with a key source signal including information indicating the position where the second video signal is combined, and the first video signal and the second video signal are combined based on this key source signal. Then, the device performs a process of outputting a video signal including an image in which the image to be combined is combined with the background image, that is, a so-called keying process.

Here, the key source signal is a video signal including image information including characters such as a title and a telop, and the key fill signal is a video signal including an image displayed inside these characters. In addition, for example, when another image is inserted in the image serving as the background image as in the case of performing so-called picture-in-picture processing, a video signal including the image to be inserted is input as the key fill signal, and the key source signal is input. As a signal, a video signal indicating a region to be inserted (a video signal which is so-called mask information) is input. In addition, the keyer device 10 has a video signal having a predetermined luminance component and chromaticity component for the purpose of only providing a desired color or the like without placing an image on a character such as a title or telop. A circuit for generating the mat signal is provided, and this mat signal can be selected as the second video signal.

The keyer device 10, which is a device exclusively performing the above-mentioned keying process, will be described below as an example of the configuration of the present invention. However, the functions realized by the keyer device 10 may be other than the switcher device, for example. It may be configured to be installed in the video equipment of.

The keyer device 10, as shown in FIG.
A first A / D converter 20 for performing digital conversion processing on an input key source signal, and a first A / D converter 2
A key source delay circuit 21 that delays the key source signal output from 0 by a predetermined time and outputs the key source signal, and pixel interpolation processing is performed on the key source signal output from the key source delay circuit 21 to generate an image. A first interpolator 22 that imparts a delay equal to or less than a pixel unit, and a first masking that performs a process of removing an unnecessary area on an image included in a key source signal output from the first interpolator 22. And a circuit 23. These first A / D converter 20, key source delay circuit 21, first
Interpolator 22 and first masking circuit 2
3 is provided for the purpose of performing delay processing on the key source signal, and as a whole constitutes a key source signal delay circuit system.

Further, the keyer device 10 performs the second A conversion process for digitally converting the inputted key fill signal.
/ D converter 24, a key fill delay circuit 25 for delaying and outputting the key fill signal output from the second A / D converter 24 by a predetermined amount of time, and a key fill delay circuit 25.
Included in the key fill signal output from the second interpolator 26 and a second interpolator 26 that delays the pixel unit of the image or less by subjecting the key fill signal output from And a second masking circuit 27 that performs processing for removing unnecessary areas on the image to be displayed. The second A / D converter 24, the key fill delay circuit 25, the second interpolator 26, and the second masking circuit 27 are provided for the purpose of performing delay processing on the key fill signal, so to speak, as a whole. It constitutes a key fill signal delay circuit system.

Further, the keyer device 10 includes a third A / D converter 28 for digitally converting the input background signal, a mat signal generation circuit 29 for generating and outputting a mat signal. A selector 30 that selects which of the key fill signal output from the key fill signal delay circuit system and the matte signal output from the matte signal generation circuit 29 is used as the second video signal to be combined, and a background. A mixer circuit 31 for synthesizing the signal and the signal selected by the selector 30 based on the key source signal output from the key source signal delay circuit system, and an analog conversion for the video signal output from the mixer circuit 31. A D / A converter 32 that performs processing, and a control circuit 3 that controls the operation of each unit that constitutes the keyer device 10.
3 and 3.

In this example, it is assumed that the signal input / output to / from the keyer device 10 is an analog signal, and various signal processing inside the keyer device 10 is performed by digital processing. When the type of input / output signals and the type of signal processing in the keyer device 10 match, the first to third A / D converters 2
The 0, 24, 28 and the D / A converter 32 may be appropriately omitted.

Further, the keyer device 10 is provided with a mat signal generation circuit 29, and the mat signal generation circuit 29 is provided.
Which one of the mat signal output from the key fill signal delay circuit system and the key fill signal output from the key fill signal delay circuit system is used as the second video signal to be combined is selected by the selector 3
The selectable configuration is 0.

The keyer device 10 having such a configuration allows a title, a telop or the like input as a key source signal to be superimposed with a single color even if a key fill signal is not input. It is possible to perform a simple combining process such as. However, the mat signal generation circuit 29 and the selector 30 may be omitted, and the mat signal may be externally input as a key fill signal even when the above-described combining process is performed.

The mixer circuit 31 includes a background signal as a first video signal including a background image and a selector 30.
The second video signal (that is, the key fill signal or the matte signal) selected as a synthesis target by is synthesized based on the key source signal output from the key source signal delay circuit system.

The mixer circuit 31 includes, for example, a first adder that inverts the key source signal, a first multiplier that multiplies the second video signal by the key source signal K, and a first addition. A second for multiplying the output from the device by the first video signal
And a second adder that adds the outputs from the first and second multipliers. The key source signal K is normalized to 0 or more and 1 or less. By this normalization, for example, when the key source signal has an 8-bit width, the value 0 becomes “0.0”,
The value 255 becomes “1.0”. Also, the output from the first adder can be represented as [1-K].

The mixer circuit 31 synthesizes the first video signal and the second video signal on the basis of the key source signal by using the adder and the multiplier to obtain a background image included in the first video signal. It is configured to output a video signal including an image obtained by combining the image to be combined included in the second video signal. It should be noted that the mixer circuit 31 is not limited to being configured by the adder or the multiplier as described above as long as the same function can be realized, and the function of performing image synthesizing processing by various digital circuits or analog circuits is possible. It may be realized.

The control circuit 33 has a function of controlling the operation of each part by outputting various control signals to each part constituting the keyer device 10. Control unit 3
3 is configured by a semiconductor chip such as a CPU (Central Processing Unit). In addition, the control circuit 33
Although not shown in the figure, an operation switch or the like for inputting an operation from the user is connected to. Control circuit 3
The control unit 3 controls the delay applied to the key source signal and the key fill signal, controls the mat signal generated by the mat signal generation circuit 29, and controls the synthesizing process in the mixer circuit 31 in response to a request from the user.

By the way, the keyer device 10 has the key source signal delay circuit system and the key fill signal delay circuit system as described above, and the respective delay circuit systems respectively respond to the key source signal and the key fill signal. It is possible to independently delay by a predetermined amount of time. As a result, the keyer device 10 can independently move the information indicating the combination position included in the key source signal and the combination target image included in the key fill signal to an arbitrary position on the screen.

However, the keyer device 10 can dispense with the key fill signal delay circuit system if the image to be combined contained in the key fill signal is not controlled to move within the screen.

In the keyer device 10, the key source signal delay circuit system and the key fill signal delay circuit system are
They have the same configuration and have the same actions and effects.

For the above reason, in the following, of the key source signal delay circuit system and the key fill signal delay circuit system, the key source signal delay circuit system will be particularly noted to explain each part. Will be omitted.

Note that each of the parts constituting the key fill signal delay circuit system, the second A / D converter 24, the key fill delay circuit 25, the second interpolator 26, and the second masking circuit 27 are key sources, respectively. It corresponds to each part constituting the signal delay circuit system, the first A / D converter 20, the key source delay circuit 21, the first interpolator 22, and the first masking circuit 23.

(3-1) First Configuration Example of Key Source Delay Circuit In the following, one specific configuration example of the key source delay circuit 21 among the respective parts constituting the key source signal delay circuit system will be described with reference to FIG. A description will be given with reference to the first configuration example shown in FIG.

The key source delay circuit 21, as shown in FIG. 5, for example, outputs a write address (Write address) and a read address (Read address) to the memory 50 composed of a semiconductor memory device. It can be configured by the counter 51 that operates.

The memory 50 has a memory capacity sufficient to temporarily hold pixel information corresponding to the maximum delay applied to the key source signal. That is, when moving the information about the combination position included in the key source signal in the horizontal direction of the screen by, for example, 10 pixels, the memory 50 needs a sufficient memory capacity to temporarily hold the pixel information of 10 pixels. Therefore, for example, when moving by 5 lines in the vertical direction of the screen, the memory 50 requires a sufficient memory capacity for temporarily holding pixel information for 5 lines.

Further, the counter 51 sequentially counts up the write address and the read address in a predetermined cycle, and outputs the write address and the read address to the memory 50. The memory 50 writes the input key source signal to the write address designated by the counter 51, and sequentially outputs the content stored at the read address designated by the counter 51. At this time, access to the same address of the memory 50 is performed in the order in which the writing process is performed after the data reading process is performed.

Here, for example, the case of delaying the key source signal (output signal) to be output with respect to the input key source signal (input signal) by n pixels will be described more specifically. In this case, as shown in FIG.
The write address and the read address output by the counter 51 are each incremented from "1" to "n". Then, in the memory 50, the area shown by the shaded area in the drawing is temporarily held in the memory 50, and as shown in FIG. 6, the held content is read out with a delay of n pixels. Become. That is, the output signal is output with a delay of n pixels from the input signal.

For the reason described above, in order to move the key information included in the key source signal to an arbitrary position on the screen, the key source delay circuit 21 sends the key source signal for one frame at the maximum ( That is, it is only necessary to delay by 2 fields). Therefore, the memory size of the memory 50 included in the key source delay circuit 21 is
It suffices to prepare only a sufficient amount of key source signals for two fields to be temporarily held.

(3-2) Second Configuration Example of Key Source Delay Circuit

By the way, the above-mentioned key source delay circuit 2
In the first configuration example of No. 1, all input key source signals are sequentially stored in the memory 50 temporarily.
However, the actual key source signal includes, for example, a blanking section such as a horizontal blanking section or a vertical blanking section, and this blanking section becomes unnecessary in the image combining processing. Therefore, in the first configuration example, an unnecessary blanking section included in the key source signal is also written in the memory 50, which causes a slight waste from the viewpoint of utilization efficiency of the memory area.

Therefore, a second configuration example of the key source delay circuit 21 in which this point is improved will be described below with reference to FIG.

Key source delay circuit 2 according to the second configuration example
1 has a basic configuration equivalent to that of the first configuration example shown in FIG. 5, but as shown in FIG. 7, the blanking interval included in the input signal is addressed so as not to be written in the memory 50. Controlled. In addition, in FIG.
The horizontal blanking interval that appears in the input signal for each line of the screen is shown by a thick line. Then, the counter 51 receives a write inhibit signal whose signal level becomes high in a cycle corresponding to the horizontal blanking interval, and outputs a write address while the signal level of the write inhibit signal is high. It is configured not to count up.

In the example shown in FIG. 7, it is assumed that the input signal is delayed by n pixels before being output, as in the case shown in FIG. 6, and the counter 51 outputs the write address between 1 and n. Shall be counted up.
If the value of the write address is "a" at the time when the write inhibit signal becomes high during the count up of this address, the value of the write address is not increased while the write inhibit signal is high. That is, during this period, writing to the memory 50 is not performed. The signal level of the write inhibit signal is low (Lo
When returning to w), it is considered that the unnecessary blanking interval has ended, and the counter 51 restarts counting up the write address from the value “a + 1”.

Since the key source delay circuit 21 in the present example configured as described above is configured to stop writing to the memory 50 for the blanking interval included in the key source signal, this blanking interval The memory size prepared in the memory 50 can be reduced by that amount.

(3-3) Third Configuration Example of Key Source Delay Circuit

By the way, the key source delay circuit 2 described above is used.
In the second configuration example of No. 1, since the write operation to the memory 50 is stopped during the period corresponding to the blanking interval, the read operation from the memory 50 is appropriately controlled and the write operation is still performed. It is necessary to prevent problems such as reading from an address that is not stored. In order to realize such address control, complicated logic circuits and address processing are required.

Therefore, in the following, with reference to FIG. 8, a third configuration example of the key source delay circuit 21 that can realize the delay of the key source signal with a simple configuration without requiring a complicated logic circuit and address processing will be described. While explaining.

Key source delay circuit 2 according to the third configuration example
As shown in FIG. 8, 1 outputs a first memory 60 that delays the input key source signal in image line units, and a write address and a read address for the first memory 60. First counter 61
A second memory 62 that delays the key source signal read from the first memory 60 in pixel units of an image; and a second memory that outputs a write address and a read address for the second memory. Counter 63
With. That is, in the key source delay circuit 21 according to the present example, the first memory 60 and the first counter 61 configure a line delay unit that delays the key source signal on a line-by-line basis of an image. The memory 62 and the second counter 63 form a pixel delay unit that delays the key source signal pixel by pixel within one line of the image.

In the line delay section, the write inhibit signal whose signal level becomes high corresponding to the blanking interval included in the key source signal is applied to the first memory 60 and the first memory 60, as in the case of the second configuration example. Input to the first counter 61, and as shown in FIG. 9, writing to the first memory 60 is stopped while the signal level of this write signal is high. As a result, the first memory 6
For 0, the writing process is performed only in the period shown by the shaded portion in FIG. 9, that is, in the period in which the input signal includes a valid signal, not in the blanking interval. In FIG. 9, horizontal blanking intervals appearing in the input signal for each line of the screen are indicated by thick lines.

In this line delay section, the write inhibit signal also functions as a read inhibit signal that inhibits reading from the first memory 60, and the read inhibit signal (ie, write inhibit signal) signal. During the period when the level is high, the reading process from the first memory 60 is stopped. As a result, the first memory 60
From this point, the read processing is performed only for the period shown by the shaded area in FIG.

Then, the read processing from the first memory 60 is configured so that the address is controlled by the first counter 61 so that the reading is delayed by one line unit of the screen. More specifically, for example,
The signal written in the first memory 60 at time A shown in FIG. 9 is delayed by one line, two lines, or three lines from this time.
Alternatively, the data is read at the time D, and the reading at the midway time is not performed.

As described above, since the line delay unit is limited to the process of delaying the key source signal in units of lines, the write process and the read process for the first memory 60 are controlled at the same timing. A write inhibit signal and a read inhibit signal whose signal level becomes high can be used, and these inhibit signals can be shared. Since the writing process and the reading process with respect to the first memory 60 are performed based on this prohibition signal, it is not necessary to provide a complicated logic circuit or address control, and the key source signal is line-by-line based on an extremely simple configuration. It is possible to delay processing with.

Further, in the line delay unit, since the unnecessary blanking section included in the key source signal is not written in the first memory 60,
The memory size required for the first memory 60 can be reduced.

On the other hand, in the pixel delay unit provided after the line delay unit, the key source signal is subjected to delay processing in pixel units within one line of the image. That is, in the key source delay circuit 21 according to the third configuration example, the key information included in the key source signal is moved in the vertical direction in the screen by the line unit by the delay process in the line delay unit, and then the pixel delay is performed. The key information is moved in the horizontal direction on a pixel-by-pixel basis in the screen by the processing in the section.

When the key source delay circuit 21 is configured as described above, the maximum shift amount of the key information in the line delay part is (2 fields-1 line), and the maximum shift amount of the key information in the pixel delay part is. It is for one line. Here, since the ratio of the horizontal blanking interval in the key source signal is about 15% in most signal formats, the line delay unit should reduce the memory size by at least the horizontal blanking interval. Is possible. Therefore, the third
In the key source delay circuit 21 according to the configuration example, the total memory size M required for the first memory 60 and the second memory 62 can be expressed as shown in the following Expression 1 for convenience. M = (2 fields-1 line) x (1-0.15) + (1 line) (Equation 1)

That is, as in this example, the key source delay circuit 21 has a two-stage structure including a line delay section and a pixel delay section, and delay processing is performed in line units and pixel units, respectively, and writing processing in the blanking interval is stopped. By adopting the configuration (2 fields-
About 15% of the memory size required to hold the key source signal for one line) can be reduced. Although this memory size reduction effect is not so large as a reduction amount, one semiconductor memory is sufficient, for example, when the first memory 60 is configured by using a standard FIFO type semiconductor memory. There may be a great advantage from the viewpoint of implementation such as whether there is or a memory size corresponding to two.

In the pixel delay unit, the maximum is 1
It suffices if delay processing is performed within the line, and the second memory 62
The memory size required for the above is sufficient if it has a memory size capable of temporarily holding the key source signal for one line at the maximum. However, the pixel delay unit may be capable of performing delay processing with one or more n lines.

(4) Interpolation Processing in Interpolator Next, the pixel interpolation processing in the first interpolator 22 of the respective parts constituting the key source signal delay circuit system in the keyer device 10 will be described below.

In the keyer device 10, the key source delay circuit 21 allows the key information to be freely moved to any position on the screen in pixel units of the image. The first interpolator 22 uses the key source delay circuit. It is provided for the purpose of moving the key information included in the key source signal in pixel units or less by further applying delay processing in pixel units or less to the key source signal delayed in the circuit 21.

The keyer device 10 may be configured without the first interpolator 22, but by including the first interpolator 22,
It is possible to move the key information included in the key source signal with higher accuracy. This aligns the key source signal and the key fill signal with higher accuracy,
Image composition processing can be performed. In particular, when the key source signal and the key fill signal are input as analog signals, there is almost always a slight deviation between the signals, so the first interpolator 22 reduces the signal difference. It is extremely effective to adjust and align. Further, the highly accurate positioning operation realized by the first interpolator 22 is also effective in highly accurately positioning the key position with respect to the background image included in the background signal.

As the pixel interpolation processing performed by the first interpolator 22, various conventionally known interpolation processing can be adopted. Below, an example of this pixel interpolation processing will be described with reference to FIG. A specific description will be given with reference to FIG.

Here, each pixel (pixel) included in the key source signal input to the first interpolator 22.
Will be schematically shown in FIG. Below,
Regarding the processing of moving the pixel located at the point A to the position of the point A ′ in FIG. 10, based on the information about the four points (points A, B, C, D) located near the pixel of the point A, Consider a case where so-called 2 × 2 linear interpolation processing is performed.

At this time, it is assumed that the point A ″, which is point-symmetric with the point A ′ about the point A, has the positional relationship as shown in FIG. 11 with respect to the other points A, B, C, and D. In this case, the information regarding the pixel of this point A ″ is obtained by the following Expression 2. A '' = ((6 x A + 2 x B) x 3 + (6 x D + 2 x C) x 5) / 64 (Formula 2)

Next, the operation for replacing the information on the pixel at the point A with the information on the virtual pixel at the point A ″, that is, the operation shown in the following expression 3 is performed.

A = A '' (Formula 3)

As a result, the pixel at the point A has been moved to the position of the point A '. Then, by performing this series of processing for all the pixels included in the key source signal, the image represented by the rectangle shown by the solid line in FIG. 10 is changed to the position represented by the rectangle shown by the dotted line in FIG. The amount of movement is less than the pixel unit.

In the above description, as the pixel interpolation processing in the first interpolator 22, an example of interpolation processing using four points has been described, but in addition to this, interpolation is performed using, for example, 16 points. Various conventionally known interpolation processes such as a method may be adopted. In addition,
The first interpolator 22 may adopt a method of interpolating each pixel without referring to information of other pixels, but by performing interpolation by referring to information of other pixels, The characteristics can be improved. Further, the first interpolator 22 can be configured by various interpolation filter circuits that have been widely used conventionally.

(5) Masking Process in Masking Circuit Next, the masking process in the first masking circuit 23 of the respective parts constituting the key source signal delay circuit system in the keyer device 10 will be described below.

In the keyer device 10, the key source delay circuit 21 delays the key source signal to move the position of the key information included in the key source signal. Therefore, in the key source signal after the delay processing, as shown in FIG. 12, a horizontal blanking interval or a vertical blanking interval included in the key source signal, or a folding region due to the delay of the key source signal occurs. Becomes Note that in FIG. 12, the effective screen area of the image included in the key source signal is shown by a rectangle surrounded by a dotted line in the figure, and the folded area caused by the delay is shown by a hatched portion.

These blanking intervals and folding regions appearing on the screen after the delay processing are not only unnecessary in the image synthesizing process, but also parts other than the key information used in the image synthesizing process appear in the effective screen region. As a result, it may be difficult to correctly perform image synthesis.

Therefore, in the keyer device 10,
A first masking circuit 23 is provided for the purpose of masking and removing these unnecessary regions. In the first masking circuit 23, the folding portion in which an unnecessary portion appears is calculated based on the movement amount applied to the key source signal by the delay processing, and the key source signal is calculated for the calculated folding portion. The process of setting the value to “0” (that is, the process of setting no key) may be performed.

The second masking circuit 23 having the same function as that of the first masking circuit 23 may be processed in the same manner as described above, but the second masking circuit 23 calculates it. A process for making the key fill signal black (that is, a process for making a state where there is no image to be combined) is performed on the folded portion. However, the second masking circuit 23 does not necessarily have to be provided.

Here, the actual masking process in the first masking circuit 23 will be described with reference to FIG. Note that FIG. 13 is a schematic diagram showing the processing performed for each line of the image and focusing on the time axis.
As shown in FIG. 13, the first masking circuit 23 compares the key source signal before the delay processing and the key source signal after the delay processing, and considers the delay amount and an unnecessary section such as a blanking section. Then, a masking signal indicating the area to be masked is generated. Note that, in FIG. 13, a portion of the key source signal excluding the blanking interval is illustrated by a white rectangular portion, and a region to be masked indicated by the masking signal is illustrated by a thick line. Then, by setting the value of the portion indicated by the masking signal in the delayed key source signal to “0”, the key source signal in which this portion is masked is output.

Since the keyer device 10 is provided with the first masking circuit 23 for performing the masking process as described above, unnecessary parts such as a blanking section and a folding region included in the key source signal after the delay process are provided. Can be effectively removed, and it is possible to prevent unintended composition during the image composition processing.
Normal composition processing can be realized across all screens.

Note that the masking process adopted in the first masking circuit 23 is not limited to the above-mentioned method, and various other methods can be adopted.
Further, the first masking circuit 23 can be easily realized by combining various circuits widely known in the related art.

(6) Supplement In the above description, focusing on the key source signal delay circuit system in the keyer device 10, the key source delay circuit 21,
Although the details of the first interpolator 22 and the first masking circuit 23 have been described, the key fill delay circuit 25 and the second interpolator 26 provided in the key fill signal delay circuit system corresponding to these respective parts. , And the second masking circuit 27 can have the same configuration, and by including these, the same action and effect can be expected for the key fill signal.

However, the keyer device 10 does not necessarily have to include the key fill signal delay circuit system.
For example, when the composition target image included in the key fill signal is not controlled to be moved within the screen, or a key source signal including characters such as a telop and a title as key information is input, and the mat signal generation circuit is based on this key information. The key fill signal delay circuit system may be omitted when the mat signal generated by 29 is combined with the background signal for exclusive use.

[0110]

According to the present invention, the composite position of the second video signal can be controlled by a very simple operation of delaying the key source signal by a predetermined amount of time. Such a delay operation can be realized by temporarily holding the key source signal and taking out the key source signal after a predetermined time, for example, a delay circuit using a general-purpose FIFO (First In First Out) type semiconductor memory. be able to. Therefore, for example, a dedicated ASIC (Applicat
It is not necessary to use an ion specific integrated circuit), and a relatively small semiconductor memory can be used at low cost. Further, according to the present invention, since the position of the key included in the key source signal is shifted on the screen by the so-called delay method, only the memory size for 2 fields is required at the maximum and the memory size for 3 fields is required. Compared with the frame buffer method, cost reduction can be achieved from the viewpoint of memory size.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining a basic principle of a delay system adopted in the present invention.

FIG. 2 is a schematic diagram for explaining a configuration of a memory required in a frame buffer method compared with a delay method adopted in the present invention.

FIG. 3 is a schematic diagram for explaining a method of using a memory in a frame buffer method compared with a delay method adopted in the present invention.

FIG. 4 is a schematic functional block diagram showing a configuration example of a keyer device shown as an embodiment of the present invention.

FIG. 5 is a schematic view showing a first configuration example of a key source delay circuit included in the keyer device.

FIG. 6 is a schematic diagram for explaining a delay process performed on a key source signal by the first configuration example of the key source delay circuit included in the keyer device.

FIG. 7 is a schematic diagram for explaining a delay process performed on a key source signal by a second configuration example of the key source delay circuit included in the keyer device.

FIG. 8 is a schematic diagram showing a third configuration example of a key source delay circuit provided in the same keyer device.

FIG. 9 is a schematic diagram for explaining a line delay process performed on a key source signal by a third configuration example of the key source delay circuit included in the keyer device.

FIG. 10 is a schematic diagram for explaining pixel interpolation processing in an interpolator included in the keyer device.

FIG. 11 is a schematic diagram for explaining pixel interpolation processing in an interpolator included in the keyer device.

FIG. 12 is a schematic diagram for explaining that a masking process is required in a masking circuit provided in the keyer device.

FIG. 13 is a schematic diagram for explaining an example of a masking process in a masking circuit provided in the keyer device.

FIG. 14 is a schematic diagram for explaining a device configuration that has been conventionally used when performing image combining processing.

[Explanation of symbols]

10 keyer device, 21 key source delay circuit, 22
1st interpolator, 23 1st masking circuit, 25 key fill delay circuit, 26 2nd interpolator, 27 2nd masking circuit, 29 mat signal generation circuit, 30 selector, 31 mixer circuit, 33
Control unit, 50 memory, 51 counter, 60 1st
Memory, 61 first counter, 62 second memory, 63 second counter

Claims (16)

[Claims] 1. An image synthesizing device for synthesizing a first video signal including a background image and a second video signal including a synthesizing target image based on a key source signal indicating a synthesizing position. A key source delay means for delaying and outputting by a predetermined amount of time, and combining the first video signal and the second video signal based on the key source signal delayed by the key source delay means. , A signal synthesizing means for outputting a video signal including an image obtained by synthesizing the synthesizing target image on the background image, and synthesizing the second video signal by controlling the amount of time delayed by the key source delay means. An image synthesizing apparatus comprising: a control unit that controls a position. 2. A masking means for masking a folding area included in a blanking interval and / or a delay included in a key source signal output from the key source delay means, the signal synthesizing means including the masking means. 2. The image synthesizing device according to claim 1, wherein the first video signal and the second video signal are synthesized based on the key source signal masked by the means. 3. The key source delay means comprises memory means for temporarily holding the contents of the key source signal and memory control means for controlling writing and reading with respect to the memory means, and the memory means is written in the memory means. 2. The image synthesizing apparatus according to claim 1, wherein the key source signal delayed by a predetermined amount of time is output by delaying and reading the contents by the memory control means. 4. The image synthesizing apparatus according to claim 3, wherein the memory control means stops writing to the memory means in a blanking interval included in the key source signal. 5. The key source delay means delays the key source signal in horizontal line units of an image, and a key source signal output from the first delay unit in pixel units of an image. And a second delay unit for delaying at, the first delay unit controlling first memory means for temporarily holding the content of the key source signal, and writing and reading to and from the first memory means. The first memory control means stops writing to the first memory means in the blanking interval included in the key source signal, and the first memory control means The contents written in the means are delayed and read in units of horizontal lines of the image, and the second delay unit temporarily stores the contents of the key source signal output from the first delay unit. A second memory means for holding and a second memory control means for controlling writing and reading to and from the second memory means, wherein the second memory control means is written in the second memory means. The image synthesizing apparatus according to claim 1, wherein the contents are read out with a delay in pixel units of the image. 6. An interpolation filter means for delaying the key source signal by a pixel unit or less of the image by performing interpolation processing on the image included in the key source signal input to the signal synthesizing means. The image synthesizing apparatus according to claim 1, characterized in that 7. A matting signal generating means for generating a matting signal having a predetermined luminance component and chromaticity component is further provided, and the signal synthesizing means produces the matting signal generated by the matting signal generating means into a second image. The image synthesizing apparatus according to claim 1, wherein the image synthesizing is performed as a signal. 8. A key fill delay means for delaying and outputting a key fill signal input from the outside by a predetermined amount of time, and a synthetic amount of the key fill signal is controlled by controlling the amount of time delayed by the key fill delay means. 2. The image synthesizing apparatus according to claim 1, further comprising: a key fill control unit, wherein the signal synthesizing unit synthesizes the key fill signal output from the key fill delaying unit as a second video signal. 9. An image synthesizing method for synthesizing a first video signal including a background image and a second video signal including a synthesizing target image based on a key source signal indicating a synthesizing position. By synthesizing the first video signal and the second video signal on the basis of a key source delay step of delaying and outputting a predetermined amount of time, and a key source signal delayed by the key source delay step. , A signal synthesizing step of outputting a video signal including an image obtained by synthesizing the synthesizing target image with the background image, and synthesizing the second video signal by controlling the amount of time delayed in the key source delay step. And a control step for controlling the position. 10. A masking step for masking a blanking interval included in a key source signal output by the key source delaying step and / or a folding area generated by a delay, and the signal synthesizing step, 10. The image synthesizing method according to claim 9, wherein the first video signal and the second video signal are synthesized based on a key source signal masked by the masking step. 11. In the key source delaying step, the contents of the key source signal are written into a memory means and temporarily held, and the contents written into the memory means are delayed and read out for a predetermined amount of time. 10. The image synthesizing method according to claim 9, wherein the delayed key source signal is output. 12. The image synthesizing method according to claim 11, wherein, in the key source delay step, writing to the memory means is stopped for a blanking interval included in the key source signal. 13. The key source delaying step writes the key source signal in the first memory means and temporarily holds it, and writes the blanking interval included in the key source signal into the first memory means. While stopping, a line delay step of delaying and reading the contents written in the first memory means in units of horizontal lines of an image, and a content of the key source signal read in the line delay step in the second memory 10. The image delaying step according to claim 9, further comprising: a pixel delay step of writing the data into the means and temporarily holding the content, and delaying and reading the content written in the second memory means in pixel units of the image. Synthesis method. 14. The method further comprises an interpolation step of delaying the key source signal by a pixel unit or less of an image by performing an interpolation process on an image included in a key source signal used in the synthesizing process in the signal synthesizing step. 10. The image synthesizing method according to claim 9, wherein: 15. A mat signal generating step for generating a mat signal having a predetermined luminance component and chromaticity component is further included, wherein in the signal combining step, the mat signal generated by the mat signal generating step is a second signal. 10. The image synthesizing method according to claim 9, wherein the image synthesizing is performed as a video signal. 16. A key fill delay step of delaying and outputting a key fill signal input from the outside by a predetermined amount of time, and controlling a synthesized position of the key fill signal by controlling the amount of time delayed in the key fill delay step. 10. The image synthesizing method according to claim 9, further comprising: a key fill control step for performing a key fill signal delayed by the key fill delay step as a second video signal in the signal synthesizing step.