JP4000791B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4000791B2
JP4000791B2 JP2001181033A JP2001181033A JP4000791B2 JP 4000791 B2 JP4000791 B2 JP 4000791B2 JP 2001181033 A JP2001181033 A JP 2001181033A JP 2001181033 A JP2001181033 A JP 2001181033A JP 4000791 B2 JP4000791 B2 JP 4000791B2
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Japan
Prior art keywords
chip
semiconductor
semiconductor chip
dicing film
substrate
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JP2002373917A (en
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範行 大録
康介 井上
博 本間
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Supply And Installment Of Electrical Components (AREA)
  • Wire Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、無線通信を行う半導体チップを有しこれに付随する外部アンテナ回路を有する小形無線通信装置の製造方法に関し、装置の電気的、機械的、化学的保護となるパッケージの構造及びその製造方法に関する。
【０００２】
【従来の技術】
従来フリップチップ接続技術を用いてリードフレームやインターポーザ基板にICチップなどの半導体チップを搭載接続する場合は、例えば特開2001−015533号公報記載のようにダイシングされた半導体チップを一度真空チャックなどで粘着テープから引き剥がし、その後、反転してコレットに持ち替え、しかる後、搭載するリードフレームやインターポーザ基板に位置決めし接続する方法が一般的であった。
【０００３】
【発明が解決しようとする課題】
しかしながら、上記従来技術は、特に半導体チップが０．３ｍｍ四方程度と小さい場合に、以下のような問題を有している。
【０００４】
従来方式では、ダイシングテープの粘着力で半導体チップが張り付いているので真空チャックなどでチャックしはがすときに、チップが小さい場合は周辺からの漏れが生じやすく、真空吸着力が不足しがちであり、安定した剥離が実現しがたい。
【０００５】
さらに、半導体チップが小さい場合は真空チャックの吸着面寸法をチップサイズとより小さく設計すると吸着力が不足するため、チップサイズぎりぎりの吸着面を必要とする。このためチャック周辺がダイシングテープ上で隣接しているチップに接触しやすく、別なチップの配置を乱してしまうおそれがあった。
【０００６】
また、従来方式ではチップの接続パッドを下向きに回転させてから接続を行うため、チップの持ち替えを生じ、特に微細なチップではチップ把持位置がずれやすく、正確な搭載が困難であった。
【０００７】
【課題を解決するための手段】
上記目的を達成するために本発明においては以下の手段を実施した。ダイシングフィルムに熱処理または紫外線照射により粘着力が低下する拡張可能なフィルムを用い、リードフレーム若しくは基板のチップ搭載位置を周辺より突出させ、また熱処理により接着する樹脂を予め塗布した。これによりにより、ダイシングテープに貼り付けられたウェハをダイシング後、テープ拡張によりチップ周辺のギャップを拡大して、周辺チップの干渉を低減し、またリードフレームましくは基板のチップ搭載位置を周辺より突出させたことでリードフレーム若しくは基板の周辺が接触することを回避した。その上で、搭載しようとする半導体チップをダイシングテープに貼り付けた状態のままで、リードフレーム若しくは基板に近接させ、ダイシングフィルム越しに裏面からコレットで押し上げて、チップとフレーム若しくは基板を接触させる。ここで紫外線照射または熱処理を実施し、半導体チップの固着力がダイシングテープ側よりリードフレーム若しくは基板側の方が強くなるようにする。しかる後にリードフレーム若しくは基板とダイシングテープを引き離し、半導体チップをリードフレーム若しくは基板に移し替える。この方法により、チップの持ち替えを無くし、チップ搭載精度を高めた。
【０００８】
【発明の実施の形態】
本発明の第１の実施の形態について図１乃至図８を用い以下に説明する。
【０００９】
図１は本発明の半導体装置の概略構造を示す斜視図である。ポッティングレジン１０５は簡便のため透明に書いてある。中間基板１０４の基材１０４ａ上に設けられた配線１０４ｂに、半導体チップ１０１は搭載されており、周囲をポッティングレジン１０５で保護されている。
【００１０】
図２に本発明の無線装置の細部詳細を説明する縦断面図を示す。なお、薄膜状の構成を明示するため、膜厚等は実際の構造より厚く強調して作図してある。半導体チップ１０１は、配線１０４ｂの一部に設けられたチップ搭載位置１０４ｃに搭載されている。チップ搭載位置１０４ｃは周囲の中間基板１０４に比べ突出した形態を有している。また、半導体チップ１０１は配線との接続部分であるチップ搭載位置１０４ｃとの接合によってのみ固定されているわけではなく、チップ搭載位置１０４ｃ付近に設けられた接着剤１０４ｅに依っても固定されている。
【００１１】
図３に本発明の半導体装置の製造に用いる中間基板１０４の構造を示す。中間基板１０４は全体として帯状の形態の薄形プリント基板であり、ポリイミドテープである基材１０４ａの上に銅メッキによる配線１０４ｂを施してある。中間基板１０４の両側には送り穴１０４ｂが設けられており、製造工程で高速に安定な送りができる。中間基板１０４には後にチップ搭載位置１０４ｃとなる突起が設けられている。
【００１２】
図４から図８に本実施例の半導体装置の製造工程を順次示す。
【００１３】
図４に搭載開始直前の状態を示す。ダイシングフィルム５０１に貼り付けられたウェハがダイシングされて個々の半導体チップ１０１となる。このままでは半導体チップ１０１の間隔が狭すぎるため、搭載開始前に予めダイシングフィルム５０１を引き延ばして、チップ間隔を拡げておく。この状態でダイシングフィルム５０１を下吸着ステージ７０２に吸着し平坦に固定しておく。一方半導体チップ１０１を搭載する中間基板１０４は上吸着ステージ７０１に平坦に吸着され、チップ搭載位置１０４ｃを下向きになるように下向きに保持される。ここで、下吸着ステージ７０２と上吸着ステージ７０１の相対位置を合わせることで、正に搭載しようとしている半導体チップ１０１ａと中間基板上のチップ搭載位置１０４ｃが対向する位置に、わずかの隙間を有して配置される。
【００１４】
次に図５に示すように、上コレット６０１、及び下コレット６０２が移動し、半導体チップ１０１と中間基板１０４を押しつける。実際にはダイシングテープ５０１の方が中間基板１０４の基材１０４ａに比べ柔軟性に富み、かつ最終廃棄される部材であり永久変形しても問題とならないため、上コレット６０１は殆ど動く必要がなく、下コレット６０２が大部分の移動を行う。中間基板１０４のチップ搭載位置１０４ｃの突起量が少ない場合は、上コレット６０１の移動量をやや大きくした方が好ましい。
【００１５】
また、このときダイシングフィルム５０１が変形させられるため、正に搭載しようとする半導体チップ１０１ａ以外に、これに隣接する半導体チップ１０４ｂなども持ち上げられるが、下吸着ステージ７０２の吸着力で下方向に吸着しており、近接した半導体チップ１０１ｂなどのずれは小さい。
【００１６】
この状態で、両コレット６０１・６０２はヒーターにより加熱されており、半導体チップ１０１、中間基板１０４も接触部付近が加熱される。このとき接着剤１０４ｅも加熱され半溶融し、半導体チップ１０１を粘着する。同時に、ダイシングフィルム５０１の粘着力は加熱処理および、下コレット６０２による変形により低下する。
【００１７】
次に図６に示すように、下コレット６０２が降下する。同時に上コレット６０１もわずかに上昇する。このため、チップ付近の加熱は中断する。このときより大きく変形させられているダイシングフィルム５０１は弾性で元の平面に戻ろうとするが、中間基板１０４の接着剤１０４ｅがチップ１０１を粘着しており、両者は殆ど動く事はない。この状態で半導体チップ１０１、中間基板１０４、接着剤１０４ｅの温度が低下し、接着剤１０４ｅの接着力が強くなる。このときダイシングフィルム５０１の粘着力は温度低下で殆ど復旧せず、弱いままである。
【００１８】
しかる後に、図７に示すように上吸着ステージ７０１と上コレット６０１を大きく上昇させると、加熱処理を経過して既に粘着力を低下させたダイシングテープ５０１の固着力より、冷却により接着力が高まった接着剤１０４ｅの接着力が強いため、半導体チップ１０１ａはダイシングテープ５０１から引き剥がされ、中間基板１０４に移動する。同時にダイシングフィルム５０１は下吸着ステージ７０２の真空吸引によって徐々に引き戻され、概ね元の形状に復帰する。
【００１９】
これらの工程を順次繰り返し、中間基板１０４に順次半導体チップ１０１が搭載された後、中間基板１０４は次のステージであるポッティングステージ８０２に移動して図８に示すように吸着固定される。そしてポッティングノズル８０１からポッティングレジン１１０の滴下を受け、半導体チップ１０１が保護されると同時に、半導体チップ１０１と中間基板１０４の固定が強化される。その後、中間基板１０４から回路部分が個別に切り出され、図１に示した製品形状となる。
【００２０】
この実施例では、チップ搭載位置１０４ａの突起量が十分にあったため、隣接するチップ搭載位置１０４ｃが無関係な半導体チップ１０１に接触することが十分防止でき、上コレット６０１の移動量は最小限で済み、中間基板１０４に与えるダメージは最小限で済む。
【００２１】
以下に、本発明のその他の実施例を示す。
【００２２】
図９は、チップ搭載位置１０４ｃの突出量が設計上の制限で十分に得られなかった場合の実施例を、第１の実施例の図５の工程と対比して示した図である。このとき上コレット６０１は第１の実施例での移動量より大きく設定されており、代わりに下コレット６０２の移動量が少なくなっている。このため、搭載しようとする半導体チップ１０１以外の半導体チップ１０１ｂ等の移動量も少なくなっており、また、搭載すべきチップ搭載位置１０４ｃは中間基板１０４全体から比べて十分な突出量を得ており、無関係な半導体チップ１０１ｂ等が中間基板１０４に不用意に接触することがない。この実施例では搭載時に上コレット６０１を移動させることでチップ搭載位置１０４ｃを突出させるため、中間基板１０４の製造工程で大きな突出を設ける必要が無く、中間基板１０４の製造工程が簡略化できるメリットがある。
【００２３】
また第１の実施例では接着剤１０４ｅに高温で溶融し中温で粘着性を示し、低温で接着剤として働く熱可塑性樹脂から成る接着剤を用いたが、初期には粘着剤としての流動性を示し、加熱処理により硬化して十分な接着強度を発揮する熱硬化性樹脂による接着剤を使用することもできる。この場合はコレット６０１及び６０２の加熱温度を熱硬化性樹脂の反応に足るだけの高温に、十分な時間保つことは困難であり、一般に熱可塑性樹脂であるダイシングフィルム５０１の耐熱温度を超えてしまう。そこで、チップ搭載時の熱処理はダイシングフィルム５０１から半導体チップ１０１を引き剥がすに足るだけの熱処理に留め、ポッティングレジン１１０の滴下工程の前に十分な熱処理をバッチで実施することで、接着剤１０４ｅの硬化時間を十分に得つつ、ダイシングフィルム５０１に不要な熱疲労を与えなくて澄む。この実施例では接着剤１０４ｅに低温で熱可塑性を示す樹脂を使用しなくても済むため、ポッティングレジン１１０との接合強度を高くすることができ、半導体装置のリフロー耐性を高くすることができるメリットがある。
【００２４】
【発明の効果】
本発明によれば、従来のフリップチップ接続による手法と比較してチップを上下反転する必要がないため、搭載精度を高めやすく、例えば０．５ｍｍ以下の微細なチップをダイシングフィルムから直接基板に搭載できるメリットがあり、より微細な半導体チップを用いた半導体装置を安価に提供することができる。
【図面の簡単な説明】
【図１】本発明の半導体装置の概略構造を示す斜視図。
【図２】本発明の半導体装置の細部詳細を説明する縦断面図。
【図３】本発明に用いる中間基板１０４の構造を示す斜視図。
【図４】製造工程の途中に本発明の半導体装置の状態を示す立面図。
【図５】製造工程の途中に本発明の半導体装置の状態を示す立面図。
【図６】製造工程の途中に本発明の半導体装置の状態を示す立面図。
【図７】製造工程の途中に本発明の半導体装置の状態を示す立面図。
【図８】製造工程の途中に本発明の半導体装置の状態を示す立面図。
【図９】その他の実施例を示す図。
【符号の説明】
１００…パッケージ（全体）、１０１…ＩＣチップ、１０４…中間基板、１０４ａ…基材、１０４ｂ…配線、１０４ｃ…チップ搭載位置、１０４ｄ…送り穴、１０４ｅ…接着剤、１１０…保護レジン、５０１…ダイシングテープ、６０１…上コレット、６０２…下コレット、７０１…上吸着ステージ、７０２…下吸着ステージ、８０１…ポッティングノズル、８０２…ポッティングステージ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a small wireless communication device having a semiconductor chip for performing wireless communication and an external antenna circuit associated therewith, and a package structure for electrical, mechanical, and chemical protection of the device and its manufacture. Regarding the method.
[0002]
[Prior art]
When a semiconductor chip such as an IC chip is mounted and connected to a lead frame or an interposer substrate using a conventional flip chip connection technique, for example, a diced semiconductor chip as described in JP-A-2001-015533 is once used with a vacuum chuck or the like. A method of peeling off from the adhesive tape, then inverting and holding it to the collet, and then positioning and connecting to the lead frame or interposer substrate to be mounted has been common.
[0003]
[Problems to be solved by the invention]
However, the above prior art has the following problems especially when the semiconductor chip is as small as about 0.3 mm square.
[0004]
In the conventional method, the semiconductor chip is stuck with the adhesive force of the dicing tape, so when peeling off with a vacuum chuck, etc., if the chip is small, leakage from the surroundings tends to occur and the vacuum adsorption force tends to be insufficient. Stable peeling is difficult to achieve.
[0005]
Furthermore, when the semiconductor chip is small, the suction force is insufficient when the suction surface size of the vacuum chuck is designed to be smaller than the chip size. For this reason, the periphery of the chuck tends to come into contact with adjacent chips on the dicing tape, and there is a possibility that the arrangement of another chip may be disturbed.
[0006]
Further, in the conventional method, since the connection is performed after the connection pad of the chip is rotated downward, the chip is changed. In particular, in a fine chip, the chip gripping position is liable to shift, and accurate mounting is difficult.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, the following means are implemented in the present invention. An expandable film whose adhesive strength is reduced by heat treatment or ultraviolet irradiation is used for the dicing film, the chip mounting position of the lead frame or substrate is protruded from the periphery, and a resin to be bonded by heat treatment is applied in advance. As a result, after dicing the wafer affixed to the dicing tape, the gap around the chip is expanded by expanding the tape to reduce the interference of the peripheral chip, and the chip mounting position of the lead frame or the substrate can be changed from the periphery. By projecting, contact with the periphery of the lead frame or the substrate was avoided. Then, with the semiconductor chip to be mounted attached to the dicing tape, the semiconductor chip is brought close to the lead frame or the substrate, and is pushed up from the back surface with a collet through the dicing film to bring the chip and the frame or the substrate into contact with each other. Here, ultraviolet irradiation or heat treatment is performed so that the fixing force of the semiconductor chip is stronger on the lead frame or substrate side than on the dicing tape side. Thereafter, the lead frame or substrate and the dicing tape are separated, and the semiconductor chip is transferred to the lead frame or substrate. This method eliminates the need to change the chip and increases the chip mounting accuracy.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described below with reference to FIGS.
[0009]
FIG. 1 is a perspective view showing a schematic structure of a semiconductor device of the present invention. The potting resin 105 is written transparent for convenience. The semiconductor chip 101 is mounted on the wiring 104 b provided on the base material 104 a of the intermediate substrate 104, and the periphery is protected by the potting resin 105.
[0010]
FIG. 2 is a longitudinal sectional view illustrating details of the wireless device of the present invention. In order to clearly show the thin film configuration, the film thickness and the like are drawn to be thicker than the actual structure. The semiconductor chip 101 is mounted at a chip mounting position 104c provided in a part of the wiring 104b. The chip mounting position 104 c has a shape that protrudes compared to the surrounding intermediate substrate 104. Further, the semiconductor chip 101 is not fixed only by bonding to the chip mounting position 104c which is a connection portion with the wiring, but is also fixed by the adhesive 104e provided in the vicinity of the chip mounting position 104c. .
[0011]
FIG. 3 shows the structure of the intermediate substrate 104 used for manufacturing the semiconductor device of the present invention. The intermediate substrate 104 is a thin printed substrate having a strip shape as a whole, and a wiring 104b by copper plating is applied on a base material 104a which is a polyimide tape. Feed holes 104b are provided on both sides of the intermediate substrate 104, and stable feed can be performed at high speed in the manufacturing process. The intermediate substrate 104 is provided with a protrusion that later becomes a chip mounting position 104c.
[0012]
4 to 8 sequentially show the manufacturing steps of the semiconductor device of this embodiment.
[0013]
FIG. 4 shows a state immediately before the start of mounting. The wafer attached to the dicing film 501 is diced into individual semiconductor chips 101. Since the interval between the semiconductor chips 101 is too narrow as it is, the dicing film 501 is stretched in advance before the mounting is started to widen the chip interval. In this state, the dicing film 501 is sucked to the lower suction stage 702 and fixed flat. On the other hand, the intermediate substrate 104 on which the semiconductor chip 101 is mounted is sucked flat by the upper suction stage 701 and held downward so that the chip mounting position 104c faces downward. Here, by aligning the relative positions of the lower suction stage 702 and the upper suction stage 701, there is a slight gap at a position where the semiconductor chip 101a to be mounted and the chip mounting position 104c on the intermediate substrate face each other. Arranged.
[0014]
Next, as shown in FIG. 5, the upper collet 601 and the lower collet 602 move to press the semiconductor chip 101 and the intermediate substrate 104. Actually, the dicing tape 501 is more flexible than the base material 104a of the intermediate substrate 104, and is a final discarded member, so that there is no problem even if it is permanently deformed. The lower collet 602 performs most of the movement. When the amount of protrusion at the chip mounting position 104c of the intermediate substrate 104 is small, it is preferable that the amount of movement of the upper collet 601 is slightly increased.
[0015]
Further, since the dicing film 501 is deformed at this time, the semiconductor chip 104b adjacent to the semiconductor chip 101a to be mounted is lifted in addition to the semiconductor chip 101a to be mounted correctly, but is attracted downward by the suction force of the lower suction stage 702. Therefore, the deviation of the adjacent semiconductor chip 101b is small.
[0016]
In this state, both the collets 601 and 602 are heated by the heater, and the semiconductor chip 101 and the intermediate substrate 104 are also heated near the contact portion. At this time, the adhesive 104e is also heated and half-melted to stick the semiconductor chip 101. At the same time, the adhesive strength of the dicing film 501 is reduced by heat treatment and deformation by the lower collet 602.
[0017]
Next, as shown in FIG. 6, the lower collet 602 descends. At the same time, the upper collet 601 also rises slightly. For this reason, heating near the chip is interrupted. At this time, the dicing film 501 deformed more greatly is elastic and tries to return to the original plane, but the adhesive 104e of the intermediate substrate 104 sticks the chip 101, and both hardly move. In this state, the temperatures of the semiconductor chip 101, the intermediate substrate 104, and the adhesive 104e are lowered, and the adhesive force of the adhesive 104e is increased. At this time, the adhesive force of the dicing film 501 hardly recovers due to the temperature drop and remains weak.
[0018]
After that, when the upper suction stage 701 and the upper collet 601 are largely raised as shown in FIG. 7, the adhesive force is increased by cooling than the fixing force of the dicing tape 501 that has already been subjected to the heat treatment and has already reduced the adhesive force. Since the adhesive force of the adhesive 104 e is strong, the semiconductor chip 101 a is peeled off from the dicing tape 501 and moved to the intermediate substrate 104. At the same time, the dicing film 501 is gradually pulled back by the vacuum suction of the lower suction stage 702 and returns to its original shape.
[0019]
These steps are sequentially repeated, and after the semiconductor chips 101 are sequentially mounted on the intermediate substrate 104, the intermediate substrate 104 moves to the next stage potting stage 802 and is fixed by suction as shown in FIG. When the potting resin 110 is dropped from the potting nozzle 801, the semiconductor chip 101 is protected, and at the same time, the fixing of the semiconductor chip 101 and the intermediate substrate 104 is strengthened. Thereafter, circuit portions are individually cut out from the intermediate substrate 104 to obtain the product shape shown in FIG.
[0020]
In this embodiment, since the protrusion amount at the chip mounting position 104a is sufficient, it is possible to sufficiently prevent the adjacent chip mounting position 104c from contacting the irrelevant semiconductor chip 101, and the amount of movement of the upper collet 601 can be minimized. Damage to the intermediate substrate 104 can be minimized.
[0021]
Other examples of the present invention will be shown below.
[0022]
FIG. 9 is a diagram showing an example in which the protrusion amount of the chip mounting position 104c is not sufficiently obtained due to the design limitation, in contrast to the process of FIG. 5 of the first example. At this time, the upper collet 601 is set larger than the movement amount in the first embodiment, and the movement amount of the lower collet 602 is reduced instead. For this reason, the amount of movement of the semiconductor chip 101b other than the semiconductor chip 101 to be mounted is also small, and the chip mounting position 104c to be mounted has obtained a sufficient amount of protrusion compared to the entire intermediate substrate 104. Thus, an irrelevant semiconductor chip 101b or the like does not inadvertently contact the intermediate substrate 104. In this embodiment, since the chip mounting position 104c is protruded by moving the upper collet 601 during mounting, there is no need to provide a large protrusion in the manufacturing process of the intermediate substrate 104, and there is an advantage that the manufacturing process of the intermediate substrate 104 can be simplified. is there.
[0023]
In the first embodiment, an adhesive made of a thermoplastic resin that melts at a high temperature and shows adhesiveness at an intermediate temperature and works as an adhesive at a low temperature is used in the adhesive 104e. It is also possible to use an adhesive made of a thermosetting resin that is cured by heat treatment and exhibits sufficient adhesive strength. In this case, it is difficult to maintain the heating temperature of the collets 601 and 602 at a high temperature sufficient for the reaction of the thermosetting resin for a sufficient time, and generally exceeds the heat resistance temperature of the dicing film 501 that is a thermoplastic resin. . Therefore, heat treatment at the time of mounting the chip is limited to heat treatment sufficient to peel off the semiconductor chip 101 from the dicing film 501, and sufficient heat treatment is performed in a batch before the dropping process of the potting resin 110, so that the adhesive 104e While sufficient curing time is obtained, the dicing film 501 is clear without giving unnecessary thermal fatigue. In this embodiment, since it is not necessary to use a resin exhibiting thermoplasticity at a low temperature for the adhesive 104e, the bonding strength with the potting resin 110 can be increased, and the reflow resistance of the semiconductor device can be increased. There is.
[0024]
【The invention's effect】
According to the present invention, since it is not necessary to flip the chip upside down as compared with the conventional flip chip connection method, it is easy to improve the mounting accuracy. For example, a fine chip of 0.5 mm or less is directly mounted on the substrate from the dicing film. Therefore, a semiconductor device using a finer semiconductor chip can be provided at a low cost.
[Brief description of the drawings]
FIG. 1 is a perspective view showing a schematic structure of a semiconductor device of the present invention.
FIG. 2 is a longitudinal sectional view illustrating details of a semiconductor device according to the present invention.
FIG. 3 is a perspective view showing a structure of an intermediate substrate 104 used in the present invention.
FIG. 4 is an elevation view showing a state of the semiconductor device of the present invention during the manufacturing process;
FIG. 5 is an elevation view showing a state of the semiconductor device of the present invention during the manufacturing process;
FIG. 6 is an elevation view showing a state of the semiconductor device of the present invention during the manufacturing process;
FIG. 7 is an elevation view showing the state of the semiconductor device of the present invention during the manufacturing process;
FIG. 8 is an elevation view showing a state of the semiconductor device of the present invention during the manufacturing process;
FIG. 9 is a diagram showing another embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Package (the whole) 101 ... IC chip 104 ... Intermediate substrate 104a ... Base material 104b ... Wiring 104c ... Chip mounting position 104d ... Feed hole 104e ... Adhesive 110 ... Protective resin 501 ... Dicing Tape, 601 ... upper collet, 602 ... lower collet, 701 ... upper suction stage, 702 ... lower suction stage, 801 ... potting nozzle, 802 ... potting stage.

Claims (5)

ウェハのダイシングにより得られた個々の半導体チップを配線が形成された基材上に順次搭載する半導体装置の製造方法であって、
ダイシングフィルムの第１面に貼り付けた前記ウェハをダイシングして、前記個々の半導体チップを得た後に、
前記ダイシングフィルムを引き延ばして、該ダイシングフィルムに貼り付いている前記半導体チップの間隔を拡げる第１工程、
前記引き延ばされたダイシングフィルムを、前記半導体チップの一つとこれが搭載される前記基材の前記配線の一部に設けられたチップ搭載位置との相対位置を合わせながら、該基材の前記配線が形成された面に、隙間を介して対向させる第２工程、
前記基材の前記配線が形成された面とは反対側の裏面に当てた第１コレットと、前記引き延ばされたダイシングフィルムの前記第１面とは反対側の第２面に当てた第２コレットとで、前記半導体チップの一つを前記基材の前記チップ搭載位置に押しつけ且つ該一つの半導体チップとこれに接触する該基材の該チップ搭載位置を加熱する第３工程、及び
前記第１コレットを前記基材の前記裏面から、前記第２コレットを前記引き延ばされたダイシングフィルムの前記第２面から夫々離して、前記基材の前記チップ搭載位置に接着された前記半導体チップの一つをダイシングフィルムから引き剥がす第４工程を順次繰り返して行い、
前記基材の前記一つの半導体チップの搭載位置付近に設けられた接着剤を、前記第３工程で加熱して半溶融させ且つ前記第４工程で冷却することにより、該一つの半導体チップを該チップ搭載位置に接着させ、
前記第３工程において、前記半導体チップの一つに隣接して前記引き延ばされたダイシングフィルムに貼られている該半導体チップの他が前記基材に接触しないように、前記第１コレットで該基材の前記チップ搭載位置を該ダイシングフィルムに向けて、前記第２コレットで該ダイシングフィルムの該一つの半導体チップが搭載された部分を該基材に向けて、夫々突き出させることを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device in which individual semiconductor chips obtained by dicing a wafer are sequentially mounted on a substrate on which wiring is formed,
After dicing the wafer attached to the first surface of the dicing film to obtain the individual semiconductor chips,
A first step of extending the dicing film to widen the interval between the semiconductor chips attached to the dicing film;
The wiring of the base material is adjusted while the relative position of one of the semiconductor chips and the chip mounting position provided on a part of the wiring of the base material on which the semiconductor chip is mounted is adjusted. A second step of facing the surface on which is formed through a gap,
A first collet applied to the back surface of the substrate opposite to the surface on which the wiring is formed, and a first collet applied to the second surface opposite to the first surface of the stretched dicing film. A third step of pressing one of the semiconductor chips against the chip mounting position of the substrate and heating the chip mounting position of the substrate contacting the one semiconductor chip with two collets; and The semiconductor chip bonded to the chip mounting position of the base material by separating the first collet from the back surface of the base material and the second collet from the second surface of the stretched dicing film. The fourth step of peeling one of the films from the dicing film is sequentially repeated,
By cooling the adhesives provided on the tower the placement near position before SL single semiconductor chip, in front Symbol 且 one said fourth step with pressurized hot is semi-molten by about a third Engineering of the substrate , the one half-conductor chip is adhered to the chip mounting position,
In the third step, the first collet is used to prevent the other of the semiconductor chips attached to the stretched dicing film adjacent to one of the semiconductor chips from contacting the base material. The chip mounting position of the base material is directed toward the dicing film, and the portion where the one semiconductor chip of the dicing film is mounted by the second collet is protruded toward the base material, respectively. A method for manufacturing a semiconductor device. 前記接着剤として、熱可塑性樹脂を用いることを特徴とする請求項１に記載の半導体装置の製造方法。  The method for manufacturing a semiconductor device according to claim 1, wherein a thermoplastic resin is used as the adhesive. 前記第４工程の後に、前記半導体チップの一つとこれが接着された前記基材の前記面にポッティングレジンを滴下して、該一つの半導体チップを保護し且つ該一つの半導体チップと該基材との固定を強化する第５工程を行うことを特徴とする請求項１に記載の半導体装置の製造方法。  After the fourth step, a potting resin is dropped onto one of the semiconductor chips and the surface of the substrate to which the semiconductor chip is bonded to protect the one semiconductor chip and the one semiconductor chip and the substrate. The method of manufacturing a semiconductor device according to claim 1, wherein a fifth step of strengthening the fixing of the semiconductor device is performed. 前記接着剤として熱硬化性樹脂を用い、
第５工程の前に、前記第３工程での前記一つの半導体チップ及びこれに接する前記基材の加熱とは別の熱処理を行うことにより、該接着剤を硬化させることを特徴とする請求項３に記載の半導体装置の製造方法。Using a thermosetting resin as the adhesive,
The adhesive is hardened by performing a heat treatment different from the heating of the one semiconductor chip and the base material in contact with the semiconductor chip in the third step before the fifth step. 4. A method for manufacturing a semiconductor device according to 3. 前記第３工程において、前記一つの半導体チップに対する前記ダイシングフィルムの粘着性を低下させることを特徴とする請求項１の半導体装置の製造方法。  2. The method of manufacturing a semiconductor device according to claim 1, wherein in the third step, the adhesiveness of the dicing film to the one semiconductor chip is lowered.
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