JP3981636B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Technical field
The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device such as a flash memory that can be electrically rewritten.
Background art
Among nonvolatile semiconductor memory devices that can be electrically rewritten, a so-called flash memory is known as a device capable of batch erasure. Flash memory has excellent portability and shock resistance, and can be erased electrically. In recent years, flash memory is rapidly in demand as a file (storage device) for small portable information devices such as portable personal computers and digital still cameras. It is expanding. In order to expand the market, reduction of the bit cost by reducing the memory cell area is an important factor. For example, January 10, 1996, published by the Japan Society of Applied Physics, “Applied Physics” Vol. 65, No. 11, p1114 to p1124 Various memory cell systems for realizing this have been proposed.
Disclosure of the invention
As another memory cell system described above, there is a virtual ground type memory cell using a three-layer polysilicon gate proposed by the present inventors (Japanese Patent Application No. 11-200242).
This memory cell is shown in FIG. (A) is a plan view, and (b), (c) and (d) are cross-sectional views taken along lines AA ′, BB ′ and CC ′ in (a), respectively.
This memory cell has a source / drain diffusion layer 205 in the well 101 formed on the main surface of the semiconductor substrate 100, a first gate (floating gate) 103b, a second gate (control gate) 111a, and a third gate 107a. The control gate (second gate) 111a of each memory cell is connected in the row direction (x direction) to form a word line WL.
The floating gate (first gate) 103b and the well 101 are formed by the gate insulating film (first insulating film) 102, and the floating gate 103b and the third gate 107a are formed by the green film (third insulating film) 106a. The line (control gate) 111a is separated by the insulating film (second green film) 110a, and the third gate 107a and the word line 111a are separated by the green film 108a.
The source / drain diffusion layer 205 is arranged extending in the direction (y direction) perpendicular to the extending direction (x direction) of the word line 111a, and connects the source / drain of the memory cells in the column direction (y direction). Functions as a local source line and a local data line. In other words, this nonvolatile semiconductor memory device is constituted by a so-called contactless type array having no contact hole for each memory cell. A channel is formed in a direction perpendicular to the diffusion layer 105 (x direction). Further, in the source / drain diffusion layer 205, the pair of diffusion layers 205 forming the source / drain is in a non-target positional relationship with respect to the floating gate pattern 103a, and one diffusion layer is both the floating gate and the third gate. It has a structure that overlaps.
The two end faces of the third gate 107a are opposed to the two end faces perpendicular to the word line 111a and the channel, respectively, of the end face of the floating gate 103b via the insulating film 106a.
The third gate 107a is buried in a gap between the floating gate 103b existing in the direction (y direction) perpendicular to the word line 111a and the channel. Further, the floating gate 103b exists symmetrically with respect to the third gate 107a, and the third gate 107a exists symmetrically with respect to the floating gate 103b.
In such a structure, even when the third gate 107a other than the floating gate 103a and the control gate 111a exists, the pitch in the word line WL direction (x direction) and the local data line direction (y direction) is minimized. The processing dimension can be doubled. Therefore, the memory cell area is minimum 4F in the cross-point type array. ² It becomes possible to reduce to (F: minimum processing dimension).
The memory cell enables not only miniaturization but also high-speed writing. FIG. 2A shows the voltage application conditions at the time of memory cell writing, and FIGS. 2B and 2C show the operation method. As shown in FIG. 2B, a positive voltage of about 5 V, for example, is applied to the diffusion layer Dn serving as the drain of the selected memory cell M at the timing of time t0, and the selected memory cell M at the timing of time t1. A positive voltage of about 12 V, for example, is applied to the word line WLn, and a voltage about the threshold value of the MOS transistor configured by the third gate AGe of the selected memory cell M at the timing of time t2, for example, Apply about 0.6V. The diffusion layer Dn−1, well, and unselected word line WLn + 1 that are the sources of the selected memory cell M are held at 0V. By the above operation, a large horizontal method and a vertical electric field are formed in the channel below the boundary between the floating gate and the third gate. This increases the generation and injection efficiency of hot electrons, and enables high-speed writing despite the small channel current. As a result, even when an internal power supply having a current supply capability of about 1 mA is used, parallel writing of memory cells of kilobytes or more becomes possible. The above operation can also be performed by switching the voltage application timings of the word line WLn, the diffusion layer Dn, and the third gate AGe of the selected memory cell, as shown in FIG.
However, several problems arise in the above-described memory cell writing method. First, in the above writing method, the third gate AG is operated by applying a voltage about the threshold value of the MOS transistor constituted by the third gate, so that the dimensional variation of the third gate AG, The variation in voltage greatly affects the write characteristics of the memory cell. FIG. 3 shows the relationship between the voltage applied to the third gate, the channel current, and the gate current. As shown in FIG. 3, it can be seen that the gate current Ig changes exponentially in the vicinity of a voltage of about 0.6 V of the third gate AG during operation. For example, when the third gate AG voltage varies by ± 0.1 V, the gate current Ig varies by about 1.3 digits.
In addition, since the internal power supply for supplying the channel current operates at the time of writing, there is a possibility that the third gate AG voltage changes due to noise from the internal power supply. As described above, since the write characteristics of the memory cell are greatly affected by the third gate AG voltage, there is a possibility that the characteristics will vary even with a minute driving noise from the internal power supply.
The write operation is performed by repeatedly applying a write bias and verifying the threshold until all the thresholds of a plurality of memory cells to be simultaneously written reach a desired value. For this reason, if there are variations in the characteristics of the memory cells, the number of repetitions of application of the write bias and threshold verification increases, and the write time becomes longer. Therefore, it is expected that the memory writing time will increase due to the influence of the size variation of the third gate AG, the variation of the voltage applied to the third gate AG, and the drive noise from the internal power supply.
Further, in order to realize a multi-value memory capable of storing data of 2 bits or more per memory cell, it is necessary to suppress the threshold voltage distribution width corresponding to each data. This greatly increases the memory write time.
An object of the present invention is to provide a nonvolatile semiconductor memory device that is suitable for miniaturization and absorbs variation in write characteristics associated with a memory cell having a high operation speed and realizes a high write speed.
The above problem can be solved by the following means. As shown in FIG. 3, the gate current Ig is greatly affected by the AG bias, but the injection efficiency γ is less affected by the AG than the gate current. For example, when AG varies ± 0.1 V around an AG voltage of about 0.6 V during operation, the variation in injection efficiency is about 0.3 digits. Therefore, if charge is stored in a certain capacity and only the charge stored in the capacity is supplied to the memory cell for writing, the variation in the write characteristics can be suppressed to the level of the injection efficiency. Similarly, if writing is performed by accumulating charges in a certain capacity via the memory cell, it is possible to suppress the variation in the write characteristics to the extent of the injection efficiency.
Some of the points of the present invention are listed below.
Writing or erasing is performed by discharging the charge from the capacitor through the memory cell or charging the capacitor and injecting hot electrons into the charge storage portion of the memory cell. As a result, it is possible to increase the speed of the write operation or erase operation to the memory cell.
Further, by using the parasitic capacitance of the bit line including the pn junction capacitance of the diffusion layer as the capacitance, the above speeding up can be achieved without specially changing the structure of the nonvolatile semiconductor memory device.
In addition, when injecting charges into the charge storage section, the internal power supply circuit for generating a voltage to be applied to the bit line is deactivated, thereby suppressing characteristic fluctuation due to operation noise caused by the internal power supply. It becomes possible.
Further, after repeating the write or erase operation a plurality of times, the threshold verification operation of the memory cell is performed, and further, by increasing the number of repetitions of the write or erase operation for each threshold verification operation, The increase in speed can be made more remarkable.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
<Example 1>
A first embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a circuit diagram focusing on one memory cell in the memory array configuration shown in FIG. 2, and FIG. 5 shows a write operation system in this embodiment. As shown in FIG. 5, the internal power supply PROG that supplies the channel current is raised to 5 V at the time t0, and the STS and STD that are the switching MOSs on the source side and the drain side of the selected memory cell are turned on at the time t1. In the ON state, a write voltage of 12 V is applied to the word line WL of the selected memory cell at time t2. Next, when the node ND on the drain side of the memory cell is charged to 5 V, STD which is the drain side switch MOS is turned off at the timing of time t3, and is disconnected from the internal power supply PROG. By applying about 0.6 V to the third gate AG of the selected memory cell at the timing of time t4, the charge accumulated in the node ND starts to flow to the source side through the memory cell. At this time, hot electrons generated in the channel region of the memory cell are injected into the floating gate to cause writing. Although the potential of the node ND on the drain side decreases as the channel current flows, writing occurs while a horizontal electric field high enough to generate hot electrons is generated in the channel portion.
The present embodiment will be described more specifically with reference to FIGS. FIG. 6 shows an example of the memory array configuration shown in FIG. 1, and FIG. 7 shows the write operation in this embodiment. In FIG. 6, nodes D00 to 03 and D10 to 13 corresponding to the source and drain of the memory cell are formed by diffusion layer wiring, and for example, 128 memory cells are arranged in parallel on the same diffusion layer wiring. Yes. The diffusion layer wiring is connected to bit lines DL0 and DL1 made of metal via a selection transistor, and the selection transistor is controlled by signals ST00, ST01, ST12 and ST13. Further, the diffusion layer wiring is connected to a common source line SS via a selection transistor, and the selection transistor is controlled by signals ST02, ST03, ST10, ST11. As the common source line SS, a diffusion layer wiring or a diffusion layer wiring shunted with metal to reduce wiring resistance is used. In FIG. 6, two diffusion layer wirings are connected to one metal bit line by two selection transistors, but N diffusion layer wirings are connected to one metal bit line by N selection transistors. It does not matter if they are connected. Similarly, in FIG. 6, two diffusion layer wirings are connected to one common source line by two selection transistors, but N diffusion layer wirings are connected to one common source by N selection transistors. It may be connected to the line. Metal bit lines DL0 and DL1 are connected to control circuits PC0 and PC1 through switch MOSs, respectively.
The operation of the present embodiment will be described using the timing waveform of FIG. Here, it is assumed that the memory cell to be written is the word line WL00. First, when a write command and write data are input, the common source line SS is raised to about 5V at time t0. Next, TR is raised at the timing of time t1 to connect the control circuit and the bit line. At this time, the control circuit outputs a voltage corresponding to the write data to the bit line. For example, 0 V is output to the bit line corresponding to the write selected memory cell, and 1 V is output to the bit line corresponding to the write unselected memory cell. Thereafter, the gate signal ST03 of the selection transistor is set to the High state at the timing of time t2, and the diffusion layer wirings D02 and D04 are charged to 5V. Next, at time t3, the gate signal ST01 of the selection transistor is set to the high state, and the bit lines DL0 and DL1 are connected to the diffusion layer wirings D01 and D03, respectively. Here, D01 and D03 are 0V when writing is selected and 1V when writing is not selected. Further, after the selected word line WL00 is raised to the write voltage, for example, 12 V at the timing of time t4, the gate signal ST03 of the selection transistor is set to LOW at the timing of time t5, and the diffusion layer wirings D02 and D04 are disconnected from the common source line. Thereafter, a write voltage, for example, about 0.6 V is applied to AG01 which is the selected AG gate. When the memory cell M01 is a write selection cell, D01 is 0V, D02 is 5V, the word line WL00 is 12V, and the AG gate is 0.6V, so that electrons are injected into the floating gate. At this time, since D02 is charged to 5V and then is in a floating state, as the channel current flows through the memory cell M01, the potential drops and finally becomes 0V. At this time, electrons are injected into the floating gate while the potential of D02 is a bias sufficient to generate hot electrons. On the other hand, when the memory cell M01 is not selected, D01 is 1V, D02 is 5V, the word line WL00 is 12V, and AG01 is about 0.6V. Electron injection does not occur. The capacitance of the diffusion layer wiring is mainly a pn junction capacitance, and is about 0.3 pF in the array configuration of this embodiment.
Next, AG01 falls at the timing of time t7, and WL00 and SS fall at the timing of time t8. Further, TR is lowered at the timing of time t9, the connection between the control circuit and the bit line is disconnected, and the operation of injecting electrons into the floating gate is completed by discharging the bit line and the diffusion layer wiring to 0V.
Thereafter, a verification operation is performed to determine whether or not the threshold value has reached a desired value, and the above-described electron injection operation is subsequently performed on memory cells that have not reached the desired threshold value. Writing is terminated when all the memory cells to be written reach a desired threshold voltage.
As a result, it is possible to reduce write variations due to AG bias fluctuations and reduce the number of write verifications, thereby shortening the time required for writing.
In addition, since it is not necessary to start up the internal power supply that supplies 5V of the write bias during writing, it is possible to suppress fluctuations in the write characteristics due to operation noise of the internal power supply by making this inactive. In addition, power consumption can be reduced.
In the above description, the operation for increasing the threshold value is described as writing, but the present invention can also be applied to the case where the operation for increasing the threshold value is erased.
In addition, when the memory cell is a so-called multi-level memory that can take two or more threshold states, the effect of the present system becomes more remarkable. In a multi-level memory, it is necessary to control a threshold corresponding to data with high accuracy. Therefore, if the writing variation is large, there is a problem that the number of threshold verifications increases and the writing speed decreases. Since this method can reduce writing variations, the number of threshold verifications can be suppressed, and the writing speed can be increased.
The same effect can be obtained even if the charge storage node in this embodiment is a memory cell formed of a silicon nitride film or a laminated film of a silicon nitride film and a silicon oxide film instead of the polysilicon film. Is possible.
Further, the same effect can be obtained even if the charge storage node is a memory cell formed of a plurality of polysilicon spheres formed in a dot shape instead of the polysilicon film.
Further, when the silicon nitride film or dot-like polysilicon sphere is used as the charge storage part, a polysilicon gate having the same function as the third gate is provided on both sides of the charge storage part via the silicon oxide film. The same effect can be obtained even if the memory cell is provided. In this case, the charge storage unit can discretely hold charges at two locations close to the adjacent polysilicon gates, and multi-value storage can be realized by the difference in the charge storage location.
<Example 2>
A second embodiment of the present invention will be described with reference to FIGS. FIG. 8 shows the write operation method of the present embodiment in the array configuration shown in FIG. The array configuration in FIG. 6 is as shown in the first embodiment, and it is assumed that the memory cell for writing is the word line WL00.
First, when a write command and write data are input, ST02 is raised at the timing of time t0, and the diffusion layer wirings D01 and D03 are connected to the common source line. Next, TR is set to a high state at the timing of time t1, and the control circuits PC0 and PC1 are connected to the metal bit lines DL0 and DL1, respectively. At this time, the control circuit outputs a write voltage, for example, 5 V to the bit line corresponding to the write selected memory cell, and 0 V to the bit line corresponding to the write unselected memory cell. After the write-selected bit line is charged to 5 V, the gate signal ST00 of the selection transistor is turned on at time t2, and the bit line and the diffusion layer wiring are connected. By this operation, the diffusion layer wirings D02 and D04 are charged to 5V when writing is selected and to 0V when writing is not selected. Thereafter, the selected word line WL00 is raised to 12 V at the timing of time t3, TR is turned off at the timing of time t4, the connection between the control circuit and the bit line is disconnected, and the bit line is set in a floating state. Next, at the timing of time t5, the selected AG gate AG01 is set to a write voltage, for example, 0.6V, and a channel current is passed through the selected memory cell.
For example, when the memory cell M01 is a write selection cell, D01 is 0V, D02 is 5V, the word line WL00 is 12V, and the AG gate is 0.6V, so that electrons are injected into the floating gate. At this time, since D02 and the bit line DL0 are in a floating state after being charged to 5V, as the channel current flows through the memory cell M01, the potential decreases and finally becomes 0V. At this time, electrons are injected into the floating gate while the potentials of D02 and bit line DL0 are sufficiently biased to generate hot electrons. On the other hand, when the memory cell M01 is not selected, D01 is 0V, D02 is 0V, the word line WL00 is 12V, and AG01 is about 0.6V. Electron injection does not occur. In the first embodiment, the node for storing the charge is the diffusion layer wiring portion, whereas in this embodiment, the diffusion layer wiring portion and the bit line portion are used, so that more charges can be stored. . For example, the parasitic capacitance of the bit line portion is about 1.0 pF, and when combined with the diffusion layer wiring portion, it is about 1.3 pF. Therefore, more charges can be accumulated than in the first embodiment, and more electrons can be injected into the floating gate in one electron injection operation.
Next, AG01 falls at the timing of time t6, and WL00 falls at the timing of time t7. Furthermore, ST03 is raised at the timing of time t8, the diffusion layer wirings D02 and D04 are connected to the common source line SS, and discharged to 0 V, thereby completing the electron injection operation to the floating gate.
Thereafter, a verification operation is performed to determine whether or not the threshold value has reached a desired value, and the above-described electron injection operation is subsequently performed on memory cells that have not reached the desired threshold value. Writing is terminated when all the memory cells to be written reach a desired threshold voltage.
As a result, it is possible to reduce write variations due to AG bias fluctuations and reduce the number of write verifications, thereby shortening the time required for writing.
In addition, since it is not necessary to start up the internal power supply for supplying 5 V of the write bias during writing, it is possible to suppress fluctuations in the write characteristics due to operation noise caused by the internal power supply by leaving it in an inactive state. Is possible.
In the above description, the operation for increasing the threshold value is described as writing, but the present invention can also be applied to the case where the operation for increasing the threshold value is erased.
In addition, when the memory cell is a so-called multi-level memory that can take two or more threshold states, the effect of the present system becomes more remarkable. In a multi-level memory, it is necessary to control a threshold corresponding to data with high accuracy. Therefore, if the writing variation is large, there is a problem that the number of threshold verifications increases and the writing speed decreases. Since this method can reduce writing variations, the number of threshold verifications can be suppressed, and the writing speed can be increased.
Further, as compared with the case of the first embodiment, more charges can be accumulated, and there is an advantage that more electrons can be injected into the floating gate by one electron injection operation.
The same effect can be obtained even if the charge storage node in this embodiment is a memory cell formed of a silicon nitride film or a laminated film of a silicon nitride film and a silicon oxide film instead of the polysilicon film. Is possible.
Further, the same effect can be obtained even if the charge storage node is a memory cell formed of a plurality of polysilicon spheres formed in a dot shape instead of the polysilicon film.
Further, when the silicon nitride film or dot-like polysilicon sphere is used as the charge storage part, a polysilicon gate having the same function as the third gate is provided on both sides of the charge storage part via the silicon oxide film. The same effect can be obtained even if the memory cell is provided. In this case, the charge storage unit can discretely hold charges at two locations close to the adjacent polysilicon gates, and multi-value storage can be realized by the difference in the charge storage location.
<Example 3>
A third embodiment of the present invention will be described with reference to FIGS. 6 and 9 to 11. FIG. 9 is a circuit diagram focusing on one memory cell in the memory array configuration shown in FIG. 2, and FIG. 10 shows a write operation method in this embodiment. As shown in FIG. 10, the internal power supply PROG for supplying a channel current is raised to 5 V at the timing of time t0, and STS and STD which are switching MOSs on the source side and the drain side of the selected memory cell are turned on at the timing of time t1. In the ON state, a write voltage of 12 V is applied to the word line WL of the selected memory cell at time t2. Next, at the timing of time t3, the STS that is the source side switching MOS is turned off, and the node NS is brought into a floating state. Thereafter, by applying about 0.6 V to the AG of the selected memory cell at the timing of time t4, a current starts to flow from the internal power supply PROG to the memory cell via the STD that is the switching MOS. At this time, hot electrons generated in the channel region of the memory cell are injected into the floating gate to cause writing. Although the drain-side node ND is constant at a write voltage, for example, 5 V, the potential of the source-side node NS rises as the channel current flows. When the potential of the node NS rises and the MOS composed of the AG gate portion is turned off, writing is stopped.
The first embodiment and the second embodiment described above are characterized in that the stored charges are written by hot electrons generated when the memory cells flow, but in this embodiment, the memory cells are connected via the memory cells. Charges are accumulated in a certain capacity, and writing is performed by hot electrons generated at that time.
This embodiment will be described more specifically with reference to FIGS. FIG. 11 shows the write operation method of the present embodiment in the array configuration shown in FIG. The array configuration in FIG. 6 is as shown in the first embodiment, and it is assumed that the memory cell for writing is the word line WL00. First, when a write command and write data are input, ST02 is raised at the timing of time t0, and the diffusion layer wirings D01 and D03 are connected to the common source line. Next, TR is set to the high state at the timing of time t1, and the control circuits PC0 and PC1 are connected to the bit lines DL0 and DL1, respectively. At this time, the control circuit outputs a write voltage, for example, 5 V to the bit line corresponding to the write selected memory cell, and 0 V to the bit line corresponding to the write unselected memory cell. After the write-selected bit line is charged to 5 V, the gate signal ST00 of the selection transistor is turned on at time t2, and the bit line and the diffusion layer wiring are connected. By this operation, the diffusion layer wirings D02 and D04 are charged to 5V when writing is selected and to 0V when writing is not selected. Thereafter, the selected word line WL00 is raised to 12V at the timing of time t3, ST02 is turned off at the timing of time t4, and the connection between the common source line and the diffusion layer wirings D01 and D03 is disconnected. Next, at the timing of time t5, the selected AG gate AG01 is set to a write voltage, for example, 0.6V, and a channel current is passed through the selected memory cell. For example, when the memory cell M01 is a write selection cell, D01 is 0V, D02 is 5V, the word line WL00 is 12V, and the AG gate is 0.6V, so that electrons are injected into the floating gate. At this time, when the potential of D01 rises as the channel current flows through the memory cell M01 and the MOS composed of the AG gate portion is turned off, writing is stopped. On the other hand, when the memory cell M01 is not selected, D01 is 0V, D02 is 0V, the word line WL00 is 12V, and AG01 is about 0.6V. Electron injection does not occur. Next, AG01 falls at the timing of time t6, and WL00 and TR fall at the timing of time t7. Further, ST01, ST02, ST03 are raised at the timing of time t8, and the bit line and the diffusion layer wiring are discharged to 0 V, thereby completing the electron injection operation to the floating gate.
Thereafter, a verification operation is performed to determine whether or not the threshold value has reached a desired value, and the above-described electron injection operation is subsequently performed on memory cells that have not reached the desired threshold value. Writing is terminated when all the memory cells to be written reach a desired threshold voltage.
As a result, it is possible to reduce write variations due to AG bias fluctuations and reduce the number of write verifications, thereby shortening the time required for writing.
In the above description, the operation for increasing the threshold value is described as writing, but the present invention can also be applied to the case where the operation for increasing the threshold value is erased.
In addition, when the memory cell is a so-called multi-level memory that can take two or more threshold states, the effect of the present system becomes more remarkable. In a multi-level memory, it is necessary to control a threshold corresponding to data with high accuracy. Therefore, if the writing variation is large, there is a problem that the number of threshold verifications increases and the writing speed decreases. Since this method can reduce writing variations, the number of threshold verifications can be suppressed, and the writing speed can be increased.
The same effect can be obtained even if the charge storage node in this embodiment is a memory cell formed of a silicon nitride film or a laminated film of a silicon nitride film and a silicon oxide film instead of the polysilicon film. Is possible.
Further, the same effect can be obtained even if the charge storage node is a memory cell formed of a plurality of polysilicon spheres formed in a dot shape instead of the polysilicon film.
Further, when the silicon nitride film or dot-like polysilicon sphere is used as the charge storage part, a polysilicon gate having the same function as the third gate is provided on both sides of the charge storage part via the silicon oxide film. The same effect can be obtained even if the memory cell is provided. In this case, the charge storage unit can discretely hold charges at two locations close to the adjacent polysilicon gates, and multi-value storage can be realized by the difference in the charge storage location.
<Example 4>
A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 12 shows the write operation method of this embodiment in the array configuration shown in FIG. The array configuration in FIG. 6 is as shown in the first embodiment, and it is assumed that the memory cell for writing is the word line WL00.
First, when a write command and write data are input, the common source line SS is raised to about 5V at time t0. Next, TR is raised at the timing of time t1 to connect the control circuit and the bit line. At this time, the control circuit outputs a voltage corresponding to the write data to the bit line. For example, 0 V is output to the bit line corresponding to the write selected memory cell, and 1 V is output to the bit line corresponding to the write unselected memory cell. Thereafter, the gate signal ST03 of the selection transistor is set to the High state at the timing of time t2, and the diffusion layer wirings D02 and D04 are charged to 5V. Next, at time t3, the gate signal ST01 of the selection transistor is set to the high state, and the bit lines DL0 and DL1 are connected to the diffusion layer wirings D01 and D03, respectively. Here, D01 and D03 are 0V when writing is selected and 1V when writing is not selected.
Further, after the selected word line WL00 is raised to the write voltage, for example, 12 V at the timing of time t4, TR is set to the LOW state at the timing of time t5, and the bit lines DL0 and DL1 are disconnected from the control circuit. Thereafter, a write voltage, for example, about 0.6 V is applied to AG01 which is the selected AG gate. When the memory cell M01 is a write selection cell, DL0 and D01 are 0V, D02 is 5V, the word line WL00 is 12V, and the AG gate is 0.6V, so that electrons are injected into the floating gate. At this time, since the bit line DL0 is in a floating state, as the channel current flows through the memory cell M01, the electric charge is charged to increase the potential, and the MOS configured by the AG gate portion is turned off. Writing stops. In the third embodiment, the node for charging the charge is the diffusion layer wiring portion, whereas in this embodiment, the diffusion layer wiring portion and the bit line portion are used, so that a larger amount of charge can be charged. For example, the parasitic capacitance of the bit line portion is about 1.0 pF, and when combined with the diffusion layer wiring portion, it is about 1.3 pF. Therefore, more charges can be accumulated than in the first embodiment, and more electrons can be injected into the floating gate in one electron injection operation.
On the other hand, when the memory cell M01 is not selected, D01 and DL0 are 1V, D02 is 5V, the word line WL00 is 12V, and AG01 is about 0.6V. There is no electron injection.
Next, AG01 falls at the timing of time t7, and WL00 and SS fall at the timing of time t8. Further, ST00 is raised at the timing of time t9, and the bit line and the diffusion layer wiring are discharged to 0 V, thereby completing the electron injection operation to the floating gate.
Thereafter, a verification operation is performed to determine whether or not the threshold value has reached a desired value, and the above-described electron injection operation is subsequently performed on memory cells that have not reached the desired threshold value. Writing is terminated when all the memory cells to be written reach a desired threshold voltage.
As a result, it is possible to reduce write variations due to AG bias fluctuations and reduce the number of write verifications, thereby shortening the time required for writing.
In the above description, the operation for increasing the threshold value is described as writing, but the present invention can also be applied to the case where the operation for increasing the threshold value is erased.
In addition, when the memory cell is a so-called multi-level memory that can take two or more threshold states, the effect of the present system becomes more remarkable. In a multi-level memory, it is necessary to control a threshold corresponding to data with high accuracy. Therefore, if the writing variation is large, there is a problem that the number of threshold verifications increases and the writing speed decreases. Since this method can reduce writing variations, the number of threshold verifications can be suppressed, and the writing speed can be increased.
Furthermore, as compared with the case of the third embodiment, more charges can be charged, and there is an advantage that more electrons can be injected into the floating gate by one electron injection operation.
The same effect can be obtained even if the charge storage node in this embodiment is a memory cell formed of a silicon nitride film or a laminated film of a silicon nitride film and a silicon oxide film instead of the polysilicon film. Is possible.
Further, the same effect can be obtained even if the charge storage node is a memory cell formed of a plurality of polysilicon spheres formed in a dot shape instead of the polysilicon film.
Further, when the silicon nitride film or dot-like polysilicon sphere is used as the charge storage part, a polysilicon gate having the same function as the third gate is provided on both sides of the charge storage part via the silicon oxide film. The same effect can be obtained even if the memory cell is provided. In this case, the charge storage unit can discretely hold charges at two locations close to the adjacent polysilicon gates, and multi-value storage can be realized by the difference in the charge storage location.
<Example 5>
A fifth embodiment of the present invention will be described with reference to FIGS. FIG. 13 shows a circuit configuration in the present embodiment. The memory array MA in the figure includes, for example, IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 7, JULY 2000, p359 to p361, which is an electrically rewritable memory cell known as an SST type memory cell, arranged in an array. The memory cell is written by applying a voltage of about 0 V to the well, about 2 V to the control gate, about 0.5 V to the drain, and about 10 V to the source, and applying it to the floating gate by the SSI method (SSI: Source Side Injection). This is done by injecting electrons. The erase operation is performed by applying about 12 V to the control gate and 0 V to the source, drain, and well, and extracting the electrons accumulated in the floating gate to the control gate. Further, the read operation is performed by measuring the memory cell current by applying about 3V to the control gate, about 2V to the drain and 0V to the source and well.
In the write operation in the present memory cell, the control gate is operated by applying a voltage about the threshold value of the MOS transistor formed by the control gate portion. It greatly affects the writing characteristics. This is the same as the case of the memory cell with AG gate described in the first to fourth embodiments. The present embodiment is to reduce the variation at the time of writing in the above memory array configuration, and is characterized in that a capacitive element is provided between the write control circuit and each memory cell. Hereinafter, this embodiment will be described in detail with reference to FIGS. 13 and 14. The write selection cell is M00. First, when a write command and write data are input, the source lines SS0 and SS1 are raised to about 10V at time t0. Next, a voltage corresponding to the write data is output from the write control circuit 50 to the bit line at time t1. Assuming that the bit line DL0 is a selected bit line and the bit line DL1 is a non-selected bit line, 0.5V is applied to DL0 and 2V is applied to DL1. When the charging of the bit line is completed, the connection between the write control circuit 50 and the bit line is disconnected, and thereafter, the selection control gate WL0 is raised to 2V at the timing of time t2. In the selected memory cell M00, 2V is applied to the control gate, 10V to the source, 0.5V to the drain, and 0V to the well, so that electrons are injected into the floating gate. On the other hand, although 2 V is applied to the control gate, 10 V to the source, and 0 V to the well in the non-programmed memory cell M10, channel current does not flow through the memory cell because 2 V is applied to the drain. Absent. At this time, a capacitor C0 is connected to DL0, and charges are accumulated in the capacitor C0 as a channel current flows through the memory cell M00. When charge is accumulated in C0 and the potential of DL0 rises to a certain voltage, the memory cell M00 is turned off and writing is stopped. Thereafter, the control gate WL0 is lowered at the timing of time t3, and the source lines SS0 and SS1 and the bit lines DL0 and DL1 are discharged to 0 V at the timing of time t4 to complete the electron injection operation.
Thereafter, a verification operation is performed to determine whether or not the threshold value has reached a desired value, and the above-described electron injection operation is subsequently performed on memory cells that have not reached the desired threshold value. Writing is terminated when all the memory cells to be written reach a desired threshold voltage.
As a result, it is possible to reduce write variations due to fluctuations in the control gate bias, and the number of write verifications can be reduced, so that the time required for writing can be shortened.
The above effect can also be realized in a configuration in which a write capacitor C is provided between the decoder circuit 51 for decoding a plurality of bit lines and the write control circuit as shown in FIG. In the case of this configuration, the write capacitance value can be set large in order to be shared by a plurality of bit lines.
Further, the above-described capacitive element may be a parasitic capacitance of a bit line made of metal. Further, it may be a MIM (Metal-Insulator-Metal) structure in which an insulating film is sandwiched between metals, or a MOS circuit structure often used in a normal circuit structure.
In the above description, the operation for raising the threshold value is described as writing, but the present invention can be applied to the case where the operation for raising the threshold value is erased.
In addition, when the memory cell is a so-called multi-level memory that can take two or more threshold states, the effect of the present system becomes more remarkable. In a multi-level memory, it is necessary to control a threshold corresponding to data with high accuracy. Therefore, if the writing variation is large, there is a problem that the number of threshold verifications increases and the writing speed decreases. Since this method can reduce writing variations, the number of threshold verifications can be suppressed, and the writing speed can be increased.
In this embodiment, the charge storage node is formed of a silicon nitride film, a laminated film of a silicon nitride film and a silicon oxide film, or a plurality of polysilicon spheres formed in a dot shape instead of the polysilicon film. Similar effects can be obtained even with cells.
Further, when the silicon nitride film or dot-like polysilicon sphere is used as the charge storage part, a polysilicon gate having the same function as the third gate is provided on both sides of the charge storage part via the silicon oxide film. The same effect can be obtained even if the memory cell is provided. In this case, the charge storage unit can discretely hold charges at two locations close to the adjacent polysilicon gates, and multi-value storage can be realized by the difference in the charge storage location.
Further, although the SST type memory cell has been described here, the same applies to a virtual ground type memory cell using a three-layer polysilicon gate as disclosed in Japanese Patent No. 2694618 and a general NOR type memory cell. The present embodiment can be applied to. However, NOR type memory cells generally have an injection efficiency of 10 ^-5 To 10 ^-6 Therefore, it is necessary to increase the value of the write capacity. If possible, it is desirable to install a capacity of about 100 pF to 1 nF. These capacitances cannot be realized in a normal case by the diffusion layer capacitance or the parasitic capacitance of the bit line, but can be realized by the capacitance according to the MIM configuration described above, the MOS capacitance, or the external capacitance outside the chip.
<Example 6>
A sixth embodiment of the present invention will be described with reference to FIGS. FIG. 16 is a cross-sectional view of the memory cell in this embodiment. This memory cell includes a well 601 in a silicon substrate 600, a source diffusion layer region 606 and a drain diffusion layer region 607 in the well, a silicon oxide film 602, a silicon nitride film 603, and a silicon oxide film 604 formed on the well. Further, a polysilicon gate 605 serving as a first gate formed thereon is provided, and a polysilicon gate 609 serving as a second gate formed on the first gate and well via a silicon oxide film 608. Consists of The basic operation of the memory cell will be described with reference to FIG. FIG. 17 shows the memory cells arranged in the same array configuration as in the fifth embodiment, and shows the erase, write and read operations at the same time. As shown in FIG. 17A, in the write operation, about 8V is applied to the first gate of the selected cell, about 2V is applied to the second gate, about 6V is applied to the source, and about 0.5V is applied to the drain. Application is performed by injecting hot electrons generated at that time into the silicon nitride film which is a charge storage portion, trapping electrons and raising the threshold value. In the erase operation, as shown in FIG. 17B, about 12V is applied to the first gate of the selected cell and about 6V is applied to the second gate, and the electrons trapped in the silicon nitride film are applied to the first gate. By lowering the threshold value. Further, in the read operation, as shown in FIG. 17C, about 2V is applied to the drain, about 0V is applied to the source and the first gate, and about 2V is applied to the second gate. Make a decision. In the memory cell in the written state, the current is small because electrons are trapped in the trap in the silicon nitride film that is the charge storage portion, but in the memory cell in the erased state, electrons are not trapped in the charge storage portion. A larger current flows than the memory cell in the written state.
In the write operation in the present memory cell, the second gate portion is operated by applying a voltage about the threshold value of the MOS transistor formed by the second gate portion. The variation in voltage greatly affects the write characteristics of the memory cell. This is the same as the case of the memory cell with AG gate described in the first to fourth embodiments. The present embodiment is to reduce the variation at the time of writing in the above memory array configuration, and is characterized in that a capacitive element is provided between the write control circuit and each memory cell.
Hereinafter, this embodiment will be described in detail with reference to FIGS. The write selection cell is M00. First, when a write command and write data are input, the source lines SS0 and SS1 are raised to about 6V at time t0. Next, a voltage corresponding to the write data is output from the write control circuit 60 to the bit line at time t1. Assuming that the bit line DL0 is a selected bit line and the bit line DL1 is a non-selected bit line, 0.5V is applied to DL0 and 2V is applied to DL1. When the charging to the bit line is completed, the connection between the write control circuit 60 and the bit line is disconnected, and thereafter the selection control gate WL0 is raised to 2V at the timing of time t2. In the selected memory cell M00, 2V is applied to the control gate, 6V to the source, 0.5V to the drain, and 0V to the well, so that electrons are injected into the floating gate. On the other hand, in the memory cell M10 which is not selected for writing, 2V is applied to the control gate, 6V to the source, and 0V to the well. However, since 2V is applied to the drain, channel current does not flow to the memory cell and writing does not occur. Absent. At this time, a capacitor C0 is connected to DL0, and charges are accumulated in the capacitor C0 as a channel current flows through the memory cell M00. When charge is accumulated in C0 and the potential of DL0 rises to a certain voltage, the memory cell M00 is turned off and writing is stopped. Thereafter, the control gate WL0 is lowered at the timing of time t3, and the source lines SS0 and SS1 and the bit lines DL0 and DL1 are discharged to 0 V at the timing of time t4 to complete the electron injection operation.
Thereafter, a verification operation is performed to determine whether or not the threshold value has reached a desired value, and the above-described electron injection operation is subsequently performed for memory cells that have not reached the desired threshold value. Writing is terminated when all the memory cells to be written reach a desired threshold voltage.
As a result, it is possible to reduce variations in writing due to bias fluctuations applied to the second gate, and the number of times of writing verification can be reduced, so that the time required for writing can be shortened.
The above effect can also be realized in a configuration in which a write capacitor C is provided between a decoder circuit 61 that decodes a plurality of bit lines and a write control circuit 60 as shown in FIG. In the case of this configuration, the write capacitance value can be set large in order to be shared by a plurality of bit lines.
Further, the above-described capacitive element may be a parasitic capacitance of a bit line made of metal.
In the above description, the operation for raising the threshold value is described as writing, but the present invention can be applied to the case where the operation for raising the threshold value is erased.
In addition, when the memory cell is a so-called multi-level memory that can take two or more threshold states, the effect of the present system becomes more remarkable. In a multi-level memory, it is necessary to control a threshold corresponding to data with high accuracy. Therefore, if the writing variation is large, there is a problem that the number of threshold verifications increases and the writing speed decreases. Since this method can reduce writing variations, the number of threshold verifications can be suppressed, and the writing speed can be increased.
Further, the same effect can be obtained even if the charge storage node in this embodiment is a memory cell formed of a plurality of polysilicon spheres formed in a dot shape instead of the silicon nitride film. .
Furthermore, when the silicon nitride film or the dot-like polysilicon sphere is used as the charge storage unit, a polysilicon gate having the same function as the second gate is formed on both sides of the charge storage unit via a silicon oxide film. The same effect can be obtained even if the memory cell is provided. In this case, the charge storage unit can discretely hold charges at two locations close to the adjacent polysilicon gates, and multi-value storage can be realized by the difference in the charge storage location.
<Example 7>
A seventh embodiment of the present invention will be described with reference to FIGS. In the array configuration shown in FIG. 6, when a memory cell that is not selected for reading has a negative threshold value, the non-selected memory cell becomes conductive when the unselected word line voltage is 0V, and the threshold value of the selected memory cell is set. Cannot be read correctly. For this reason, the threshold value of the memory cell must always be 0 V or higher.
When performing the erase operation by lowering the threshold value of the memory cell, for example, a method of applying a negative high voltage, for example, −18 V to the word line to be erased to lower the threshold value of the memory cell in units of word lines. is there. At this time, as shown in FIG. 21, the erase bias application and the threshold verification operation are repeated until the thresholds of all the memory cells to be erased become VE1 or less. As a result, the threshold value of the memory cell after erasing becomes like distribution 1 shown in FIG. 21, and the threshold value of some memory cells may be 0 V or less. As described above, if there is a memory cell having a threshold value of 0 V or less, normal reading cannot be performed. Therefore, a post-erase operation for setting the threshold value to 0 V or more is necessary following erasure. This is done by setting the threshold values of all the memory cells to be VE2 or more.
In this post-erase operation, if the threshold value is excessively increased, the write state may not be discriminated. Therefore, the threshold distribution 2 after the post-erase is suppressed to VE3 or lower, which is a voltage lower than the read voltage VREAD. There is a need. If the variation in the post toilet characteristics is large, a memory cell with a threshold value exceeding VE3 may occur accidentally, or repeated bias application and threshold verification to narrow the threshold value between VE2 and VE3 The overall speed of erasure is reduced.
Therefore, when the erase operation is performed by lowering the threshold value and then performing the post-erase by raising the threshold value, the write variation can be reduced by using the method of the first to sixth embodiments. It is possible to suppress the occurrence of post-erase speeds. The post-erase operation will be described below based on the second embodiment with reference to the flowchart shown in FIG.
First, when an erase command is input, -18V is applied to the selected word line, and the threshold value of the memory cell is lowered. Thereafter, the threshold value is verified to determine whether or not the threshold value of all memory cells to be erased is equal to or lower than VE1, and if it is NG, the erase pulse is applied again to lower the threshold value of the memory cell. At this time, if the number of repetitions exceeds a predetermined value KMAX, a Fail flag is output to the outside as an erasure failure and the erasure is terminated. When all the threshold values become VE1 or less, the post-erase operation is performed next. First, the power supply and the bit line are connected, and the bit line is charged to 5V. Next, the power supply and the bit line are disconnected, and the bit line is brought into a floating state. Thereafter, when the selected word line is raised to 12V and the auxiliary gate is raised to 0.6V, electrons are injected into the floating gate. After a certain time, the voltage of the word line and auxiliary gate is lowered to stop the post-erase operation, and the threshold value is verified. If the threshold value of all the memory cells to be posted is not equal to or higher than VE2, the post-erase bias is applied again only to the memory cells equal to or lower than VE2. At this time, if the number of repetitions exceeds a predetermined value NMAX, a Fail flag is output to the outside as an erasure failure, and the post-erasing operation is terminated.
When the threshold voltage of all the memory cells to be posted becomes VE2 or more, it is verified whether the threshold value of the memory cell is VE3 or less. If there is a memory cell having a threshold value equal to or higher than VE3, a Fail flag is output to the outside as an erasure failure, and the post-erase operation is terminated. Therefore, if the threshold value after the post-erase is not less than VE2 and not more than VE3, the erase operation is normally terminated.
When outputting the Fail flag, it is desirable to set the thresholds of all memory cells to be erased to a predetermined voltage or higher in advance.
Although the description has been given based on the second embodiment, the same applies to the first embodiment and the third to sixth embodiments.
<Example 8>
The eighth embodiment of the present invention will be described with reference to FIGS. When writing by increasing the threshold value of the memory cell by the method shown in the first to seventh embodiments, the efficiency of electron injection into the floating gate increases as the writing to the memory cell progresses and the threshold value increases. descend. Therefore, if a bias is set so that a memory cell with early writing will not be written more than the desired threshold, the application of the repetitive pulse and the threshold until the memory cell with slow writing reaches the desired threshold. It becomes necessary to carry out verification, and the writing speed as a whole decreases.
Therefore, it is necessary to increase the bias applied to the memory cell for each write pulse and to keep the electron injection efficiency constant. FIG. 23 shows an example thereof, which is a method of increasing the voltage applied to the selected word line to VW1, VW2, VW3... As the number of write pulses increases. Since the electron injection efficiency into the floating gate increases as the word line voltage increases, writing is performed while keeping the injection efficiency constant by appropriately setting VW1, VW2, VW3,... According to the memory cell characteristics. It becomes possible.
As shown in FIG. 24, a method of increasing the voltage applied to the drain to VWD1, VWD2, VWD3... As the number of write pulses increases is also effective. Since the electron injection efficiency into the floating gate increases as the drain voltage increases, writing is performed while keeping the injection efficiency constant by appropriately setting VWD1, VWD2, VWD3,... According to the memory cell characteristics. Is possible.
<Example 9>
A ninth embodiment of the present invention will be described with reference to FIGS. 25 and 26. FIG. So far, in the first to eighth embodiments, the method of writing by flowing the accumulated charge to the memory cell and the method of writing by charging a certain capacity via the memory cell have been described. As shown in FIG. 25, the threshold value verification operation is repeated for one electron injection operation. In this method, when the variation value of the threshold value that occurs in one electron injection operation is insufficient, the number of repetitions increases, and as a result, the writing speed may be lowered. A feature of the present embodiment is that a decrease in writing speed is prevented by repeating threshold verification after performing an electron injection operation at least once. FIG. 26 shows a writing method in this embodiment.
This embodiment will be described with reference to FIG. After the electron injection operation is repeated N = f (k) times (where k is the number of threshold verifications and f (k) is a function of k), the threshold verification is performed by the memory cell to be written. Writing is performed by repeating until all the writing is completed or until the threshold verification count reaches the specified value Kmax times. N is a function of k and can be arbitrarily set according to the characteristics of the memory cell. For example, since it becomes difficult to inject electrons into the floating gate as the threshold value increases, increasing the number of repetitions of the electron injection operation as the number of threshold verifications increases increases the threshold increase. It is also possible to set to keep it as constant as possible.
<Example 10>
A ninth embodiment of the present invention will be described with reference to FIGS. In the first to ninth embodiments, the case where one memory cell has 1-bit information has been described. However, in this embodiment, a multilevel memory in which one memory cell has three or more threshold states is used. explain. FIG. 27 shows the correspondence between the threshold state and data for a 2-bit / cell multilevel memory. By setting the threshold value of the memory cell from the first state to the fourth state, it is possible to store two bits of “01”, “00”, “10”, and “11”, respectively. Therefore, the bit cost can be reduced. In FIG. 27, the fourth state corresponds to the erased state.
FIG. 27 and FIG. 28 are used to show an example of a general write method in a 2-bit / cell flash memory. The flash memory in FIG. 28 can assume the threshold state shown in FIG. First, when a write command is input from the outside, write data is taken into a data buffer inside the chip. Next, the bit line corresponding to the memory cell to be written in the first state is connected to the power source and raised to about 5V. Thereafter, when the selected word line is raised to about 12V and the selected AG is raised to about 0.6V, a part of hot electrons generated in the channel portion of the memory cell is injected into the floating gate, and the threshold of the memory cell is increased. The value rises. After the selected word line and the selected AG are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the first state is completed. The verification operation is performed by applying Vpref1 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the first state reach a predetermined threshold value.
When writing to the first state is completed, writing to the second state is started. First, the bit line corresponding to the memory cell to be written in the second state is connected to the power supply and raised to about 5V. Thereafter, when the selected word line is raised to about 12V and the selected AG is raised to about 0.6V, a part of hot electrons generated in the channel portion of the memory cell is injected into the floating gate, and the threshold of the memory cell is increased. The value rises. After the selected word line and the selected AG are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the second state is completed. The verification operation is performed by applying Vpref2 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the second state reach a predetermined threshold value.
When the writing to the second state is completed, writing to the third state is started. First, the bit line corresponding to the memory cell to be written in the third state is connected to the power source and raised to about 5V. Thereafter, when the selected word line is raised to about 12V and the selected AG is raised to about 0.6V, a part of hot electrons generated in the channel portion of the memory cell is injected into the floating gate, and the threshold of the memory cell is increased. The value rises. After the selected word line is lowered and the bit line is discharged, the memory cell is read to verify whether or not writing to the third state is completed. The verification operation is performed by applying Vpref3 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the third state reach a predetermined threshold value.
As described above, the multi-value memory is written by repeating the electron injection into the floating gate and the verification operation for each threshold state. However, as described above, if there is a variation in the write characteristics of the memory cells, the number of repetitions (hereinafter, the number of verifications) increases. For example, when there is a variation of about 1.3 digits in the write characteristics of the memory cell, the number of verifications is required about 12 times for each state, and reaches 36 times in three states. As described above, especially in a multi-level memory, if there is a variation in the write characteristics of the memory cells, the problem that the number of verify times increases and the write time increases becomes significant.
FIG. 29 shows a flowchart when the write method described in the second embodiment is applied to 2 bits / cell. First, when a write command is input from the outside, write data is taken into a data buffer inside the chip. Next, the bit line corresponding to the memory cell to be written in the first state is connected to the power source and raised to about 5V, the selected word line is raised to 12V, and then separated from the power source to be in a floating state. After that, by raising the selection AG to about 0.6 V, the charge accumulated in the parasitic capacitance of the bit line is discharged through the memory cell, and at this time, a part of the hot electrons generated in the channel portion is floating gate This increases the threshold value of the memory cell. After the selected AG and the selected word line are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the first state is completed. The verification operation is performed by applying Vpref1 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the first state reach a predetermined threshold value.
When writing in the first state is completed, writing in the second state is started. First, the bit line corresponding to the memory cell to be written in the second state is connected to the power source and raised to about 5V, the selected word line is raised to 12V, and then disconnected from the power source to enter the floating state. After that, by raising the selection AG to about 0.6 V, the charge accumulated in the parasitic capacitance of the bit line is discharged through the memory cell, and at this time, a part of the hot electrons generated in the channel portion is floating gate This increases the threshold value of the memory cell. After the selected AG and the selected word line are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the second state is completed. The verification operation is performed by applying Vpref2 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the second state reach a predetermined threshold value.
When writing in the second state is completed, writing in the third state is started. First, the bit line corresponding to the memory cell to be written in the third state is connected to the power source and raised to about 5V, the selected word line is raised to 12V, and then separated from the power source to be in a floating state. After that, by raising the selection AG to about 0.6 V, the charge accumulated in the parasitic capacitance of the bit line is discharged through the memory cell, and at this time, a part of the hot electrons generated in the channel portion is floating gate This increases the threshold value of the memory cell. After the selected AG and the selected word line are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the third state is completed. The verification operation is performed by applying Vpref3 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the third state reach a predetermined threshold value.
As described above, if writing is performed by flowing only charges stored in a certain capacity, that is, parasitic capacity of the bit line, to the memory cell, variation in write characteristics can be suppressed to about 0.3 digits. In this case, the number of verifications can be reduced to about 3 times for each state, and even if the three states are combined, the number of verifications can be reduced to 10 times or less. For this reason, it is possible to suppress a decrease in write speed, which is a problem in the multilevel flash memory.
In the above description, the memory cell applied voltages in the first to third state writing are the same, but as shown in FIG. 30, the selected word line voltage Vw1 in the first state writing is set to the selected word line in the second state writing. The voltage may be higher than the line voltage Vw2, and VW2 may be set higher than the selected word line voltage Vw3 at the time of writing the third state. In this case, since a higher voltage is applied to a memory cell whose threshold value needs to be greatly changed, efficient writing can be performed.
Further, as shown in FIG. 31, the selected bit line voltage Vd1 at the time of writing the first state is higher than the selected bit line voltage Vd2 at the time of writing the second state, and Vd2 is the selected bit line voltage at the time of writing the third state. It may be set higher than Vd3. In this case, since a higher voltage is applied to a memory cell whose threshold value needs to be greatly changed, efficient writing can be performed.
The above describes the case where the write method described in the second embodiment is applied to a non-volatile memory of 2 bits / cell, but it can be similarly applied to a multi-level memory of 3 bits / cell or more. . Needless to say, the methods described in the first embodiment and the third to sixth embodiments can be similarly applied to a multi-level memory having 2 bits / cell or more.
<Example 11>
FIG. 32 shows a multi-level writing method different from that in the ninth embodiment. In general, in the array configuration shown in FIG. 6, there is no upper limit other than reliability for the threshold value of the memory cell. Therefore, in the first state in FIG. 27, the distribution width can be set larger on the higher threshold side. For this reason, in writing to the first state, it is not necessary to control the threshold value with high accuracy, and by setting the width or voltage of the writing pulse to be large, writing can be completed with one pulse regardless of characteristic variations. It becomes possible.
In the write to the first state, the bit line corresponding to the memory cell to be written to the first state is connected to the power supply to about 5V, and then the selected word line is set to about 12V and the selected AG is about 0.6V. As a result, a part of hot electrons generated in the channel portion of the memory cell is injected into the floating gate. At this time, the write to the first state is completed with one write pulse by setting the high voltage pulse width applied to the selected word line to 10 μs or more or setting the selected word line voltage to a sufficiently high value of about 15V. It becomes possible to do.
When writing to the first state is completed, writing to the second state is started. The writing flow after the second state is the same as that of the second embodiment, and writing is performed by flowing only the charges accumulated in the bit line parasitic capacitance to the memory cell. First, the bit line corresponding to the memory cell to be written in the second state is connected to the power source and raised to about 5V, the selected word line is raised to 12V, and then disconnected from the power source to enter the floating state. After that, by raising the selection AG to about 0.6 V, the charge accumulated in the parasitic capacitance of the bit line is discharged through the memory cell, and at this time, a part of the hot electrons generated in the channel portion is floating gate This increases the threshold value of the memory cell. After the selected AG and the selected word line are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the second state is completed. The verification operation is performed by applying Vpref2 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the second state reach a predetermined threshold value.
When writing in the second state is completed, writing in the third state is started. First, the bit line corresponding to the memory cell to be written in the third state is connected to the power source and raised to about 5V, the selected word line is raised to 12V, and then separated from the power source to be in a floating state. After that, by raising the selection AG to about 0.6 V, the charge accumulated in the parasitic capacitance of the bit line is discharged through the memory cell, and at this time, a part of the hot electrons generated in the channel portion is floating gate This increases the threshold value of the memory cell. After the selected AG and the selected word line are lowered and the bit line is discharged, the memory cell is read to verify whether writing to the third state is completed. The verification operation is performed by applying Vpref3 to the selected word line and determining whether or not the memory cell is turned on. This write operation and verify operation are repeated until all the memory cells to be written to the third state reach a predetermined threshold value.
By forming the state corresponding to the highest threshold distribution with a single write pulse as in this embodiment, the number of verifications can be reduced to about seven.
The above describes the case where the write method described in the second embodiment is applied to a non-volatile memory of 2 bits / cell, but it can be similarly applied to a multi-level memory of 3 bits / cell or more. . Needless to say, the methods described in the first embodiment and the third to sixth embodiments can be similarly applied to a multi-level memory having 2 bits / cell or more.
<Example 12>
FIG. 33 shows a multi-level writing method different from those in the tenth and eleventh embodiments. In the figure, reference numeral 70 denotes a read / write control circuit, which activates SVD1 to turn on MOS transistor MVD1 when writing to the first state, and connects first power supply VD1 and bit line BL. is there. Similarly, when writing to the second state, SVD2 is activated to connect the second power supply VD2 and the bit line BL, and when writing to the third state, SVD3 is set to It has a function of activating and connecting the third power supply VD3 and the bit line BL. Here, the voltage of the first power supply is set higher than that of the second power supply, and the voltage of the second power supply is set higher than that of the third power supply. For example, the first power supply is 6V, the second power supply is 5V, and the third power supply is 4V.
FIG. 34 is a write flow when the circuit configuration of FIG. 33 is used. When a write command and write data are input, the bit line is connected to a power supply corresponding to the write data and charged to a desired potential. For example, the bit line of the memory cell selected to write to the first state is 6V, the bit line of the memory cell selected to write to the second state is 5V, and the write to the third state is selected. The bit lines being charged are each charged to 4V. Thereafter, the connection between each power source and the bit line is disconnected, and the bit line is brought into a floating state. When the selected word line is raised to about 12 V which is the write voltage and the selected AG is raised to about 0.6 V, the electric charge charged in each bit line is discharged by the memory cell, and hot electrons generated at this time are floated. Injected into the gate. At this time, the memory cell to be set to a higher threshold state has a larger amount of charge accumulated in the bit line and a larger amount of charge injected into the floating gate. After the selected word line is lowered and the bit line is discharged, the memory cell is read to verify whether writing to each state is completed. This write operation and verification operation are repeated until all memory cells reach a predetermined threshold voltage from the first state to the third state. By appropriately setting the first to third power supply voltage values, it is possible to complete the writing of the three states almost simultaneously.
In this method, since writing to three states and verification are performed simultaneously, the required number of verifications is about three.
<Example 13>
FIG. 35 shows a computer system in which the flash nonvolatile memory according to the first to twelfth embodiments of the present invention is incorporated. This system includes a host CPU, an input / output device, a RAM, and a memory card connected to each other via a system bus. It consists of and.
The memory card includes, for example, a flash nonvolatile memory with a large capacity storage of several tens of gigabytes as a replacement for a hard disk storage device, and enjoys the high-speed writing speed that is an advantage of the flash nonvolatile memory according to the embodiment of the present invention. The storage device has a sufficient industrial advantage.
The present invention is not limited to a memory card having a relatively small thickness. Even when the thickness is relatively large, an interface with the host bus system and a command of the host system are analyzed to analyze the flash nonvolatile memory. Needless to say, the present invention can be applied to any nonvolatile memory device including an intelligent controller capable of controlling a nonvolatile memory.
Data stored for a long time is stored in this non-volatile storage device, while data that is processed and frequently changed by the host CPU is stored in the RAM of the volatile memory.
The card has a system bus interface connected to the system bus, and enables a standard bus interface such as an ATA system bus. The controller connected to the system bus interface accepts commands and data from the host system connected to the system bus, the CPU, and the input / output device.
If the command is a read command, the controller accesses one or more necessary flash EEPROMs and transfers read data to the host system.
When the command is a write command, the controller accesses one or more necessary flash EEPROMs and stores write data from the host system therein. This storing operation includes a program operation and a verify operation for a necessary block, sector or memory cell of the flash memory.
If the command is an erase command, the controller accesses one or more necessary flash EEPROMs and erases the data stored therein. This erase operation includes an erase operation and a verify operation for a necessary block, sector or memory cell of the flash memory.
The flash non-volatile memory according to the embodiment of the present invention is not only a technique for causing a memory cell to have a binary threshold voltage in order to store one bit of digital data in one memory cell. Needless to say, the present invention is also applicable to a technique in which a memory cell has a multilevel threshold voltage of four or more in order to store multiple bits of data.
As mentioned above, the invention made by the present inventor has been specifically described based on the above-described embodiment. However, the present invention is not limited to the above-described embodiment, and can be changed without departing from the gist thereof. Of course.
For example, the present invention may be applied to a one-chip microcomputer (semiconductor device) including a memory cell array unit having a nonvolatile semiconductor memory element.
According to the present invention, the writing speed or erasing speed of the nonvolatile semiconductor memory device can be improved, and the power consumption of the nonvolatile semiconductor memory device can be reduced.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a flash memory for explaining the principle of the present invention.
FIG. 2 is a diagram for explaining a write operation of the flash memory.
FIG. 3 is a diagram for explaining the problem and the solution of the flash memory.
FIG. 4 is a circuit diagram for explaining the first embodiment of the present invention.
FIG. 5 is a timing diagram in the circuit diagram.
FIG. 6 shows a memory array configuration for explaining the first embodiment in detail.
FIG. 7 is a timing chart for explaining the write operation according to the first embodiment.
FIG. 8 is a timing chart for explaining the write operation according to the second embodiment.
FIG. 9 is a circuit diagram for explaining the first embodiment of the present invention.
FIG. 10 is a timing chart in the circuit diagram.
FIG. 11 is a timing chart for explaining the write operation according to the third embodiment.
FIG. 12 is a timing chart for explaining a write operation according to the fourth embodiment.
FIG. 13 is a circuit diagram for explaining the fifth embodiment of the present invention.
FIG. 14 is a timing chart in the circuit diagram.
FIG. 15 shows a circuit configuration different from that in FIG. 13 for realizing the fifth embodiment.
FIG. 16 is a cross-sectional view of a non-volatile memory for explaining Example 6 of the present invention.
FIG. 17 is a diagram for explaining operating voltage conditions of the flash memory.
FIG. 18 is a circuit diagram for explaining the sixth embodiment.
FIG. 19 is a timing chart in the circuit diagram.
FIG. 20 shows a circuit configuration different from that in FIG. 18 for realizing the sixth embodiment.
FIG. 21 is a threshold distribution diagram for explaining the seventh embodiment.
FIG. 22 is a flowchart of the writing method for explaining the seventh embodiment.
FIG. 23 is a timing chart for explaining the write operation according to the eighth embodiment.
FIG. 24 is a timing chart for explaining the write operation according to the eighth embodiment.
FIG. 25 is a flowchart illustrating the writing method according to the first to eighth embodiments.
FIG. 26 is a flowchart of the writing method for explaining the ninth embodiment of the present invention.
FIG. 27 is a threshold distribution diagram for explaining Example 10 of the present invention.
FIG. 28 is a flowchart for explaining a conventional multi-level flash memory writing method.
FIG. 29 is a flowchart of the write method for explaining the tenth embodiment of the present invention.
FIG. 30 is a timing chart for explaining the tenth embodiment of the present invention.
FIG. 31 is a timing chart for explaining the tenth embodiment of the present invention.
FIG. 32 is a flowchart of the write method for explaining the eleventh embodiment of the present invention.
FIG. 33 is a circuit diagram for explaining Example 12 of the present invention.
FIG. 34 is a flowchart of the write method for explaining the twelfth embodiment of the present invention.
FIG. 35 is a system configuration diagram for explaining Example 13 of the present invention.

Claims (7)

The charge which has been accumulated in the capacitor discharges through the memory cell, by injecting hot electrons generated at that time in the charge storage portion of the memory cell, it has row write or erase, and charges in the charge storage section A nonvolatile semiconductor memory device characterized in that an internal power supply circuit for generating a voltage to be applied to a bit line is made inactive when implanting . The nonvolatile semiconductor memory device according to claim 1 , wherein the charge storage unit is a floating gate. The nonvolatile semiconductor memory device according to claim 1 , wherein the charge storage unit is a silicon nitride film. The nonvolatile semiconductor memory device according to claim 1 , wherein the capacitor is a parasitic capacitor of a bit line. 5. The nonvolatile semiconductor memory device according to claim 4 , wherein a part of the parasitic capacitance is composed of a pn junction capacitance of a diffusion layer of the memory cell. 2. The nonvolatile semiconductor memory device according to claim 1 , wherein a threshold value verifying operation of the memory cell is performed after repeating the writing or erasing operation a plurality of times. 7. The nonvolatile semiconductor memory device according to claim 6 , wherein the number of repetitions of the write or erase operation is increased for each threshold verification operation.

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