WO2004068500A1 - Nonvolatile semiconductor memory device - Google Patents

Abstract

A nonvolatile semiconductor memory device has control means which arranges that a pulse voltage to be applied, before a first verifying operation, to memory cells during write operation is greater than a pulse voltage to be applied before a second verifying operation and that any pulse voltage to be applied after the first verifying operation is increased by a constant pulse height increment each time a threshold value verifying operation is performed. In this way, a narrow-band of threshold voltage can be obtained without any increase of write time, and the write speed of the whole memory can be raised.

Description

Nonvolatile semiconductor memory device

TECHNICAL FIELD The present invention relates to an electrically rewritable nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device capable of storing multiple data.

 Akita

2. Description of the Related Art In recent years, flash memory has excellent portability and impact resistance, and can be erased electrically all at once. In recent years, flash memory has rapidly become a file for small portable information devices such as portable personal computers and digital still cameras. Demand is growing. To expand the market, it is essential to reduce the bit cost by reducing the memory cell area, and various memory cell methods have been proposed to achieve this. One of them is a virtual ground type memory cell using a three-layer polysilicon gate as shown in Japanese Patent Application No. 11-200242. As shown in FIG. 1, the memory cell has a first well composed of a well WEL in a silicon substrate SUB, a source in a well, a drain diffusion layer region DR, and a polysilicon film formed on the well. It consists of three gates: a floating gate FG serving as a gate, a control gate VV serving as a second gate, and an auxiliary gate AG serving as a third gate. AG and FG are disposed through an insulating film TOX as that formed for example Si0 ₂ on WEL. Of these, the third gate AG is embedded in the gap between the floating gate FG that is perpendicular to the word line and the channel, and Between has a separate structure in example Si0 ₂ of such an insulating film SWA. The floating gate FG and the SWF, which is also made of a polysilicon film, are separated from the lead line WL by an insulating film IPO, and the third gate AG is separated from the word line WL by an insulating film CA and IPO. Have been. The source / drain diffusion layer DR is arranged perpendicular to the word line WL and exists as a local source line and a local data line connecting the source / drain of the memory cell in the column direction (X direction). Consists contactors Torres-type array having no contactor Bokuana for each memory cell, it is possible to improve the formation density of the memory cells, the memory cell area 4 F ^2: can be reduced to (F minimum feature size).

The above-mentioned memory cell enables not only miniaturization but also high-speed writing. Figure 2 shows the voltage application conditions during memory cell writing. A positive voltage of, for example, about 5 V is applied to the diffusion layer Dn serving as the drain of the selected memory cell M, and a positive voltage of, for example, about 13 V is applied to the lead line WLn of the selected memory cell M. To the third gates AGe of the memory cells M and M + ² , a voltage approximately equal to the threshold of the MOS transistor constituted by the third gate, for example, approximately IV is applied. The diffusion layer D n−1, the gate, and the unselected word line WL n + 1 that are the sources of the selected memory cell M are held at 0V. By the above operation, a large horizontal electric field and a vertical electric field are formed in the channel below the boundary between the floating gate and the third gate. This increases the generation and injection efficiency of hot electrons, and enables high-speed writing despite the small channel current. In conventional hot Elec tron injection method, with respect to the injection efficiency in the range of 10- ⁶ 10_ ^5, in this method, it is possible to obtain a high injection efficiency of approximately 10_ ^3. Therefore, use an internal power supply with a current supply capacity of about 1 mA. However, it is possible to write more than kilobytes of memory cells in parallel.

 In flash memory, as a method of achieving cost reduction, as shown in 1999 IBaa International Solid State Circuits and onference Digest of Technical Papers ρ. There is known a multi-valued technology in which a multi-bit data is held by providing a value voltage level.

When the memory cell shown in Fig. 1 is applied to a multi-valued flash memory, as a method for speeding up writing, for example, the Constant Charge Injection Programming method shown in DIGEST OF TECHNICAL PAPERS 2002 SYMPOSIUM ON VLSI CIRCUITS p.302 to 303 (Hereinafter referred to as the CCIP method). In the CCIP method, as shown in Fig. 3, electric charge is stored in a fixed capacitance C provided on the drain side of the memory cell MEM, and only the electric charge stored in that capacitance is passed to the memory cell to perform writing. Do. Figure 4 shows the write operation method of the CCIP method. First, the internal power supply PROG that supplies the channel current at the timing of t0 is set to 5 V, SWS and SED are started at the timing of t1, and STS, which is the switching MOS on the source side and the drain side of the memory cell MEM, Turn STD ON. Next, a write voltage of 13 V is applied to the read line WL of the selected memory cell at the timing of t2. After that, when the memory cell MEM is charged to the drain side node ND power; 5 V, the SWD falls at the timing of t3, the STD which is the drain side switch MOS is set to the FFFF state, and the internal power supply PROG And disconnect. By applying about IV to the AG of the selected memory cell at the timing of t4, the charge accumulated at the node ND starts flowing to the source side via the memory cell. At this time, a hot electron generated in the channel region of the memory cell is injected into the floating gate to write data. Only happens. The potential of the node ND on the drain side decreases as the channel current flows, but writing occurs while a high horizontal electric field sufficient to generate hot electrons is generated in the channel portion. If the CCIP method is not used, the amount of current per cell must be reduced to several hundred nA or less in order to write cells in kilobytes in parallel. It was necessary to set the voltage to be applied to, for example, IV or less, and operate in the subthreshold region. For this reason, the write characteristics of the memory cell greatly vary due to dimensional variations in the AG section, etc., but according to the CCIP method, the variations in the write characteristics can be greatly improved. On the other hand, in a multilevel flash memory, a very narrow distribution width is required for a threshold voltage corresponding to each data. When writing, it is necessary to keep the threshold voltage of each memory cell within this narrow threshold distribution. In general, the value is narrowed by applying a write pulse and reading (verify) for verifying whether the data has been written. In other words, in a multi-level flash memory, if the variation in write characteristics between memory cells is large, the number of times of verifying is required, and thus there is a problem that the writing of the entire storage device is delayed. According to the CCIP method, the variation in writing between memory cells can be significantly reduced, so that the number of times of verification can be reduced, and the writing speed of the multi-level flash memory can be increased.

As described above, writing to a large-capacity flash memory is performed simultaneously on a plurality of memory cells connected to one read line. Since the write speed differs depending on the memory cell, the write pulse is applied repeatedly while verifying the threshold voltage Vth. Memory cells whose value Vth has risen up to a predetermined write level Only when all the memory cells to be written are written, that is, when the threshold voltage Vth of all the memory cells to be written reaches a predetermined level, the writing is completed. . .

 In such a writing method, a writing speed is determined by a memory cell having a low writing speed. In order to write the memory cell with the slowest write speed faster, it is conceivable to increase the write pulse voltage and increase the write pulse width. However, in this case, a memory cell with a fast write time may be written at the first pulse beyond the allowable threshold voltage Vth, resulting in erroneous write. In particular, in a multi-level flash memory in which multiple thresholds and value levels are provided in one memory cell to hold multi-bit data, the allowable threshold voltage Vth width for each level is, for example, about 0.4 V. Is very small, a write error occurs when a memory cell in which writing is fast exceeds a predetermined threshold voltage Vth. Therefore, it is necessary to optimize the pulse application method so that both the fast-writing memory cell and the slow-writing memory cell can write fastest within the allowable threshold voltage range.

As one means for making this possible, for example, an ISPP dncremental step pulse programming method as disclosed in JP-A-7-169284 and JP-A-134879 has been proposed. FIG. 5 shows a write pulse in the 1SPP method, and shows a pulse voltage applied to the lead line. The low voltage pulse Vvr in the figure is a pulse applied in the verify operation, and a high voltage, for example, a Vpp pulse is a pulse applied in the write operation. This write operation and verify operation are one cycle. The cycle is repeated. The ISPP method is characterized in that the pulse voltage is increased by Vpp for each application cycle. In this way, a memory cell with a fast write operation can be prevented from being overwritten because the write operation is completed while the initial write pulse voltage is low and no subsequent high pulse voltage is applied. Also, for memory cells with slow writing, the writing pulse voltage rises with each pulse application, so writing is faster than continuing to apply pulses of the same voltage. JP-A-134879 shows an example in which the ISPP method is applied to a 2-bit / cell multi-level flash memory. Figure 6 shows the relationship between data and threshold distribution in a 2-bit / cell multi-level flash memory. By making it possible to set the threshold distribution in four states, one memory cell can hold 2-bit data. Figure 7 shows the application of the ISPP method to this 2-bit / cell multi-level flash memory. Ρί, writing to the “1” level, Ρί2, writing to the “2” level, and Ρ3, writing to the “3” level. First, in P1, writing is performed by increasing the pulse voltage by ΔVppl every write cycle from the initial write pulse Vppl, and verification is performed with the verify voltage Vvrl corresponding to the “1” level. This cycle is repeated, and when all the memory cells to be written to the "1" level have been completely written, the operation shifts to the "2" level write P2. In P2, writing is performed by increasing the pulse voltage by A Vpp2 for each write cycle from the initial write pulse Vpp2, and verification is performed with the verify eye voltage Vvr2 corresponding to the "2" level. This cycle is repeated, and when all the memory cells to be written to the "2" level have been completely written, the operation shifts to the "3" level write P3. Similarly, in P3, from the initial write pulse Vpp3, the write Writing is performed by increasing the pulse voltage by Δ ν _Ρ ρ3 for each write cycle, and verification is performed with the verify voltage Vvr3 corresponding to the “3” level. This cycle is repeated, and when all the memory cells to be written to the "2" level have been completely written, all multi-level level writing has been completed.

 In the above ISPP method, there is a limit in increasing the writing speed. In other words, even for the fastest bit for writing, the threshold voltage does not rise sufficiently with the initial pulse with a low voltage, and multiple pulses are required before the writing is completed. Japanese Patent Application Laid-Open No. 11-39887 discloses an improved technique for increasing the writing speed of the ISPP method. Here, as shown in FIG. 8, the first pulse width in writing is set longer than the second pulse width, and the first pulse voltage is set shorter than the second pulse voltage. Therefore, the fastest bit to be written will be completed with one or several pulses.

However, in the above technique, there is a limit particularly in increasing the speed of multi-value writing. That is, in a multi-level flash memory, it is necessary to form a plurality of threshold states, so that the threshold setting range is wider than that of a normal 1-bit / cell flash memory. For this reason, a wider pulse must be applied to complete the write with the fastest bit in one pulse. Since the amount of change in the threshold is almost proportional to the logarithm of the pulse application time, the pulse width to be applied first becomes exponentially large, and the writing speed is greatly reduced. Furthermore, when writing to a multi-level flash memory by the CCIP method described above, the writing speed of the entire storage device cannot be increased with the conventional writing pulse application method. Non-volatile semiconductor storage device represented by flash memory Since the data capacity of data storage devices such as moving pictures is increasing, the speed of writing and erasing data is required to be further improved. SUMMARY OF THE INVENTION Under such a background, an object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening a writing time of the entire memory device and realizing an improvement in a writing speed by improving a writing method. Disclosure of the invention

 In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention provides a threshold voltage by applying a write or erase signal composed of a plurality of pulses to transfer charges to and from a charge storage node. A non-volatile semiconductor memory device having a storage element for storing information in accordance with the threshold voltage, wherein after applying each pulse, a threshold voltage of the storage element is detected, and the threshold voltage is detected. Has a verifying means for verifying whether or not has reached a predetermined level. When the verifying means determines that the threshold voltage of the storage element has reached the predetermined level, the pulse When it is determined that the voltage has not reached the above-described predetermined level, control means for performing the next pulse application is provided, and the voltage is applied before the first threshold verification in the writing or erasing. When the voltage of the first pulse is the first pulse voltage, the second threshold, and the second / pulse voltage applied before value verification is the second pulse voltage, the first pulse voltage is There is control means for setting the voltage higher than the second pulse voltage.

In the present invention, preferably, the pulses applied after the second pulse have the same pulse width, and the pulse voltage increases by a constant pulse height increment every time the threshold value is verified. Set as follows. Further, in the present invention, the control means sets the pulse width of the panel applied after the second pulse to be equal to or less than the pulse width of the first pulse, and the pulse voltage is When the voltage reaches a predetermined voltage, the pulse voltage applied thereafter is set to the predetermined voltage, and the pulse width can be set so as to gradually increase. According to the present invention, the write pulse can be optimized, the threshold band can be narrowed without increasing the write time, and the write speed of the entire memory device can be improved.

 In the present invention, in particular, a first conductivity type well formed on a main surface of a semiconductor substrate, a second conductivity type semiconductor region formed in the well and extending in a first direction, A first gate formed on the substrate via a first insulating film, a second gate formed on the first gate via a second insulating film, and a third gate; An end face of the third gate is an end face facing between the adjacent first gates, and faces an end face of the first gate existing in parallel with the first direction via a third insulating film. It is preferable that the formed electrically rewritable memory cells be applied to a memory cell array arranged in a matrix. Since the above-mentioned memory cell can perform high-speed writing by hot electron injection with high injection efficiency, the writing speed of the entire memory device can be further increased with the optimization of the writing pulse.

Further, according to the present invention, there is provided a memory cell array in which electrically rewritable memory cells each formed by stacking a charge storage node and a control gate on a semiconductor layer are arranged in a matrix, and at least a memory cell for performing writing or erasing. And the same number of capacitor elements as described above, and the charge stored in the capacitor element is stored in the memory by applying a pulse. By discharging through a cell and injecting a hot electron generated at that time into a floating gate, a threshold value after a pulse is applied to a flash memory having a means for writing or erasing is detected. Verification means for verifying whether the threshold voltage has reached a predetermined level, and when the verification means determines that the threshold voltage has reached the predetermined level, Control means for terminating the application of the pulse, applying the next pulse when the threshold value and the value voltage have not reached the predetermined level, and before the first threshold value verification in the writing or erasing When the voltage of the pulse applied to the first pulse voltage is the first pulse voltage and the voltage of the pulse applied before the second threshold value verification is the second pulse voltage, the first pulse voltage is the second pulse voltage. Greater than the voltage, The width of the pulse applied after the first threshold verification is the same, and the voltage of the pulse applied after the first threshold verification is changed every time the threshold is verified. It has a control means for setting so as to increase by a constant pulse height increment.

Further, the control means is characterized in that the pulse applied before the first threshold and value verification is set to be two or more times, and that the pulse is applied after the first threshold verification. The pulse is set so as to be applied at least twice between the threshold verifications. As a result, especially in a multi-valued damage operation, it is possible to suppress the variation in the write characteristics of the memory cell and to optimize the damage pulse, and to improve the write speed of the entire memory device. BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a diagram showing a structure of a memory cell for realizing high-speed writing and miniaturization. FIG. 2 is a diagram showing an array configuration of the memory cells. FIG. 3 is a circuit diagram showing the operation of the CCIP method. FIG. 4 is a waveform chart showing the operation of the CCIP method. FIG. 5 is a waveform diagram showing a write pulse waveform according to the ISPP method. FIG. 6 is a diagram showing a threshold distribution of 2 bits / cell. FIG. 7 is a waveform diagram showing a write pulse waveform when the ISEP method is applied to 2 bits / cell. FIG. 8 is a waveform diagram showing a write pulse waveform in a conventional write method. FIG. 9 is a waveform diagram showing a write pulse waveform according to the first embodiment. FIG. 10 is a diagram illustrating a configuration example of a write pulse generation circuit according to the first embodiment of the present invention. FIG. 11 shows a write pulse waveform according to the second embodiment of the present invention. FIG. 12 shows a write pulse waveform according to the third embodiment of the present invention. FIG. 13 shows a write pulse waveform according to the fourth embodiment of the present invention. FIG. 14 shows a write pulse waveform according to the fifth embodiment of the present invention. FIG. 15 shows a write pulse waveform according to the sixth embodiment of the present invention. FIG. 16 shows a write pulse waveform according to the sixth embodiment of the present invention. FIG. 17 shows a write pulse waveform according to the sixth embodiment of the present invention. FIG. 18 shows a write pulse waveform according to the sixth embodiment of the present invention. FIG. 19 shows a write pulse waveform according to the seventh embodiment of the present invention. FIG. 20 shows a write pulse waveform according to the eighth embodiment of the present invention. FIG. 21 shows a write pulse waveform according to the ninth embodiment of the present invention. FIG. 22 shows a write pulse waveform according to the ninth embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION <First embodiment>

 FIG. 9 is a diagram showing one embodiment of the nonvolatile semiconductor memory device according to the present invention, and is a waveform diagram showing a write pulse in the present embodiment. In the present embodiment, the pulse voltage Vppi applied at the beginning of writing is set higher than the pulse voltage Vpp applied for the second time, compared to the conventional ISPP method. It is desirable that the pulse voltage Vppi at the beginning of writing be set so that the fastest bit to be written is written up to the target threshold voltage by this pulse. The second and subsequent pulses are written by increasing the pulse voltage by ΔνΡΡ according to the ISPP method.

FIG. 10 shows a configuration example of a write pulse generation circuit according to the present embodiment. The write pulse generation circuit consists of the internal power supply circuit CP and the code decoder DW. The input signal SEL to the internal power supply circuit CP is a signal for selecting a generated voltage level, and is controlled by the CPU in the nonvolatile semiconductor memory device. The signal STP is a signal for selecting a pulse width, and is an output from the CPU in the non-volatile semiconductor memory device like the SEL. The STP and the address selection signal ADH enable the code decoder DW to output a bias with a specified pulse width and pulse voltage to the selected code line. In the conventional example shown in Fig. 8, for example, the initial pulse width was set to 50 µ3, the pulse voltage was set to 14.5V, the pulse width for the second and subsequent pulses was increased to 2 s, and the pulse voltage was increased stepwise by 0.5V. However, according to this method, the initial pulse width is set to 2 μβ, which is the same as the second and subsequent pulse widths, and the pulse voltage is set to about 16 V, which is higher than the second pulse voltage of 15 V. This reduces the initial pulse width, which previously required 50 S to 2 S, before the fastest bit is written. This will make it possible to significantly speed up writing.

 <Second embodiment>

 FIG. 11 is a waveform diagram illustrating a write pulse according to another embodiment of the present invention. There is an upper limit to the voltage that can be generated by the internal power supply circuit CP described above, the withstand voltage of the transistor in the code decoder, and the pulse voltage that can ensure the reliability of the memory cell. Therefore, especially when the threshold value needs to be shifted greatly, such as in a multi-valued flash memory, the pulse width of the initial pulse is the same as the second and subsequent pulses even if the maximum available pulse voltage is used. There is a possibility that the pulse width cannot be set. Therefore, in this embodiment, as shown in FIG. 11, the maximum pulse voltage Vppmax that can be used is used for the initial pulse, and the pulse width is set to Tppi larger than the second and subsequent pulse widths Tpp. As a result, even when the threshold voltage change required at the time of programming is large, as in a multi-valued flash memory, the fastest bit at which programming can be performed is up to the specified threshold voltage by the initial pulse. Written. Furthermore, since the maximum usable voltage is used for the initial pulse, there is an effect that the writing can be completed at the fastest speed and the bit can be completed in the shortest time.

 Third Embodiment>

FIG. 12 is a waveform diagram showing a write pulse according to another embodiment of the present invention. If the threshold voltage needs to be shifted greatly, as in a multilevel flash memory, writing using the maximum available pulse voltage may not be completed by the ISPP method. Therefore, as shown in Fig. 12, when the pulse voltage reaches the maximum usable voltage Vppmax when writing is performed by the ISPP method, the pulse width of the subsequent pulses gradually increases while keeping the pulse voltage at Vppmax. Let it. This At this time, it is desirable to set the width of each pulse so that the threshold voltage shift amount that changes for each pulse is constant. In FIG. 12, the initial pulse voltage may be Vppmax, and the pulse width may be Tppi larger than the pulse width Tpp used in ISFP. According to the present embodiment, even when writing is not completed by ISPP alone, there is an effect that writing can be completed quickly by gradually increasing the pulse width.

 4th embodiment>

 FIG. 13 shows an example in which the write pulse shown in FIG. 9 is applied to the 2-bit / cell multi-level flash memory shown in FIG. The write cycles Pl, P2, and P3 represent writing to the "1" level, "2" level, and "3 level" in FIG. 6, respectively. In each write cycle, as shown in Figure 9, the initial pulse and subsequent

Writing is performed by ISPP. First, write cycle; In P1, initial pulse

With Vppli, the fastest write bit is set to be complete, and subsequent ISPPs cause the write to proceed sequentially. The initial pulse voltage Vpp li is higher than the initial pulse voltage Vpp 1 of the ISPP. The step voltage ΔVp 1 of the ISPP is set to be equal to or less than the threshold distribution width allowed for the “1” level. After writing to the "1" level is completed, the cycle P2 for entering the "2" level starts. In the write cycle P2, the initial pulse Vpp2 i is set so that the write to the fastest bit power “2,” level is completed, and the write is advanced sequentially by the subsequent ISPP. Here, the initial pulse voltage Vpp2 i is larger than the first pulse voltage Vpp2 of the ISPP, and the step voltage AVpp2 of the ISPP is set equal to or less than the threshold distribution width allowed for the "2" level Is done. After the writing to the "2" level is completed, the write cycle P3 for the "3" level starts. In the write cycle P3, the initial pulse Vpp3 i is set so that the write to the fastest bit card ^ 3 "level is completed, and the subsequent ISPP sequentially proceeds with the write. Here, the initial pulse voltage Vpp3 i The ISPP first pulse voltage Vpp3 is larger than the ISPP step voltage AVpp3 is set to be equal to or less than the threshold distribution width allowed for the "3" level. When the writing of the threshold value is completed, it means that the multi-level level writing has been completed. Here, for example, when the amount of shift of the threshold voltage required at the time of writing is small, such as the T level, Does not have to apply the initial pulse.If the amount of shift of the threshold voltage required at the time of writing is large, such as "3", the initial pulse voltage is Vppmax, The pulse width by setting larger than the pulse width Tpp used in ISPP, it is possible to write faster storage instrumentation 置全 body.

 <Fifth embodiment>

FIG. 14 is an example different from FIG. 13 in which the write pulse shown in FIG. 9 is applied to a 2-bit / cell multilevel flash memory. In the threshold and value configuration shown in Fig. 6, the threshold located at the center and the distribution width required for the value distributions "1" level and "2" level are small, but the uppermost threshold, The distribution width of the value distribution "3" level may be large. Therefore, in writing at the "3" level, the ISPP to narrow the threshold distribution is not performed, and a high-voltage and wide pulse is applied to make the "3" level as fast as possible. Finish writing. In FIG. 14, the no- and low-voltages Vpp3 i may be Vppmax. The write pulse application method shown in FIG. 14 has the following effects in addition to increasing the write speed. In writing to the "3" level, a wide pulse with a high voltage is applied, so if writing to the "3" level is performed after writing to the "Γ" and "2" levels is completed, the " The 1 "and" 2 "levels are disturbed and the threshold distribution may be broadened, making it indistinguishable from the other levels. Prior to programming, "3" level programming is performed, which has the effect of avoiding this problem.

 <Sixth embodiment>

FIG. 15 is a diagram showing one embodiment of the nonvolatile semiconductor memory device according to the present invention, and is a waveform diagram showing a write pulse in the present embodiment. The present embodiment is based on the premise of a writing method in which electric charges accumulated in a certain capacitance are discharged through a memory cell, and a hot electron generated at that time is injected into a floating gate. Hereinafter, an application example of the present invention will be described for the CCIP method illustrated in FIGS. 3 and 4 in the flash memory having the third gate illustrated in FIGS. 1 and 2. By applying the ISPP method to the CCIP method, it is possible to increase the writing speed. Furthermore, in the CCIP system, the same effect can be obtained by setting the initial pulse voltage higher or lower than the second pulse voltage, as in FIG. If the threshold voltage needs to be greatly shifted, as in the case of multilevel flash memory, the pulse width of the initial pulse can be reduced even if the maximum available pulse voltage is used. There is a possibility that the same pulse width cannot be set for the second and subsequent times. Normal hot electron injection method, source side injection writing, or Fowler-Nordheim tunneling In the case of writing with a single current, as shown in Fig. 11, the maximum pulse voltage Vppmax is used for the initial pulse, and the pulse width is set to Tppi larger than the second and subsequent pulse widths Tpp to increase the speed. Can be realized. However, when writing is performed using charges accumulated in a fixed capacity as in the CCIP method, the effect of speeding up cannot be obtained even if the pulse width is increased. This is because the amount of charge injected into the floating gate is limited by the amount of charge stored in a certain capacitance. Therefore, as shown in Fig. 15, in the initial pulse area Pinit:-accumulation of electric charge in the constant capacity and discharge by the memory cell are performed several times. During this period, the verify operation is not performed to verify whether or not the writing has been completed, and the number of times Ni and the pulse voltage Vppi are set so that the fastest bit of writing is completed in this initial pulse region. It is desirable. The pulse setting shown in FIG. 15 has the effect that the writing speed can be increased in the CCIP method. As a specific example of FIG. 15, FIG. 16 shows a write pulse when applied to the memory cells shown in FIGS. The upper part of the figure shows the voltage pulse applied to the control gate of the memory cell, that is, the lead line, and the lower part shows the voltage pulse to AG, which is the third gate of the memory cell. As described above, writing to a memory cell is performed by applying a high voltage of, for example, 13 V to a lead line, and applying a low voltage such as a threshold voltage to the AG. Therefore, the voltage pulse to the word line takes longer time to rise and fall than the voltage pulse to AG. Therefore, in the initial pulse region in FIG. 15, it is better to apply the voltage pulse to the AG Ni times and set the lead line voltage to Vppi—constant than applying the voltage pulse to the word line Ni times. Can write faster There is an advantage that will be.

 In addition, as described above, in the CCIP method, writing is performed using charges accumulated in a fixed capacitance, and thus the amount of charge injected into the floating gate is limited by the amount of charge accumulated in the fixed capacitance. Therefore, when the accumulated charge is small or the injection efficiency is low, the threshold value may not be sufficiently changed by one injection operation. In such a case, as shown in FIG. 17, in the Pispp region, it is possible to secure the shift amount of the threshold voltage by applying a plurality of pulses, for example, Ns times in one cycle. . Further, FIG. 18 shows a write pulse when this method is applied to the memory cells shown in FIGS. The upper part of the figure shows the voltage pulse applied to the control gate of the memory cell, that is, the lead line, and the lower part shows the voltage pulse to the third gate of the memory cell, AG. As described above, writing to a memory cell is performed by applying a high voltage of, for example, 13 V to a word line, and applying a voltage as low as a threshold voltage to AG. Therefore, the voltage pulse to the word line takes more time to rise and fall than the voltage pulse of AG. For this reason, in the Pispp region in FIG. 17, it is better to apply a voltage pulse to the AG Ns times and apply a constant voltage to the lead wire during this period than to apply a voltage pulse to the lead wire Ns times between belly eyes. There is an advantage that writing can be performed faster.

 <Seventh embodiment>

FIG. 19 is a diagram showing one embodiment of the nonvolatile semiconductor memory device according to the present invention, and is a waveform diagram showing a write pulse in the present embodiment. Multi-value flash If the threshold voltage needs to be shifted significantly, as in the case of a memory, even if the maximum available pulse voltage is used, writing by the ISPP method may not be completed. If a normal hot electron injection method, source side injection writing, or writing by Fowler-Nordheim tunnel current is used, the maximum pulse voltage that can be used when writing is performed by the ISPP method is shown in Fig. 12. When the voltage reaches Vppmax, the speed of subsequent pulses can be increased by gradually increasing the pulse width while keeping the pulse voltage at Vppmax. However, when writing is performed using charges accumulated in a fixed capacity as in the CCIP method, the effect of speeding up cannot be obtained even if the pulse width is increased. This is because the amount of charge injected into the floating gate is limited by the amount of charge stored in a given capacitance. Therefore, as shown in Fig. 19, in the ISPP region Pispp, after the pulse voltage reaches Vppmax, the writing speed is increased by gradually increasing the number of pulses. Here, the number of pulses is the number of times that charge is accumulated in a fixed capacity and discharge is performed by a memory cell repeatedly. During this time, the verify operation for verifying whether writing is completed is not performed. It is desirable that the number of pulses be set so that the shift amount of the threshold voltage is constant. For example, in FIG. 19, the number of times is set so that the threshold voltage shift amount by Nbl pulse application and the threshold shift amount by Nb2 pulse application performed subsequently are the same. According to the present embodiment, even when writing is not completed by ISPP alone, there is an effect that writing can be completed quickly by gradually increasing the number of pulses. Further, when applied to the memory cells shown in FIGS. 1 and 2, as in the sixth embodiment, the word voltage is kept constant and the AG voltage is kept constant. It is desirable to adopt a method in which pressure is applied a plurality of times.

 <Eighth Embodiment> 'FIG. 20 shows an example in which the write pulse shown in FIG. 15 is applied to the 2-bit / cell multi-line flash memory shown in FIG. The write cycles Pl, P2, and P3 represent writing to the "1" level, "2" level, and "3 level" in FIG. 6, respectively. In each write cycle, as shown in Fig. 20, writing is performed using the initial pulse area and the subsequent ISEP area.

 First, in the write cycle P1, Nli pulses are applied at the pulse voltage Vppli in the initial pulse region. As a result, the setting is made such that the fastest bit power of the write ^ 1 "level write is completed. The initial pulse voltage Vppl i is

It is larger than the first pulse voltage Vpp 1 in the ISPP region. The step voltage Δνρρΐ in the ISPP region is set equal to or less than the threshold distribution width allowed for the “1” level. In the ISPP area, pulse application and verification are repeated, and if all bits to be written to the "1" level are determined to have been written by verification, the write cycle P1 ends and the write cycle P2 starts. You.

In the write cycle P2, N2 i pulses are applied at the pulse voltage Vpp2 i in the initial pulse region. As a result, the fastest bit power for writing; "2" level writing is set to be completed. The initial pulse voltage Vpp2 i is larger than the first pulse voltage Vpp2 in the ISPP area. The step voltage ΔVpp2 in the ISPP region is set to be equal to or less than the threshold and the value distribution width allowed for the “2” level. Repeat pulse application and verify in ISPP area However, if all bits to be written to the “2” level are determined to be completely written by the verification, the write cycle P2 ends and the write cycle P3 starts.

 In the write cycle P3, N3 i pulses are applied at the pulse voltage Vpp3 i in the initial pulse region. As a result, the fastest bit power of the writing is set so that the writing is completed at the '2' level.The initial pulse voltage Vpp3i is higher than the first pulse voltage Vpp3 in the ISPP region. Vpp3 is set to be equal to or less than the threshold and value distribution width allowed for level “3.” In the ISPP area, pulse application and verification should be repeated and written to level “3” If all the bits are determined to have been written by the verify operation, the write cycle P3 ends, and writing of all multi-valued levels ends. The initial pulse area may not be necessary if the shift amount of the threshold voltage required for data writing is small. When the amount of shift of the threshold voltage to be performed is large, setting the pulse voltage in the initial pulse region to Vppmax has the effect of increasing the writing speed of the entire memory device.

 Ninth embodiment>

FIG. 21 is an example different from FIG. 20 in the case where the write pulse shown in FIG. 15 is applied to a 2-bit / cell multi-level flash memory. In the threshold direct configuration shown in Fig. 6, the distribution width required for the threshold distribution "1" level and "2" level located at the center is small, but the threshold distribution is the highest. "3" level distribution width is It can be large. Therefore, when writing at the "3" level, the ISPP method for narrowing the threshold distribution is not performed, and a high voltage and multiple pulses are applied to make the "3" level as fast as possible. In the CCIP method, — writing is performed using the charge stored in the constant capacitance, so the amount of charge injected into the floating gate is limited by the amount of charge stored in the constant capacitance. In writing at the "3" level, writing is performed by applying multiple pulses, instead of setting the pulse width to a long value as shown in Fig. 14. During this time, it is necessary to verify whether the writing has been completed. The refining operation is not performed, and an extra overhead time is omitted, and the panelless voltage Vpp3 i may be Vppmax in FIG.

 The write pulse application method shown in FIG. 21 has the following effects in addition to the higher write speed. When writing to the "3" level, a wide pulse is applied at a high voltage. Therefore, if the writing to the "3" level is performed after the writing to the "1" and "2" levels is completed, the Levels "1" and "2" are subject to day staves, and the thresholds and value distribution may be broadened and become indistinguishable from other levels. In the writing method of FIG. 21, since the "3" level writing is performed before the writing to the "1" level and the "2" level, there is an effect that this problem can be avoided.

As a specific example of FIG. 21, FIG. 22 shows a write pulse when applied to the memory cells shown in FIGS. The upper part of the figure shows a voltage pulse applied to the control gate of the memory cell, that is, the lead line, and the lower part shows a voltage pulse to AG, which is the third gate of the memory cell. As described above, when writing to a memory cell, a high voltage of, for example, 13 V is applied to a read line, This is implemented by applying a voltage to the AG! Therefore, the voltage pulse to the word line takes longer time to rise and fall than the voltage pulse to AG. For this reason, in the initial pulse region in FIG. 21, it is better to apply the voltage pulse to the AG N3i times and apply the voltage of the lead line to Vpp3i during the initial pulse region than to apply the voltage pulse to the AG line N3i times. There is an advantage that writing can be performed at higher speed. The same applies to the subsequent “2” level writing and “1” level writing.

 As described above, in the first to ninth embodiments of the present invention, the description has been made on the assumption that the storage node is a polysilicon gate. However, the storage node may be a nanoscale silicon sphere. And there is no problem with silicon nitride electron traps. In addition, as an example of a multi-valued flash memory, a 2-bit / cell memory cell in which four threshold states can be formed in one memory cell was described. Needless to say, the present invention can be applied to a flash memory. Industrial applicability

 The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique for realizing high integration, high reliability, and high speed of an electrically rewritable nonvolatile semiconductor memory device.

Claims

 The scope of the claims

 A memory cell array in which electrically rewritable memory cells each formed by stacking a charge storage node and a control gate on a semiconductor layer are arranged in a matrix; and writing or writing is performed by changing a threshold value of the memory cells. A pulse applying means for erasing; and a verifying means for detecting a threshold after the pulse is applied and verifying whether the threshold voltage has reached a predetermined level. When it is determined that the value voltage has reached the predetermined level, control means for terminating the application of the pulse and, when the threshold voltage has not reached the predetermined level, applying the next pulse Wherein the pulse applying means converts the voltage of the first pulse applied before the first threshold verification in the writing or erasing into a first pulse voltage and a second threshold verification. When the voltage of the second pulse is a second of the pulse voltage applied to the first pulse voltage is a non-volatile semiconductor memory device you and sets greater than the second pulse voltage.

2. The method according to claim 1, wherein the pulse applying unit applies pulses applied after the second pulse with the same pulse width, and the pulse voltage is increased by a constant pulse height increment every time the threshold value is verified. A nonvolatile semiconductor memory device characterized in that it is set to increase.

 3. The pulse application unit according to claim 2, wherein the pulse application unit sets a pulse width of a pulse applied after a second pulse to be equal to or less than a pulse width of the first pulse. Nonvolatile semiconductor memory device.

4. The pulse application device according to claim 2, wherein the pulse application means has a pulse voltage of a predetermined voltage. And the pulse voltage applied thereafter is set to the predetermined voltage, and the pulse width is set so as to increase gradually. The first conductive layer formed on the main surface of the semiconductor substrate A mold gate; a second conductivity type semiconductor region formed in the mold so as to extend in a first direction; and a first gate formed on the semiconductor substrate via a first insulating film. A second gate formed on the first gate with a second insulating film interposed therebetween, and a third gate, wherein the end face of the third gate is between the adjacent first gates. An electrically rewritable memory cell formed opposite to the end face of the first gate, which is parallel to the first direction, and faces the end face of the first gate with a third insulating film interposed therebetween. A memory cell array disposed therein and changing a threshold value of the memory cell. A pulse applying means for performing writing or erasing, and a verifying means for detecting a threshold value after the pulse application, and verifying whether the threshold value and the value voltage have reached a predetermined level. When the verifying means determines that the threshold voltage has reached the predetermined level, the application of the pulse is terminated, and when the threshold and the value voltage have not reached the predetermined level, the next pulse mark is applied. And a pulse applying means for applying a voltage of a pulse applied before a first threshold value verification in the writing or erasing to a first pulse voltage and a second threshold value verification. When the voltage of the previously applied write pulse is the second pulse voltage, the first pulse voltage is larger than the second pulse voltage, and the width of the pulse applied after the second pulse is the same And the second pal The voltage of the pulse applied after the threshold A non-volatile semiconductor memory device characterized in that it is set so as to increase by a constant pulse height increment.

 The pulse application unit according to claim 5, wherein the pulse application unit sets a pulse width of a pulse applied after the second pulse to be equal to or less than a pulse width of the first pulse. Nonvolatile semiconductor memory device.

7. The pulse application device according to claim 5, wherein, when the pulse voltage reaches a predetermined voltage, the pulse voltage applied thereafter is set to the predetermined voltage, and the pulse width is set to be gradually increased. Characteristic nonvolatile semiconductor memory 8. A memory cell array in which electrically rewritable memory cells configured by stacking a charge storage node and a control gate on a semiconductor layer are arranged in a matrix, and at least writing is performed. Alternatively, the same number of capacitive elements as the memory cells to be erased are provided, and the charge stored in the capacitive elements is discharged through the memory cells by applying a pulse, and the hot electrons generated at that time are discharged to the floating gate. And a pulse applying means for performing writing or erasing by injecting the threshold voltage, detecting a threshold value after the pulse application and setting the threshold voltage to a predetermined level A verification unit that verifies whether or not the threshold voltage has reached the predetermined level. When the verification unit determines that the threshold voltage has reached the predetermined level, the application of the pulse is terminated, and the threshold voltage is reduced. A control unit that performs a next pulse application when the predetermined level has not been reached; the pulse application unit includes a pulse voltage applied before a first threshold value verification in the writing or erasing; The first pulse voltage and the second pulse voltage before the second threshold verification. When the first pulse voltage is larger than the second pulse voltage, the pulse width applied after the first threshold value verification is the same, and the first pulse voltage is higher than the second pulse voltage. A nonvolatile semiconductor memory device characterized in that a pulse voltage applied after threshold value verification is set so as to increase by a constant pulse height increment every time threshold value verification is performed.

 9. The non-volatile semiconductor device according to claim 8, wherein the pulse application unit sets the number of pulses applied before the first threshold value verification to be two or more. The non-volatile semiconductor memory is characterized in that the pulse applied after the first threshold verification is set to be applied at least twice between the threshold verifications.