WO2004068500A1 - Nonvolatile semiconductor memory device - Google Patents

Nonvolatile semiconductor memory device Download PDF

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Publication number
WO2004068500A1
WO2004068500A1 PCT/JP2003/001000 JP0301000W WO2004068500A1 WO 2004068500 A1 WO2004068500 A1 WO 2004068500A1 JP 0301000 W JP0301000 W JP 0301000W WO 2004068500 A1 WO2004068500 A1 WO 2004068500A1
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Prior art keywords
pulse
voltage
threshold
write
applied
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PCT/JP2003/001000
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French (fr)
Japanese (ja)
Inventor
Hideaki Kurata
Shunichi Saeki
Masahiro Sakai
Yoshinori Takase
Jiro Kishimoto
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Hitachi, Ltd.
Hitachi Device Engineering Co., Ltd.
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0491Virtual ground arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562Multilevel memory programming aspects
    • G11C2211/5621Multilevel programming verification

Abstract

A nonvolatile semiconductor memory device has control means which arranges that a pulse voltage to be applied, before a first verifying operation, to memory cells during write operation is greater than a pulse voltage to be applied before a second verifying operation and that any pulse voltage to be applied after the first verifying operation is increased by a constant pulse height increment each time a threshold value verifying operation is performed. In this way, a narrow-band of threshold voltage can be obtained without any increase of write time, and the write speed of the whole memory can be raised.

Description

Nonvolatile semiconductor memory device

TECHNICAL FIELD The present invention relates to electrically rewritable nonvolatile semiconductor memory device, a storage nonvolatile semiconductor memory device particularly multi de Ichita.

Akira field

BACKGROUND Flash memory is portability, excellent 耐衝 擊性, electrically can be collectively erased cry and force ゝ al, in recent years, rapid as a file of a small portable information devices such as a portable Per saw null computers and digital still cameras demand is growing. Its the expansion of the market is essential to reduce the bit cost by the reduction of the memory cell area, various memory cell systems for accomplishing this have been proposed. One of them, for example, Japanese Patent Application No. 11 - 200242 as shown in, there is a virtual ground type memory cell using a three-layered polysilicon gate. The memory cell, as shown in FIG. 1, Ueru WEL in the silicon substrate SUB, Seo in Ueru Ichisu, drain diffusion layer regions DR, and Helsingborg silicon film or formed on Weru Ranaru first gates become the floating gate one DOO FG, a second gate becomes Bok control gate Bok VV, and consists of three gate Bok third gate Bok become auxiliary gate AG. AG and FG are disposed through an insulating film TOX as that formed for example Si0 2 on WEL. Among them, the third gate AG is present is embedded in the gap of the floating gate FG that is present in the word line and the channel and vertical direction, between the floating gate FG, for example, Si0 2 of such an insulating film and it has a separate constituted by SWA. Also, the floating Gut FG and and also SWF made of a polysilicon film is an insulating film IPO, has been separated from the Wado line WL, and the third gate AG is the absolute Enmaku CA and IPO, a word line WL separation It is. Source / drain diffusion layers DR are arranged perpendicularly to word line WL, and exists as a local source line and a local data line for connecting the source / drain of the memory cell in the column direction (X direction). Consists contactors Torres-type array having no contactor Bokuana for each memory cell, it is possible to improve the formation density of the memory cells, the memory cell area 4 F 2: can be reduced to (F minimum feature size).

The memory cell, as well as miniaturization, to allow fast writing. It shows the voltage application condition at the time of the memory cell write in Fig. Select a positive voltage of the drain and about 5 V, for example, in the diffusion layer D n ing of the memory cell M, a positive voltage of about 1 3 V for example, Wa word line WLn of the selected memory cell M, selected the third MO S transient threshold I straight about the voltage of the static constituted by gate Bok to the third gate AG e of memory cells M and M + 2, for example, applying a degree IV. Diffusion layer D n-1 to be the source of the selected memory cell M, Ueru, the unselected word line WL n + 1 is held at 0 V. With the above operation, a large electric field in the horizontal method and vertical direction are formed in the channel boundary subordinates the floating gate Bok and third gate. Thereby increasing the generation and injection efficiency of hot Bok electronics Bok Ron, even though the channel current is small, thereby enabling high-speed writing. In conventional hot Elec tron injection method, with respect to the injection efficiency in the range of 10- 6 10_ 5, in this method, it is possible to obtain a high injection efficiency of approximately 10_ 3. Therefore, even when using an internal power source having a current supply capacity of about 1 mA, it is possible to write kilobytes or more memory cells in parallel.

Further, in the flash memory, as a method of realizing a cost reduction, 1999 IBaa International Solid and one State Circuits As shown in onference Digest of Technical Papers ρ.110~111, a plurality of threshold in one memory cell provided value voltage levels, multi-level techniques to hold the multi-bit data is known.

The memory cell shown in FIG. 1 when applied to a multi-level flash memory, it has been shown as a method for writing speed, for example, DIGEST OF TECHNICAL PAPERS 2002 SYMPOSIUM ON VLSI CIRCUITS p.302~303, Constant Charge Injection Programming method (hereinafter CCIP system and referred to) there is. The CCIP method, as shown in FIG. 3, keep an electric charge is charged at a constant capacitance C provided on the drain side of the memory cell MEM, a write only by flowing only the charge stored in the capacitor in the memory cell do. Figure 4 shows the write operation mode of the CCIP scheme. First, the internal power supply PROG to the supply channel current at timing t 0 and 5 V, and the SWS and SED at timing t 1 raised a Suitchingu MOS source side and the drain side of the memory cell MEM STS, the ON state of the STD. Next, apply a write voltage 1 3V to Wado line WL of the selected memory cell at the timing of t 2. Thereafter, the drain-side Roh one de ND force of the memory cell MEM; when charged to 5 V, and the SWD to fall at the timing t 3, the STD is the drain side of the switch MOS and 〇 FF state, the internal power source PROG detach and. By applying a degree IV in AG selection menu Moriseru at a timing t 4, the charge accumulated in the node ND begins to flow to the source side through the memory cell. Writing only by hot Toereku Tron generated in the channel region of the time memory cell are injected into the floating gate occurs. Node ND on the drain side potential decreases as the channel current flows, but writing takes place while generating the Chiyane Le portion high enough horizontal electric field generation of hot Elec Bok Ron. Without the CCIP method for writing cells of kilobytes I Units in parallel, it is necessary to suppress the amount of current per cell below several hundred nA, Therefore the memory cell to the third gate AG set the voltage you applied example below IV to, it is necessary to operate in the subthreshold region. Such as by size variation of the order AG unit, but will be writing characteristics of the memory cell varies greatly, according to the CCIP system can play variability of the writing characteristic is greatly improved. On the other hand, in the multi-level flash memory, the threshold voltage corresponding to each data, a very narrow distribution width is required. When writing is the threshold voltage of each memory cell, it is necessary to fall within the scope of this narrow threshold distribution. Generally it is realized with application of the write pulse, threshold by a read (verify) to verify whether the written, the narrowing value. That is, in multilevel flash memory, the writing characteristic Baratsukigadai heard among the memory cells, since the number of verification is much needed, storage entire writing is slow Kunar problem. According to CCIP method, it is possible to reduce the programming variation between memory cells on a large width, it is possible to reduce the number of verify operations, the effect of the writing speed of the multi-level flash memory can be increased.

As noted above, the writing of the large-capacity flash memory is performed simultaneously for one more memory cells that Tsurana to Wado line. Because the writing speed is different by the memory cell, while verification of the threshold voltage Vth, is applied repeatedly write pulse. Shikire to a predetermined write level, and the memory cell write viewed prohibited state value Vth rises, when the memory cell to be written is written all document, i.e., all the memory cells to be written threshold voltage Vth so that the writing has been completed at the time when reached to a predetermined level. .

In such writing method, writing included speed is determined by the slowest memory cell the write speed. Writing to writing faster writing the slowest memory cell, it is contemplated et al is to increase the force \ write pulse width to increase the address pulse voltage. And then force, In this way, fast memory cell with write, the first pulse, there is a possibility that is written above the threshold voltage Vth allowed the Shimare ,, erroneous writing. In particular, one in the memory cell of the plurality Shikire, multilevel flash memory to hold the multi-bit data by providing a value level. In Li has a width of for example 0.4V approximately of the threshold voltage Vth allowed for each level very small and, the write error fast memory cell with the write exceeds a predetermined threshold voltage Vth. Therefore, both the fast memory cells and slow memory cell with the write of write, so that put the fastest writing within a threshold voltage range allowed, it is necessary to optimize the method of applying the pulse.

As a means to make this possible, for example, JP-A-7 169 284 and JP-flat U - 134 879 as shown in ISPPdncremental Step Pulse Programming) method has been proposed. Figure 5 is a representation of a write pulse in 1SPP method shows a pulse voltage applied to a word line Wa. Low voltage pulse Vvr in the figure is a pulse applied in Berifuai operation, high voltage, e.g. Vpp pulse is a pulse which is applied in the write operation. The write operation and have verify operation becomes one cycle, until the write is completed, the cycle is repeated. The ISPP method is characterized in that is increased by 厶 Vpp voltage pulse for each application cycle. In this way, fast notes Riseru of writing, the initial writing is completed between address pulse voltage is low, never the subsequent high pulse voltage is applied, it can be prevented that excessive written. Further, with respect to the slow memory cell of a write, since the write pulse voltage is going up each pulse application, from continuing to apply the pulses of the same voltage, it will be written faster writing. Further, JP-A-134879 shows an example of applying the ISPP method multilevel Flash memory of 2 bit / cell. Figure 6 shows the relationship between data and threshold voltage distribution in the multi-level flash memory of 2 bit Bok / cell. With settable threshold distributions of 4 state, it is possible to hold the data of 2 bits in one memory cell. Figure 7 shows an application of the ISPP method multilevel flash memory of 2 bit Bok / cell. Writing to "1" level at Ri, writing to the "2" level in [rho] 2, it is performed each writing to "3" level in [rho] 3. First, at P1, from the initial programming pulse VPPL, we write in that we raise the pulse voltage by delta VPPL every write cycle, verified by corresponding to behenate Rifai voltage Vvrl to "1" level. Repeat this cycle, "1" when the memory cell to be written to the level has become all write completion, the process proceeds to "2" level of writing included P2. In P2, the initial write pulse Vpp2, writes in that we raise the pulse voltage by A Vpp2 for each write cycle verifies at Berifuai voltage Vvr2 corresponding to "2" level. Repeat this cycle, the memory cell to be written to "2" level for all when a write completion, the process proceeds to "3" level of the write P3. Similarly, in P3, from the initial write pulse Vpp3, the verification in writing included in each cycle have line to write in that we raise the pulse voltage by Δ ν Ρ ρ3, "3" base equivalent to the level Rifai voltage Vvr3 do. Repeat this cycle, "2" when the memory cell to be written and a has decreased every completion of writing to the level, so that the multi-level programming has been completed.

In the above ISPP method, there is a limit to the writing speed. That is, even in the most fast-bit write, not sufficiently threshold voltage increases in the initial pulse low voltage is that it requires a plurality of pulses until the completion of writing. In JP-A-11-39887, in order to speed up the writing of the ISPP method, technique which has been subjected to improvement is shown open. Here, as shown in FIG. 8, first longer than the pulse width of the second pulse width in the writing, it is set shorter than the second pulse voltage to the first pulse voltage. Therefore, the fastest bit write would write in one or several pulse ends.

However, in the above technique, in particular the writing speed of the multi-level there is a limit. That is, in multilevel flash memories, it is necessary to form a plurality of threshold state, the setting range of the threshold becomes wider remote by flash memory of conventional 1-bit / cell. Therefore, in the write complete the fastest bit write by one pulse, it is necessary to apply a more wider pulses. The amount of change in the threshold, since the substantially proportional to the logarithm of the pulse applying time, the pulse width to be applied to the first exponentially increases, thereby decreasing the writing speed significantly. Further, when executing the writing of the multi-level flash memory according CCIP method described above can not be that it conventional write pulse application method to speed up the writing speed of the entire storage device. The nonvolatile semiconductor memory equipment typified by a flash memory, since the increased data capacity handled such as video increasingly, further improvement in speed is required to its write and erase. The present invention Against this background, the improvement of the writing process, it is possible to shorten the write time of the whole memory device is to provide a nonvolatile semiconductor memory device capable of realizing improvement of the writing speed. Disclosure of the Invention

To achieve the above object, a nonvolatile semiconductor memory device of the present invention applies a write or erase signals comprising a plurality of pulses, by performing Professor receive charge to charge storage node, the threshold voltage controls, a non-volatile semiconductor memory device having a memory element that holds information according to the threshold voltage to detect the threshold voltage of the memory element after each pulse application, the threshold voltage when but which have (verifying) verification means for verifying whether reaches a predetermined level, the threshold voltage of the memory element is determined to have reached the predetermined level by said verification means, said pulse application is terminated, and when it is determined that it has not reached the predetermined level, a control means for performing the following pulse application, application of prior first threshold verification in the write or erase The first pulse voltage of the first pulse voltage that, second Shikire, when the second / pulse of the voltage applied to the pre-value verification was second BALS voltage, the first voltage pulse having a control means for setting larger than the second BALS voltage.

Further, in the present invention, preferably the pulse is applied after the second pulse, pulse width are the same, also the pulse voltage is increased by a constant pulse height incremented each to verify the threshold set to. Further, in the present invention, the control means may set such that the pulse width of the path Noresu applied after the second pulse with the same or less than the pulse width of the first pulse, also, the pulse voltage when reaching a predetermined voltage, pulse voltage to be applied to subsequent to the predetermined voltage, it has a feature that can be configured to gradually increase the pulse width. The present invention, it is possible to optimize the write pulse, without increasing the write time, to achieve narrowing of the threshold, enabling the write speed increase of the entire memory device.

Further, the present invention particularly, a first conductivity type Ueru formed on the main surface of the semiconductor substrate, a second conductivity type semiconductor region formed to extend in a first direction within the Ueru, the semiconductor a first and a gate Bok formed via a first insulating film on the substrate, a second gate formed via a second insulating film on the first gate, and a third gate, the end surface of the third gate I, to face through the first gate end face and the third insulating film, which exist in parallel to the first comprising an end surface opposed to the gate a first direction adjacent the electrically rewritable memory cell formed is applied to the memory cell arrays arranged in a Matoritasu shape is desired. Since the memory cell is capable of writing at a high speed with high hot electronics Bok Ron injection of injection efficiency, together with optimization of the write pulse, it is possible to quickly Ri by the write of the entire memory device.

Further, in the present invention, a memory Seruarei electrically rewritable memory cells are arranged in a matrix which consists by stacking a control gate and a charge storage node on the semiconductor layer, the memory cell for at least write or erase by the provided the same number of capacity element, the charge that has been accumulated in the capacitor discharges through the memory cell by applying a pulse to note enter the floating gate of hot Bok electronics Tron generated when the , for the flash memory having means for writing or erasing, detects the threshold after pulse application verification means for verifying whether reached the threshold voltage to a predetermined level has, when it is determined that the threshold voltage has reached the predetermined level by said verification means, to terminate the application of the pulse, the Shikire, a value voltage predetermined When it does not reach the level, a control means for performing the following pulse application, the voltage of the pulse applied before first threshold verification in the writing or erasing the first pulse voltage, the second tooth when the pulse voltages applied to front threshold validation and second pulse voltages, the first pulse voltage is applied increases, also the first threshold verify later than the second pulse voltage a width of the pulse the same, also the pulse voltage to be applied to the first threshold verification and subsequent is controlled to be set to increase by a constant pulse height incremented each to verify the threshold It has the means.

Furthermore, the control means, first Shikire, characterized by setting the pulses applied before the value verification as is more than once, also be applied to the first threshold verification or later that pulse, and sets to be applied at least twice during the threshold verification and threshold verification. Thus, particularly in multi-level harm inclusive operation, and suppression of the writing characteristic variation of the memory cell, it is possible to realize the optimization of Gaikomi pulse, it is possible to realize a writing speed up the whole memory device. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram showing a structure of a memory cell for implementing the write speed and miniaturization. Figure 2 is a diagram showing the array structure of the memory cell. Figure 3 is a circuit diagram showing the operation of the CCIP method. Figure 4 is a waveform diagram showing the operation of the CCIP method. Figure 5 is a waveform diagram showing a write pulse waveform by ISPP method. Figure 6 is a diagram illustrating a threshold distribution of the 2 bit / cell. 7, in the case of applying the ISEP method 2 bits Bok / cell is a waveform diagram showing a write pulse waveform. Figure 8 is a waveform diagram showing a write pulse waveform of the conventional writing method. 9, in the first embodiment, is a waveform diagram showing a write-inclusive pulse waveform. Figure 1 0 is a diagram showing a configuration example of a write pulse generator circuit that put the present invention the first embodiment. Figure 1 1 is a write pulse waveform in the present invention the second embodiment. Figure 1 2 is a write pulse waveform in the third embodiment of the invention. Figure 1 3 is a write pulse waveform in the present invention the fourth embodiment. Figure 1 4 is a write pulse waveform in the present invention the fifth embodiment. Figure 1 5 is a write pulse waveform in the present invention sixth embodiment. Figure 1 6 is a write pulse waveform in the present invention sixth embodiment. Figure 1 7 is a write pulse waveform in the present invention sixth embodiment. Figure 1 8 is a write pulse waveform in the present invention sixth embodiment. Figure 1 9 is a write BALS waveform in the present invention seventh embodiment. 2 0 is a write pulse waveform in an embodiment of the present invention eighth. Figure 2 1 is a Contact Keru write pulse waveform to the present invention the ninth embodiment. 2 2 is a write look pulse waveform of the present invention the ninth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION <First Embodiment>

9 Ri FIG der showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, is a waveform diagram showing a write pulse in the present embodiment. In this embodiment, the conventional ISPP method, is set higher than the pulse voltage Vpp applied pulse voltage Vppi applied to write initial second. Writing the initial pulse voltage Vppi is fastest bit Bok of writing, by the pulse, be set to be written to a threshold voltage as a target is preferable. In accordance with the second and subsequent pulses ISPP method writes by increasing the pulse voltage by ΔνΡΡ.

Figure 10 is a diagram showing a configuration example of a write pulse generator circuit in this embodiment. The write pulse generating circuit is constituted by an internal power supply circuit CP and Wadodekoda DW. Input signal SEL to the internal power supply circuit CP is a signal for selecting a voltage level to be generated and by connexion controlled CPU in the non-volatile semiconductor memory device. The signal STP is a signal for selecting the pulse width, is output from the CPU in the same non-volatile semiconductor memory device and SEL. The STP and § de Les selection signal ADH, Wadodeko one da DW becomes possible to output a Baiasu having a pulse width and the pulse voltage Jo Tokoro to Wado line selected. In the conventional example shown in FIG. 8, for example, an initial pulse width 50 mu 3, a pulse voltage was 14.5 V, the second and subsequent pulse width 2 s, was increased pulse voltage stepwise by 0.5V. However, in accordance with the present method, the width of the initial pulse and the same 2 μ β and the second and subsequent pulse width, to set the pulse voltage to the high 16V about Ri by the second pulse voltage 15V. Thus, before the fastest bit Bok write is a write completion, will be the initial pulse width was needed prior 50 S can be reduced to 2 S, it is possible to significantly write speed.

<Second Embodiment>

Figure 11 is a waveform diagram showing a write pulse in another embodiment of the present invention. Previous voltage and which can be generated by the internal power supply circuit CP that describes the breakdown voltage of Bok run register in Wadodekoda, the upper limit there Ru etc. Possible pulse voltage ensure the reliability of the memory cell. Therefore, in particular as multi-level flash memory, when it is necessary to greatly shift Bok the threshold, even using the maximum pulse voltage available, the same pulse width of the initial pulse and second and subsequent a possibility that can not be set to pulse width occurs. Therefore, in this embodiment, as shown in FIG. 11, the initial pulse, with a maximum pulse voltage Vppmax available, sets the pulse width to have greater than the pulse width Tpp the second and subsequent TPPI. Thus, as in the multi-level flash memory, even if the threshold voltage change amount that is required when writing is large, the fastest bit of writing, the initial pulse, to a predetermined threshold voltage written is written. Furthermore, since the use of the maximum voltage that can be used for the initial pulse, there is an advantage of being able to write complete writing most Hayare, the bits in the shortest time.

Ku third embodiment>

Figure 12 is a waveform diagram showing a write pulse in another embodiment of the present invention. As in the multi-level flash memory, when it is necessary to greatly shift Bok threshold voltage, even using the maximum pulse voltage available, may not write is completed by the ISPP method. Therefore, as shown in FIG. 12, when it reaches the pulse voltage maximum available voltage Vppmax when carrying out the write only the ISPP method, the subsequent pulse increasing the pulse width while a pulse voltage was Vppmax make. At this time, the width of each pulse, the threshold voltage shift Bok amount that varies for each pulse is constant and Do - it is desirable to have been set to. Further, in FIG. 12, the initial pulse voltage is Vppmax, but may be not large Tppi than the pulse width Tpp whose pulse width is used ISFP. According to this embodiment, only the ISPP even if the writing is not completed, by increasing the pulse width, there is an effect that it is possible to quickly complete the writing.

Ingredients Fourth Embodiment>

Figure 13 is a write pulse shown in FIG. 9, an example of the application of the multi-level flash memory of 2 bit Bok / cell shown in FIG. Each write cycle Pl, P2, P3 is in table writing to "1" level, "2" level, "3-level" in FIG. 6. In each write cycle, as shown in FIG. 9, the initial pulse and subsequent

Writing is performed by ISPP. First write cycle; In P1, the initial pulse

The VPPL i, the fastest bit Bok writing is set to be a write completion, by subsequent ISPP, sequential write is advanced. Initial pulse voltage Vpp li is greater than the initial pulse voltage Vpp 1 of ISPP. Step voltage delta Vp 1 of ISPP is "1" same as acceptable threshold distribution width level, or is set to less. "1" after writing to the level of the end, "2" write cycle P2 to the level is started. In write cycle P2, the initial pulse Vpp2 i, is set to be a write completion to the fastest bit Bok force "2 ,, levels of writing, by subsequent ISPP, sequential write is advanced. Where the initial pulse voltage Vpp2 i is larger than the first pulse voltage Vpp2 of ISPP les. step voltage AVpp2 of ISPP is "2" the same as the acceptable threshold distribution width level, or it is set below. "2" level after writing to an end, "3" in the write cycle P3 force to level S is started. write cycle P3, the initial pulse Vpp3 i, such as the completion of writing to the fastest bit solved ^ 3 "level of the write set, by subsequent ISPP, sequential write is advanced. Here the initial pulse voltage Vpp3 i is greater than the first pulse voltage Vpp3 of ISPP les. Step voltage AVpp3 of ISPP is "3" same as the acceptable threshold distribution width level, or it is set below. If writing to this "3" level is finished, so that the multi-valued level of writing has been completed. Here, as in the example 'T level and the shift Bok amount of the threshold voltage required at the time of writing is small, it may be omitted by applying an initial pulse. Further, for example, "3" as in the case shift amount of the threshold voltage required at the time of writing is large, the initial pulse voltage is Vppmax, using the pulse width ISPP pulse by setting larger than the width Tpp, it is possible to write faster storage instrumentation 置全 body.

<Fifth Embodiment>

Figure 14 is a write pulse shown in FIG. 9, an example different from that of FIG. 13 in the case of applying to the 2 bit / cell of the multi-level flash memory. Shikire, the value configuration shown in FIG. 6, colored paper located in the center, the value distribution is a "1" level and "2" is leveled distribution width required for Honoré is small, the uppermost Shikire, distribution width value distribution is "3" level may be greatly. Therefore, in the writing of "3" level, without performing ISPP for narrowing the threshold distribution by applying a wider pulse width at a high voltage, as fast as possible "3" level to end the writing. 14, Bruno, ° ls e voltage Vpp3 i may be Vppmax. The write pulse applying method of FIG. 14 is effective as described below in addition to the writing speed. "3" in writing to level, to apply a wider pulse width at a high voltage, "gamma and" 2 "after completion of writing to the level" 3 "when writing to the level takes place already after the forming" 1 "and" 2 "level disturbed the threshold distribution is spread, may become indistinguishable from other levels. the writing method of FIG. 14," 1 "level and" 2 "to level prior to writing, "3" because the level writing is performed, the effect of this problem can be avoided.

<Sixth Embodiment>

Figure 15 is Ri FIG der showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, is a waveform diagram showing a write pulse in the present embodiment. This embodiment, the charge stored in the capacity of a certain discharges through the memory cell assumes a programming method of injecting hot Tereku Tron generated when the floating gate. In the following, we have you a flash memory having a third gate Bok shown in FIGS. 1 and 2, the CCIP method shown in FIGS. 3 and 4, that describes an application example of the present invention. By applying the ISPP method even in CCIP method, it is possible to increase the speed of writing. Furthermore, even in the CCIP scheme, similar to FIG. 9, the higher is set higher than the pulse voltage applied to the initial pulse voltage for the second time, it is possible to obtain a similar effect. And force Shinano force, et al., In particular as multi-level flash memory, when it is necessary to greatly shift the threshold I straight can be used the maximum pulse voltage available, the pulse width of the initial pulse possibility of a second or subsequent can not be set to the same pulse width occurs. And normal hot Elec tron ​​injection method, if the writing by the source over the scan side injection writing or Fowler Nordheim tons, channel current, using a maximum pulse voltage Vppmax available for the initial pulse, as shown in FIG. 11, the pulse by setting the width greater than the pulse width Tpp the second or subsequent TPPI, it is possible to realize high-speed. But like the name husk CCIP method, when writing with the charge accumulated in the constant volume can not be obtained the effect of speeding be longer pulse width. This is because the amount charge injected into Floating Nguge one Bok is constrained by the amount of charge stored in a volume. Therefore, as shown in FIG. 15, the initial pulse area Pinit, - a plurality of times accumulation of charges to a constant volume, the discharge by the memory cells. During this time, the base Rifai operation to verify whether the written-inclusive has been completed is not performed, most fast I bit Bok of the writing is in this initial pulse area, so that the writing is complete, set the number of times Ni and pulse voltage Vppi it is desirable. The pulse setting shown in FIG. 15, there is an effect that can realize the writing speed in CCIP scheme. Specific examples of FIG. 15, shown FIG. 1, the write pulse is applied to the memory cell shown in FIG. 2 in FIG. 16. The upper part of FIG. Shows the voltage pulse applied to the control gate Bok i.e. Wado lines of the memory cell, and the lower stage shows the voltage pulse to the AG, the third gate of the memory cell. As mentioned above, write to the memory cell by applying a high voltage of 13V for example Wado line, the AG is performed by applying Shikire, a low voltage of about the value voltage. Therefore, a voltage pulse to the word line, as compared with the voltage pulse AG, becomes a this takes time to start-up and falling down. Therefore, in the initial pulse area in FIG. 15, rather than applying Ni times a voltage pulse to the word line, is better to a voltage pulse to the AG applies Ni times, and sets the between Wado line voltage Vppi- a constant , there is an advantage of the Rukoto can be performed to write faster.

Also, as noted earlier, the CCIP method for writing using an electric charge stored in the constant volume, the amount of charge to be injected into the floating gate, it is constrained by the amount of charge stored in a volume. Therefore, if and accumulated charge is small, if the injection efficiency is small, there is a possibility that no threshold is sufficiently changed in one injection operation. In such a case, as shown in FIG. 17, Te region odor Pispp, by applying a plurality of pulses, for example Ns times a cycle, it is possible to secure the amount of shift of the threshold voltage . Further, it is shown Figure 1 this method, a write pulse is applied to indicate the memory cell 2 in Figure 18. The upper part of FIG. Shows the voltage pulse applied to the control gate That Wado lines of the memory cell, and the lower stage shows the voltage pulse to the AG, the third gate of the memory cell. As described above, writing to the memory cell by applying a high voltage to the word line for example 13V, the AG is performed by applying a low voltage of about the threshold voltage. Therefore, a voltage pulse to the word line, as compared with the voltage path Noresu of AG, it takes time to start-up and falling down. Therefore, in Pispp region in FIG. 17, rather than applying Ns times a voltage pulse to the Wado lines between Berifuai, a voltage pulse to the AG applies Ns times, is better to set a constant between Wado line voltage , there is an advantage that would be capable of performing write faster.

<Seventh embodiment>

19 Ri FIG der showing an embodiment of a nonvolatile semiconductor memory device according to the present invention, is a waveform diagram showing a write pulse in the present embodiment. As the multi-level flash memory, when it is necessary to greatly shift the threshold voltage, even using the maximum pulse voltage available, may not write is completed by the ISPP method. And normal hot electron injection, Sosusai Doinjekushi tio emission write or Fowler Nordheim tunneling current due to the writing der lever, as shown in FIG. 12, the maximum pulse voltage is available when carrying out the write by ISPP method, when reaching the voltage Vppmax, subsequent pulses is possible to speed by gradually increasing the pulse width while a pulse voltage was Vppmax. As such, les, such obtained the effect of speeding even if, by increasing the pulse width for writing using an electric charge stored in the constant volume of However while, CCIP scheme. This is because the charge amount injected into the off Rote queuing gate is by connexion constrained to the charges accumulated amount constant volume. Therefore, as shown in FIG. 19, and have contact ISPP region Pispp, after the pulse voltage reaches Vppmax realizes faster writing by gradually increasing the number of pulses. Here, the number of pulses, a number of times to repeat the discharge due to the accumulation and the memory cell in the charge to the constant volume, during which not perform base verifies Rifai operate whether writing has been completed. The pulse number, it is desirable that the shift amount of threshold voltage is set to be constant. For example, in FIG. 19, the threshold voltage shift amount of Nb l times of the pulse applied, followed by a threshold shift amount of Nb2 times pulse application to be performed to set the number of times to be the same. According to this embodiment, only the ISPP even if the writing is not completed, by increasing the number of pulses, there is an effect that it is a call to complete the write quickly. Furthermore, when applied to the memory cell shown in FIG. 1, 2, like the sixth embodiment, while the word voltage constant, it is desirable that the method of applying a plurality of times voltage of AG.

'Figure 20 <Eighth Embodiment> The write pulse shown in FIG. 15, an example of applying the Tijika flash memory of 2 bit / cell shown in FIG. Each write cycle Pl, P2, P3 is in table writing to "1" level, "2" level, "3-level" in FIG. 6. In each write cycle, as shown in FIG. 20, is due connexion write the ISEP area after the initial pulse area and its place.

First, in a write cycle P1, the initial pulse area, a pulse voltage VPPL i, Nl i times of the pulse is applied. Thus,. The initial pulse voltage VPPL i is set to be the fastest bit force ^ 1 "level write completion of the write

Greater than the initial pulse voltage Vpp 1 in ISPP region. Step voltage Δνρρΐ in ISPP area, "1" same as acceptable threshold distribution width level, if Ku is set to less. In ISPP region, repeated pulse application and verification, "1" all bits to be written to the level, if it is determined that the write incompletion by verifying the write cycle P1 is completed, the write cycle P2 is started that.

In writing Saikunore P2, in the initial pulse area, a pulse voltage Vpp2 i, N2 i times of the pulse is applied. Thus, the fastest bit force writing; is set to be "2" level write complete. The size les than the first pulse voltage Vpp2 in the initial pulse voltage Vpp2 i is ISPP area. Sutetsu flop voltage delta Vpp2 in ISPP region, "2" Shikire acceptable level, the same as the value distribution width, or its being set below. In ISPP area, to repeat the pulse application and verification, "2" all the bits to be written to the level, if it is determined that write complete by verifying the write cycle P2 is completed, the write cycle P3 is started; ^ Ru.

In write cycle P3, the initial pulse area, a pulse voltage Vpp3 i, N3 i times of the pulse is applied. This is set to be the fastest bit force '2 "level write completion of the write. Initial pulse voltage Vpp3 i is Sutetsu flop voltage at first greater than the pulse voltage Vpp3. ISPP region in ISPP area Δ Vpp3 is "3" Shikire acceptable level, the same as the value distribution width, or its being in. ISPP region set below, to repeat the pulse application and verification, "3" to be written to the level all bits, when it is determined that the write completion by verify, write cycle P3 is completed, so that multi levels all write is completed. here, for example, "1" level as when writing If shift Bok amount of the threshold voltage required for the small, there is a possibility that the initial pulse region is not required. also, for example, "3" as the level required when writing If a large shift Bok amount of the threshold voltage is, by the pulse voltage of the initial pulse area and Vppmax, there is an effect that it is possible to write speed of the entire storage device.

Ingredients ninth embodiment>

Figure 21 is a write pulse shown in FIG. 15, an example different from that of FIG. 20 in the case of applying the multi-level flash memory of 2 bit Bok / cell. The threshold I straight configuration as shown in FIG. 6, but the distribution width required for a threshold distribution is "1" level and "2" level at the center is small, is the uppermost threshold distribution "3" distribution width of the level may be larger. Therefore, "3" level in the write, without performing ISPP method for narrowing the threshold distribution, the high voltage and the plurality of by applying a pulse, can only speed device '3' level the write terminates the CCIP method, -.. for writing using an electric charge stored in the constant volume, the amount of charge injected into the floating gate is limited by the amount of charge accumulated in a volume Therefore in the writing of "3" level, instead of setting a longer pulse width as shown in FIG. 14 and writes by applying a plurality of pulses. During this time, whether written lump is complete verification Surube Rifai operation is not performed, are omitted head time to unnecessary over. Further, in FIG. 21, Panoresu voltage Vpp3 i may be Vppmax.

The write pulse applying method in FIG. 21 is effective as described below in addition to the writing speed. "3" in writing to level, applying wider pulses at high voltage, "1" and "2" when writing to the write complete after "3" level to the level takes place already after formation "1" and "2" level is subjected to Deisutabu of Shikire value distribution widens, there may not be able to distinguish them from other levels. The writing method of FIG. 21, "1" level and "2" prior to writing to level "3" because the level writing is performed, the effect of this problem can be avoided.

As a specific example of FIG. 21 shows FIG. 1, the write pulse is applied to the memory cell shown in FIG. 2 in FIG. 22. The upper part of FIG. Shows the voltage pulse applied to control one Rugate i.e. Wado lines of the memory cell, and the lower stage shows the voltage pulse to the AG, the third gate of the memory cell. As described above, writing to the memory cell by applying a high voltage of 13V for example Wado line, threshold! / The AG, the value voltages as low les is performed by applying a voltage. Therefore, a voltage pulse to the word line, as compared to the voltage pulse of the AG, it takes a long time to start-up you and stand down. Therefore, in the initial pulse area in FIG. 21, rather than applying N3i times a voltage pulse to the Wado line, a voltage pulse to the AG applies N3i times, is better to set therebetween Wado line voltage Vpp3i- a constant , there is an advantage that would be capable of performing write faster. This subsequently-out carried out "2" level write the same in the "1" level write.

May above, in the embodiment 1 of the present invention 9, although storage Roh one de have Gyotsu description assumes that a polysilicon gate, also stored Roh one de is filed nanoscale silicon spheres through, there is no problem in the electron trap of silicon Nai stride. As an example of the multi-level flash memory has been describes a memory cell of one to the memory cells can form a four threshold states and the two bits Bok / cell, 3 bits / cell or more multilevel It can of course be applied to the flash memory. Industrial Applicability

The present invention relates to a semiconductor integrated circuit device, particularly integration of electrical rewritable nonvolatile semiconductor memory device, highly reliable, it relates to a technique for realizing a high speed.

Claims

The scope of the claims
. And Memoriseruare I which electrically rewritable memory cell formed by stacking a control gate and a charge storage node on the semiconductor layer are arranged in a matrix, writing by changing the threshold value of the memory cell or a pulse applying means for erasing, detect the threshold after pulse application, a verification means for verifying whether reaches the threshold voltage to a predetermined level, threshold by pre Symbol verification means when the value voltage is determined to reach the predetermined level, to terminate the application of the pulse, when the threshold voltage has not reached the predetermined level, the control means for the following pulse application has the pulse applying means, said write or first voltage of the first pulse first pulse voltage to be applied before the threshold verification in erasing, the second threshold verification When the voltage of the second pulse is a second of the pulse voltage applied to the first pulse voltage is a non-volatile semiconductor memory device you and sets greater than the second pulse voltage.
2 in. Claim 1, wherein the pulse applying means, the pulses applied to the second and subsequent pulses, the pulse width is the same, also the pulse voltage by a predetermined pulse height incremented each to verify the threshold the nonvolatile semiconductor memory device according to feature to set as increasing.
3. In claim 2, wherein the pulse applying means, characterized in that the pulse width of the pulse applied to the second and subsequent pulses is set to be the same, or hereinafter as the width of the first pulse the nonvolatile semiconductor memory device according to.
4. In claim 2, wherein the pulse applying means, when the pulse voltage reaches a predetermined voltage, that is the pulse voltage to be applied after a predetermined voltage is set so as to gradually increase the pulse width a first conductivity type © le formed on the main surface of the non-volatile semiconductor memory semiconductor substrate, wherein, a second conductivity type semiconductor region formed to extend in a first direction in the © in Le, a first and a gate Bok formed via a first insulating film on the semiconductor substrate, a second gate Bok formed via a second insulating film on the first gate, and a third gate , the end face of the front Symbol third gate, through the end face of mediation in opposite end faces between the first gate Bok adjacent existing in parallel to said first direction said first gate Bok and the third insulating film It is arranged electrically rewritable memory cells opposed to being formed on Matrix form And a memory cell array, and pulse applying means for performing the O connexion write or erase to changing the threshold of the memory cell, detecting a threshold after pulse application, the Shikire, a value voltage predetermined a verification means for verifying whether the reached level, when it is determined that the threshold voltage has reached a pre-Symbol predetermined level by said verification means, to terminate the application of the pulse, the Shikire, when the value voltage does not reach the predetermined level, a control means for performing the following pulse indicia pressure, the pulse applying means is applied before the first threshold verification in the write or erase pulse large pulse voltage of the voltage first, when a second voltage of the writing pulse applied before threshold verification and the second pulse voltage, the first pulse voltage than the second voltage pulse hear, also The width of the pulse applied to the second and subsequent pulses have the same, and the voltage of the pulse applied to the second and subsequent pulses, to increase by a predetermined pulse height incremented each to verify the threshold nonvolatile semiconductor memory device and setting the.
In. Claim 5, wherein the pulse applying means includes a setting means sets the pulse width of the pulse applied to the second and subsequent pulses, as is the same or less than the pulse width of the first pulse nonvolatile semiconductor memory device.
7. The method of claim 5, wherein the pulse applying means, when the pulse voltage reaches the predetermined voltage, the pulse voltage to be applied after a predetermined voltage, to set so as to gradually increase the pulse width and Memoriseruare nonvolatile semiconductor memory 8. charge storage node in the semiconductor layer and the control gate Bok a formed by laminating the electrically rewritable memory cells are arranged in Conclusions re box-shaped, wherein at least write or comprising a memory cell and the same number of capacitive elements for erasure, and discharged via the memory cell by applying a pulse accumulated keep charge to the capacitive element, hot Bok electronics Bok Ron floating gate that is generated when the by injecting a has a pulse application means for writing or erasing, by detecting the threshold after the pulse application, the threshold voltage predetermined level A verification means for verifying whether or not reached, when it is determined that the threshold voltage has reached the predetermined level by said verification means, to terminate the application of the pulse, the threshold voltage when not reached the predetermined level, a control means for performing the following pulse application, the pulse applying means, the write or voltage pulse applied before first threshold verification in Clear a first pulse voltage, when the second pulse of the voltage applied before the threshold verification and the second pulse voltage, the first pulse voltage is greatly than the second pulse voltage and 1 times th Ri same der pulse width to be applied after the threshold verification, also pulse voltage to be applied to the first threshold validation later is constant for each to verify the threshold set to increase by pulse height increment The nonvolatile semiconductor memory device according to claim Rukoto.
According to claim 8, wherein the pulse applying means, first in the nonvolatile semiconducting. Claim 8 to set such a pulse is applied before the threshold verification is two or more times, the pulse applying means a pulse applied to the first threshold validation and later, the nonvolatile semiconductor memory, wherein the set to be applied at least twice during the threshold verification and threshold verification
PCT/JP2003/001000 2003-01-31 2003-01-31 Nonvolatile semiconductor memory device WO2004068500A1 (en)

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