JP3975111B2 - Mixed modulator, oversampling D / A converter and A / D converter - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a modulator (mixed modulator), an oversampling D / A converter, and an A / D converter of a system in which Δ modulation and ΔΣ modulation are mixed.
[0002]
[Prior art]
Oversampling D / A converters and A / D converters convert at a sampling rate several tens to several hundreds times the frequency band of the input signal, drive the quantization noise to the high frequency side by signal processing, The analog interface circuit can perform high-resolution conversion, and is attracting attention as an optimum method for an analog-digital mixed system LSI whose scale is increasing.
[0003]
Modulation methods used in the signal processing section of oversampling D / A and A / D converters are Δ modulation (delta modulation), ΔΣ modulation (delta-sigma modulation), and a combination of these modulation methods. It has been known.
[0004]
Δ modulation is differential pulse code modulation in which the difference between successive sample signals is a 1-bit code. Specifically, this is a feedback type modulation method that obtains a predicted value for an input signal and quantizes (modulates) the difference signal between the input signal and the predicted value. Noise can be reduced.
[0005]
In addition, ΔΣ modulation is a feedback modulation scheme that quantizes (modulates) a difference (quantization noise) between an input signal and an output signal (quantized signal). In this method, the noise component in the required signal band can be reduced by distributing the quantization noise to a high frequency band by oversampling.
[0006]
The mixed modulation employed in the present invention is a combination of the Δ modulation and the ΔΣ modulation, and is also referred to as interpolation modulation, and performs ΔΣ modulation on a difference signal between an input signal and a predicted value.
[0007]
Thus, mixed modulation has the best of both worlds. That is, since the quantization noise is driven to a high frequency range by ΔΣ modulation, the quantization noise power is small and the quantization noise power itself, which is an advantage of Δ modulation, is small.
[0008]
Therefore, when mixed modulation is used, a high-order and steep filter characteristic is added to the post-stage digital filter in the A / D converter and the post-filter in the analog signal output stage in the D / A converter. Therefore, it is possible to suppress the increase in circuit scale and power consumption.
[0009]
Hereinafter, an example of a mixed modulator and an oversampling A / D and D / A converter using the mixed modulator will be described.
[0010]
21A and 21B show the basic configuration of the mixed modulator. The difference between the modulator described in (a) and the modulator described in (b) is only the position of the adder 8b for ΔΣ modulation, and the processing content is substantially the same in either configuration. The same.
[0011]
Here, the configuration described in (a) will be described as an example.
[0012]
In FIG. 21A, reference numerals 5, 6, and 7 are delay units, reference numerals 8a, 8b, 8c, and 9 are adders, and reference numeral 2 is a quantizer. The inside of the quantizer 2 has a threshold value of ±. When a signal exceeding the threshold value of + is input, “+ Δ” is output, and “0” is input between the threshold values of + and −. When a signal less than the -threshold value is input, "-Δ" is output. “Δ” at this time is called a quantization step (or quantization step width).
[0013]
The system function in the block configuration shown in FIG. 21A is expressed as the following equation (1).
[0014]
Y = (1-Z ^-1 ) ((X + (1-Z ^-1 ) Q)) ...... (1)
Here, X represents an input signal, and Y represents an output signal. Q represents an error between the input signal and the output signal of the quantizer 2, that is, quantization noise.
[0015]
In this description, a first-order mixed modulation method is taken as an example. In FIG. 21A, first-order ΔΣ modulation and first-order Δ modulation are mixed.
[0016]
The output of the adder 9 in FIG. 21A is an output of a prediction value for Δ modulation, and therefore 11 is a prediction integrator. Each delay unit delays the input signal by a delay clock for a predetermined time.
[0017]
The predictive integrator 11 adds one of the values “+ Δ”, “0”, and “−Δ”, while the integrator 10 including the delay unit 5 and the adder 8c is “input signal-predicted”. Value minus the value after one delay of the quantizer output, that is, the output of the adder 8b shown in FIG.
[0018]
The mixed modulator integrates the output of the quantizer 2 with the prediction integrator 11 to generate a prediction signal, and "input signal-predicted value-quantized value after one delay", that is, FIG. Feedback is made to the adders 8a, 8b and 9 so that the output of the adder 8b shown in a) is minimized. The effect of this is equivalent to performing ΔΣ modulation on the difference signal between the input signal and the predicted value.
[0019]
As is clear from the system function of the above equation (1), the output of the mixed modulator is a differential code as in the case of Δ modulation. The difference between this difference code and the difference code of Δ modulation is that the difference code of Δ modulation simply represents the difference between the input signal and the predicted value, whereas the difference code of mixed modulation was generated by Δ modulation. The difference code is a code obtained by further ΔΣ modulation.
[0020]
As described above, the oversampling A / D and D / A converters convert at a sampling rate several tens to several hundreds times the input signal frequency band. Due to the effect of this oversampling, the quantization noise is diffused up to a high frequency range. Therefore, if attention is paid only to the input signal frequency band, it is equivalent to a reduction in quantization noise power.
[0021]
When a mixed modulator is used, the advantage of Δ modulation and ΔΣ modulation is added to the effect of oversampling, and the quantization noise can be made extremely small more effectively.
[0022]
Also in the A / D converter, similarly, the quantization noise power can be extremely reduced, and this makes it possible to reduce the level of analog characteristics or the like required for the constituent circuits.
[0023]
As described above, the mixed modulator can be easily realized as a modulator used in an oversampling A / D or D / A converter, and can perform high-resolution conversion using a low-bit analog interface circuit. Is possible.
[0024]
[Problems to be solved by the invention]
However, the conventional mixed-type modulator has the advantages of Δ modulation and ΔΣ modulation, and at the same time, does not cause “slope overload” of the Δ modulation unit that is a component thereof, that is, “input signal step width” Is not equal to or smaller than the quantization step (quantization step width) Δ output by the quantizer ”, the mutual integration results between the predictive integrator of the Δ modulator and the integrator of the ΔΣ modulator Since this calculation process appears at the output via the regenerative integrator, noise and distortion are generated, and in addition, the output is not stable during this calculation period and the settling time is increased. Has the disadvantages.
[0025]
In other words, the mixed modulator has two loops (a majority of the components are shared) of a feedback loop of Δ modulation and a feedback loop of ΔΣ modulation, and if the input change is too large, Δ The predicted value in the modulation cannot follow, and the difference between the input signal and the predicted value greatly exceeds the quantization step width (determines the tracking capability of the feedback loop). When such a situation occurs, one feedback loop tries to converge forcibly, and the other feedback loop is out of the convergence condition, and conversely, the other is out of the convergence condition when trying to converge. Since the phenomenon is repeated, settling is delayed.
[0026]
This phenomenon will be described with reference to FIGS.
[0027]
In FIG. 21A, the output of the predictive integrator 11 is point A, and the point where the difference between the input signal and the predicted value appears, that is, the output of the adder 8a is point B. Also, the point after the delay of the output of the quantizer 2 is subtracted from the point B, that is, the output of the adder 8b is the point C, the output of the integrator 10 is the point D, and the output of the quantizer, The output of the mixed modulator is point E.
[0028]
That is, the result of integrating the previous E point is the A point, the result of subtracting the A point from the input signal is the B point, and the result of subtracting the previous E point from the B point is the C point. The result of integrating the C point is the D point.
[0029]
The quantizer 2 outputs “Δ” if the D point is “Δ / 2” or more, outputs 0 if it is within the range of “± Δ / 2”, and is less than “−Δ / 2”. If there is, “−Δ” is output. The timing diagram of FIG. 22 shows how each point changes when a signal five times the quantization step “Δ” of the input signal is input. In the initial state, each point shows zero.
[0030]
In FIG. 22, for convenience, Δ is omitted and the numerical values are drawn. That is, in FIG. 22, for example, a numerical value “5” means “5Δ”. In FIG. 22, when an input signal of “5Δ” is input at time T1, first, since the previous E point is “0”, the A point is also “0”, so the B point, the C point, Point D indicates “5Δ”.
[0031]
Since the point D is 10 times larger than the threshold value Δ / 2, the point E indicates “Δ”. At the next clock, point A becomes Δ, therefore point B becomes “4Δ”, point C becomes “3Δ”, and point D adds “5Δ” which is the value of the previous point D to become “8Δ”. At time T6, point A first becomes “5Δ”, which is equal to the input signal and point B becomes “0”, but point D at the same time greatly increases to “10Δ”, which greatly exceeds the input signal “5Δ”. Yes. Therefore, the point E previously outputs “Δ”.
[0032]
The convergence conditions in this example are “5Δ” at point A and “0” at points B, C, D, and E. At time T9, point D shows Δ closest to the convergence point of the first time, but point A at that time is “8Δ”, point B is “−3Δ”, and point C is “−4Δ”. In this example, it finally converges at T27.
[0033]
The “tilt overload” phenomenon of Δ modulation generally referred to is only the movement of the point A in the present description, and converges when the point A reaches 5Δ for the first time. Since there is the integrator 10 of the ΔΣ modulation section which is the other component, the calculation time until convergence is very long compared to only Δ modulation.
[0034]
The output signal of this calculation process appears as a ringing waveform after passing through the regeneration integrator, passing through the convergence point many times. The change in the signal level at point A is shown on the lower side of FIG. It can be seen that large ringing occurs. Here, ringing is caused by a P portion surrounded by a dotted line (a portion in which an excessive signal accumulated in the integrator 10 is reduced by time T6).
[0035]
In this description, 5Δ, which is an integer multiple of Δ, is used as an input signal. However, in practice, a signal unrelated to Δ is input, and the calculation time is further increased. In addition, as the input signal step increases, the calculation time required for convergence increases and the ringing waveform increases greatly. The ringing described above is the cause of the increase in the settling time and is a problem of the conventional mixed modulator.
[0036]
That is, when a step waveform as shown in FIG. 23A is input to the D / A converter, as shown in FIG. 23B, ringing occurs at times t0 to t1 (this is settling time ST). Exists. Therefore, the output of the D / A converter cannot actually be used unless it is after time t1. If the settling time (ST) is long, an extra waiting time is increased and signal processing is delayed.
[0037]
The present invention has been made to solve such problems. In an oversampling A / D and D / A converter using a mixed modulator, a slope overload of the Δ modulator is caused. Even when a large step is input as an input signal, the object is to suppress the occurrence of ringing and shorten the settling time.
[0038]
[Means for Solving the Problems]
The mixed modulator according to the present invention has switch means for separating a portion for executing ΔΣ modulation and control means for controlling switching of the switch means. As a result, the mixed modulator can be instantaneously changed to a Δ modulator.
[0039]
For example, when the amount of change in the input signal exceeds a predetermined allowable range, the control unit controls the switch unit to cut off the portion that performs ΔΣ modulation and suppresses the occurrence of ringing, so that ringing does not occur (at least ringing does not occur). When the possibility of occurrence is low), the above-mentioned disconnection is released and the mixed modulator is restored.
[0040]
According to one aspect of the mixed modulator of the present invention, the amount of change per clock of the input signal is monitored, and when the amount of change is large, the ΔΣ modulator is used in a short period immediately after the input signal is input. By stopping the integrator function and stopping the feedback of the output signal one clock before the quantizer, only the Δ modulation operation is performed, and the difference between the input signal and the predicted value is the step width of the quantizer. If it falls within the range, a mixed modulation operation in which Δ modulation and ΔΣ modulation are mixed is performed.
[0041]
That is, in the first stage Δ modulation, when the difference between the input signal and the predicted value exceeds the quantization step width Δ, a Δ modulation circuit is configured, and the predicted value is the quantization step width Δ for each input signal. Approaching. When the difference between the input signal and the predicted value falls below the quantization step width Δ, the original circuit (mixed modulation circuit of Δ modulation and ΔΣ modulation) is formed. Therefore, even when an input change exceeding the quantization step width Δ is given, there will be no additional subtraction between the integrator of the ΔΣ modulator and the prediction integrator, and ringing will continue for a long time. do not do.
[0042]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1A shows the configuration of the Δ modulator, and FIG. 1B shows the configuration of the ΔΣ modulator. Each modulator has an adder 90, a quantizer 100, and a delay device 200 for one clock. However, the Δ modulator has a prediction filter 300 as an integrator, whereas the ΔΣ modulator has a noise shape filter 400.
[0043]
FIG. 1C shows the configuration of the mixed modulator. In the figure, reference numeral 91 is an adder. FIG. 1D shows the basic configuration of the mixed modulator according to the present invention.
[0044]
As shown in FIG. 1 (d), the mixed modulator of the present invention includes a difference determiner (control means) 500 and two switches SW1 (switches for substantially disconnecting the noise shape filter 400 from the circuit). ) And SW2 (switches for cutting the feedback path of the ΔΣ modulator).
[0045]
When the difference determination unit 500 detects that the difference exceeds a threshold value (predetermined allowable range), the switch SW1 is switched to the a terminal side, and the switch SW2 is opened. Thereby, the mixed modulator shown in FIG. 1D is changed to a Δ modulator shown in FIG.
[0046]
Therefore, even when a large step that causes a gradient overload of the Δ modulation unit, which is a drawback of the conventional mixed modulator, is input as an input signal, for example, since it switches to the Δ modulation circuit after one clock of the oversampling clock, No ringing occurs. Therefore, the settling time can be shortened.
[0047]
Since the output of the mixed modulator is a differential output, in actual use, it is necessary to provide the regeneration integrator 13 in the subsequent stage as shown in FIG. FIG. 20 is a configuration example of a D / A converter. As shown in the figure, it comprises a mixed modulator 12, a regenerative integrator 13, a DA converter 23, and a post filter 24.
[0048]
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
[0049]
(Embodiment 1)
FIG. 2 is a block diagram showing the configuration of the mixed modulator of the present invention.
[0050]
In the figure, reference numeral 2 is a quantizer, reference numerals 3a and 3b are selectors, reference numeral 1 is a difference determination unit for determining a difference between an input signal and a predicted value, reference numerals 4, 5, 6, and 7 are delay units, Reference numerals 8a, 8b, 8c, and 9 are adders. Reference numeral 10 is an integrator of the ΔΣ modulation unit, and reference numeral 11 is a prediction integrator of the Δ modulation unit.
[0051]
The adder 8a outputs the difference between the input signal and the output of the prediction integrator 11. The output of the adder 8a is input to the difference determiner 1, and the difference determiner 1 determines whether or not the input difference amount exceeds the threshold value Δ of the quantizer 2, and the selector 3a and the selector 3b. It has a function to control.
[0052]
The difference determiner 1 is a determiner that detects an excessive input, and also functions as a controller that controls the selector. That is, the determination output of the difference determiner 1 is directly input to the selectors 3a and 3b, and switching of the selectors 3a and 3b is controlled by the signal.
[0053]
FIG. 3 shows the operation when a large step (in the example shown in FIG. 2, the initial value is zero, 5Δ is input, and −14Δ is subsequently input) is input as an input signal. Represents. In the figure, for convenience, Δ is omitted and a numerical value is drawn. For example, the numerical value “5” means “5Δ”. The omission of Δ is the same in FIGS. 6 and 9.
[0054]
As compared with FIG. 22 (operation of the conventional example), it is clear that the convergence is made in a very short time (see the behavior at the time of 5Δ input). That is, if there is an input of 5Δ at time T1, it immediately switches to the Δ modulation circuit at that time (T1), and thereafter the value at point A is incremented by Δ. And it converges at the time (T7) as early as possible.
[0055]
When −14Δ is input after 5Δ is input, the difference determination unit reads the change amount −19Δ of the input signal, switches to the Δ modulation circuit, and decreases the value of the prediction integrator by Δ.
[0056]
Despite the large input change amount of −19Δ, the convergence time is much faster than the operation of the conventional mixed modulator shown in FIG. 22 (at the time of 5Δ input), and the effect of preventing ringing is exhibited.
[0057]
The example shown in FIG. 3 is a special case where an integer multiple of the step width Δ of the quantizer is given as an input. In contrast, FIG. 4 shows a timing diagram close to actual use.
[0058]
FIG. 4 shows a timing chart when 5Δ + α is given to the circuit of FIG. 2 as an input signal. In FIG. 4, α <Δ / 2 is assumed, but it can be easily confirmed that there is no problem even if α> = Δ / 2 only by the difference in the output of the quantizer. Even when an input change of nΔ + α (n is an integer, α <Δ) is given to the modulator, it can be confirmed that the modulator operates normally.
[0059]
(Embodiment 2)
FIG. 5 shows another configuration example of the mixed modulator of the present invention. The difference between FIG. 1 and FIG. 5 is whether or not the output of the difference determiner is delayed by one clock. That is, in the present embodiment, unlike the previous embodiment, the output of the difference determiner is not delayed by one clock.
[0060]
A timing diagram showing the operation of the mixed modulator of FIG. 5 is shown in FIG. In the figure, for convenience, Δ is omitted and the numerical values are drawn.
[0061]
The mixed modulator shown in FIG. 5 excludes the delay of one clock of the output of the difference determiner.
[0062]
However, the example shown in FIG. 6 (FIG. 3) is a special case in which an integer multiple of the step width Δ of the quantizer is given as an input. On the other hand, a timing diagram close to actual use is shown in FIG. . Hereinafter, FIG. 4 and FIG. 7 are compared.
[0063]
As described above, FIG. 4 shows a timing chart when 5Δ + α is given as an input signal to the circuit of FIG. 2, and FIG. 7 shows a timing chart when 5Δ + α is given as an input signal to the circuit of FIG. Show.
[0064]
In FIGS. 4 and 7, α <Δ / 2 is assumed. However, it is easy to confirm that there is no problem even if α> = Δ / 2 only by the difference in the output of the quantizer. 7, it can be confirmed that the modulator of the present invention operates normally even when an input change of nΔ + α (n is an integer, α <Δ) is given.
[0065]
Comparing FIG. 4 and FIG. 7, it is possible to confirm the influence of the difference in the circuit configuration of FIG. 2 and FIG. 5 on the modulation operation.
[0066]
In both cases, Δ modulation operation is performed until time T5, but it can be seen that there is a difference in the value of point D at time T6.
[0067]
Specifically, in the circuit shown in FIG. 2, the point D is α at time T6, and in the circuit shown in FIG. 5, the point D is 2α at time T6.
[0068]
The behavior of point D after time T6 is still incremented by α in both circuits, and the circuit shown in FIG. 5 reaches the quantizer threshold earlier by one clock. That is, the circuit shown in FIG. 5 rises earlier by one clock than the circuit shown in FIG.
[0069]
The difference depending on the circuit configuration described above depends on how long the Δ modulation operation is continued. In the circuit of FIG. 2, the Δ modulation operation is continued until T6, and in the circuit of FIG. 5, the Δ modulation operation is completed at time T5.
[0070]
In the present invention, the greatest object is to prevent ringing, and Δ modulation operation is adopted as the means. From this point of view, it can be said that the circuit configuration of FIG. 5 is more suitable for the original purpose because the Δ modulation operation is completed one clock earlier.
[0071]
The advantages of the circuit of FIG. 5 over the circuit of FIG. 2 are that the above-described Δ modulation operation can be completed one clock earlier, that one delay device can be reduced, and the circuit scale can be reduced. is there.
[0072]
The difference determiner 1 has a very simple circuit configuration, and the amount of delay generated here is considered to be very small. Furthermore, since the output of the difference determiner 1 directly controls the selectors 3a and 3b, there is almost no delay amount from the difference determiner 1 to the selectors 3a and 3b.
[0073]
Therefore, it is considered that the delay device 4 is not particularly necessary, and FIG. 5 shows a circuit configured based on this idea. For these reasons, the circuit configuration of FIG. 5 is very useful.
[0074]
However, the circuit configuration of FIG. 2 may be advantageous. For example, when the operation clock is very fast, mis-latching may occur unless the synchronous design shown in FIG. 2 is adopted. In addition, since the shortening of the convergence time for one clock cannot provide a great effect, the circuit of FIG. 2 should be adopted.
[0075]
On the other hand, when the operation clock is relatively slow, the problem caused by the asynchronous circuit design does not occur as described above. In addition, since the effect of shortening the convergence time for one clock is large, there is an advantage of employing the circuit of FIG.
[0076]
As described above, the advantages of the mixed modulator of the present invention can be maximized by properly using the circuit configurations of FIGS.
[0077]
(Embodiment 3)
Next, a configuration example in which the mixed modulator of the present invention is further modified will be described with reference to FIG.
[0078]
FIG. 8 is greatly different from the above-described configuration example of the mixed modulator of the present invention. The differences from the circuit configurations shown in FIGS. 2 and 5 are the position and operation of the difference determiner 12 and the position of the adder 8c.
[0079]
The adder 8 c adds the value one clock before the quantizer 2 to the value of the prediction integrator 11. The adder 8a calculates the difference between the input signal and the output of the adder 8c, and the result is input to the integrator 10.
[0080]
The difference determiner 12 has a function of receiving the output of the adder 8a, determining whether or not it exceeds twice the step width Δ of the quantizer 2, and controlling the selector 3a and the selector 3b.
[0081]
FIG. 9 shows the operation when a large step (in the example shown in FIG. 8, initial value zero, 5Δ input, and subsequently −14Δ is input) is input as an input signal to the modulator of FIG. Represents. In FIG. 9, for convenience, Δ is omitted and a numerical value is drawn.
[0082]
In FIG. 9, as in FIG. 3, the convergence is made at times T7 and T28, and the effect of preventing ringing can be confirmed even in this circuit configuration.
[0083]
In this circuit configuration, the difference between the circuits shown in FIGS. 2 and 5 is that the threshold value of the difference determiner 12 is set to 2Δ.
[0084]
If this threshold is Δ, the circuit configuration of FIG. 8 does not operate normally. Before explaining this, the timing when a 5Δ + α input signal (initial value zero) is given to the circuit of FIG. 5 is shown in FIG. 10, and it will be explained that it operates also for nΔ + α input. .
[0085]
In FIG. 10, only the rising portion with respect to the input of 5Δ + α is shown. Since the determination at point C is performed with a threshold value of 2Δ, the mode is switched to the mixed modulation operation at time T6. The timing of switching from Δ modulation to mixed modulation is shifted backward by the same one clock as in the circuit configuration of FIG. 2 because the output of the difference determiner 12 is delayed by one clock.
[0086]
That is, it can be confirmed that the same effect as the circuit configuration shown in FIG. 2 is obtained and that prevention of ringing can be realized.
[0087]
If attention is paid only to the rising point, it seems that the threshold value of the difference determiner 12 operates normally even when the threshold value is Δ. However, when the threshold value is set to Δ, the mixed modulation operation is not normally performed. This is shown below.
[0088]
FIG. 11 is a continuation of the timing diagram shown in FIG. Here, description will be made assuming that the value of α is Δ / 8.
[0089]
Since the threshold value of the quantizer 2 is Δ / 2 and the point D at time T8 is Δ / 2, the quantizer 2 outputs Δ. As a result, both the points A and B are incremented by Δ, and the value of the point C at time T9 is −2Δ + α.
[0090]
Since the threshold value of the difference determiner 12 is 2Δ, the mixed modulation operation is continued without switching to the Δ modulation operation.
[0091]
FIG. 12 shows a timing chart when the threshold value of the difference determiner 12 is Δ. The portion corresponding to FIG. 10 at time T0 to T9 is omitted because there is no change, and the time from T6 to T15 is shown in the figure.
[0092]
Upon reception of the value C of point C at time T9, −2Δ + α, the difference determiner 12 outputs 1 and switches to the Δ modulation circuit at time T10. As a result, the value of the integrator 10 is cleared, and α is added again. At time T13, the point D reaches Δ / 2, and at time T15, the Δ modulation circuit is switched.
[0093]
Thereafter, since this series of operations is continued, a pulse occurs in the output signal every 5 clocks. Since the input signal has Δ / 8 as a fraction, a pulse is generated every 8 clocks. Therefore, when the threshold value of the difference determiner 12 is Δ, it is understood that the input signal does not operate normally.
[0094]
From the above, in the circuit configuration of FIG. 8, it is important to set the threshold value of the difference determiner 12. If the setting is appropriately performed, the same effects as those of the mixed modulator shown in FIGS. It is possible to obtain
[0095]
The advantages of this circuit configuration are as follows. Since the threshold value of the difference determiner 12 is 2Δ, the bit width of the input signal to the difference determiner 12 can be reduced.
Specifically, it is very useful in that the 1-bit input signal can be reduced and the circuit scale can be reduced with respect to the difference determiner 1 shown in FIGS. Circuit configuration.
[0096]
(Embodiment 4)
Next, a case where the mixed modulator of the present invention is applied to an oversampling D / A converter will be described.
[0097]
FIG. 13 is an example showing the configuration of an oversampling D / A converter using the mixed modulator of the present invention.
[0098]
As the mixed modulator of the present invention, for example, the modulator of FIG. 2 is applied. The circuit denoted by reference numeral 18 in FIG. 13 represents the mixed modulator shown in FIG. 2, wherein 13 is a reproduction integrator, 16 is a D / A converter, and 17 is a post filter for band limitation. .
[0099]
Since the output of the mixed modulator is a differential code as shown in equation (1) in the column of the prior art, a reproduction integrator 13 for reproducing a signal is necessary.
[0100]
The signal reproduced by the reproduction integrator 13 has a low quantization noise level due to the mixed modulation, and the quantization noise is distributed on the high band side due to the noise shaping effect.
[0101]
Therefore, the analog post filter 17 does not require a steep characteristic, quantization noise can be easily removed, and a highly accurate oversampling D / A converter can be realized.
[0102]
By using the mixed modulator shown in FIG. 2, the above-described highly accurate oversampling D / A converter can be realized on a small circuit scale, and the problem of settling time can be solved by preventing ringing. It is a very useful circuit.
[0103]
(Embodiment 5)
Next, the case where the mixed modulator of the present invention is applied to an oversampling A / D converter will be described.
[0104]
FIG. 14 shows an example of the configuration of an oversampling A / D converter using the mixed modulator of the present invention.
[0105]
As the mixed modulator of the present invention, for example, the modulator of FIG. 2 is applied. A circuit corresponding to the difference determiner 1 in FIG. 2 is the comparator 23 in FIG. 14, a latch circuit 24 that latches the comparison signal, and a determination circuit 25 configured by a digital logic circuit.
[0106]
The analog adder 21 in FIG. 14 has the same function as the adder 8a in FIG.
[0107]
The analog adder 22 in FIG. 14 has the same function as the adder 8c in FIG. The configurations of the quantizer 29 and the latch circuit 30 in FIG. 14 have the same functions as the quantizer 2 in FIG.
[0108]
The analog selector 28 in FIG. 14 has the same function as the selector 3a in FIG. The analog integrator 27 in FIG. 14 has the same function as the integrator 10 in FIG.
[0109]
2 and 14, the delay units 6 and 7, the adder 9, and the selector 3 b that are assigned the same reference numerals have the same function and perform the same operation.
[0110]
The D / A converters 20, 26, and 31 in FIG. 14 are necessary in three paths extending from digital to analog.
[0111]
The D / A converter 20 is a path from the prediction integrator 11 to the adder 8a in FIG. 2, and the D / A converter 26 is a path from the difference determiner 1 to the selectors 3a and 3b in FIG. The converter 31 is used in each path from the selector 3b to the adder 8c in FIG. Therefore, the mixed modulator of FIG. 14 is equivalent to the modulator of FIG.
[0112]
Therefore, even when a large step causing a gradient overload is input as an input signal, the occurrence of ringing is suppressed and the settling time is shortened.
[0113]
The A / D converter in FIG. 14 operates as follows.
[0114]
As shown in the figure, the path from the latch circuit 30 to the output of the adder 9, the path from the delay unit 7 to the output of the selector 3b, the reproducing integrator 13, and the digital filter 33 are all configured by digital circuits.
[0115]
On the other hand, all the input stages are composed of analog circuits.
[0116]
The analog signal input to the analog adder 21 passes through the analog adder 22 and the selector 28, is integrated by the analog integrator 27 (during the mixed modulation operation), and is simultaneously quantized to a digital signal by the quantizer 29. The latch circuit 30 latches the digital signal.
[0117]
The output of the adder 9 is returned to an analog signal by the D / A converter 20 and input to the analog adder 21 where it is subtracted from the analog signal. The output from the delay unit 7 is converted into an analog signal by the D / A converter 31 and subtracted from the analog signal by the analog adder 22.
[0118]
Since the output of the mixed modulator 32 is a differential code as described above, the quantization noise reproduced by the reproducing integrator 13, band-limited by the digital filter 33, and driven to the high frequency range by ΔΣ modulation is removed, and A A digital signal is obtained as an output of the / D converter.
[0119]
The quantization noise power can be extremely reduced by the effects of oversampling, Δ modulation, and ΔΣ modulation. Therefore, the resolution and analog characteristics required for the analog adders 21 and 22, the analog integrator 27, the quantizer 29, and the D / A converters 20, 26, and 31 as the sources of quantization noise are reduced. Can do. As described above, since the mixed modulator according to the present invention is used, there is an effect that ringing can be suppressed even when an input that causes a gradient overload is input.
[0120]
(Embodiment 6)
Next, a configuration example different from that in FIG. 14 when the mixed modulator of the present invention is applied to an oversampling A / D converter will be described.
[0121]
FIG. 15 shows an example of the configuration of an oversampling A / D converter using the mixed modulator of the present invention.
[0122]
As the mixed modulator of the present invention, the modulator of FIG. 8 is applied. A circuit corresponding to the difference determiner 12 in FIG. 8 is the comparator 23 in FIG. 15, a latch circuit 24 for latching the comparison signal, and a determination circuit 25 configured by a digital logic circuit. The circuit corresponding to the delay device 4 in FIG. 8 has the function of the latch circuit 24 in FIG.
[0123]
8 and 15, circuits having the same reference numerals have the same functions and perform the same operations.
[0124]
14 differs from FIG. 15 in that an adder 8c is used in FIG. 15 instead of the analog adder 22 in FIG. 14, and that the D / A converter 31 in FIG. 14 is not required in FIG. There is a point.
[0125]
This has the advantage of the configuration of the mixed modulator shown in FIG. Specifically, since the path from digital to analog is one less than in FIG. 14, the number of D / A converters can be reduced by one, and the analog adder is replaced with a digital adder. Can do.
[0126]
Therefore, the error reduction by the analog circuit is easier to realize than the circuit shown in FIG. This makes it possible to realize an A / D converter with higher accuracy and a smaller area.
[0127]
(Embodiment 7)
Next, a configuration example different from that in FIG. 14 when the mixed modulator of the present invention is applied to an oversampling A / D converter will be described.
[0128]
FIG. 16 is an example showing the configuration of an oversampling A / D converter using the mixed modulator of the present invention.
[0129]
In the present embodiment, for example, a modulator having the configuration shown in FIG. 8 is used as the mixed modulator. A circuit corresponding to the difference determiner 12 in FIG. 8 is the comparator 23 and the delay circuit 39 in FIG.
[0130]
The circuit corresponding to the quantizer 2 in FIG. 8 is the quantizer 29 and the delay circuit 40 in FIG.
[0131]
Circuits corresponding to the adders 8a, 8c, and 9 in FIG. 8 are the analog adders 21, 34, and 36 in FIG. A circuit corresponding to the delay device 4 in FIG. 8 is the delay circuit 39 in FIG. Further, the circuits corresponding to the delay devices 6 and 7 in FIG. 8 are the latch circuit 35 and the delay circuit 37 in FIG.
[0132]
A circuit corresponding to the integrator 10 in FIG. 8 is the analog integrator 27 in FIG. 16. Circuits corresponding to the selectors 3a and 3b in FIG. 8 are the selectors 28 and 38 in FIG. 16, respectively.
[0133]
The mixed modulation circuit shown in FIG. 8 corresponds to the mixed modulator 42 constituted by the analog circuit in FIG.
[0134]
The operation of the mixed modulator 42 in FIG. 16 is the same as that of the mixed modulator shown in FIG. 8. The output is latched by the latch circuit 43 constituted by a digital circuit, and the differential code is passed through the reproduction integrator 13. , And the digital filter 33 cuts quantization noise and noise generated on the analog circuit, so that an accurate A / D converter can be configured.
[0135]
The advantage of this circuit configuration is that all circuit elements are realized in analog, so there is no need to use a C-MOS process, and it can be realized with bipolar, etc. In addition, the mixed type has the effect of suppressing ringing. A modulator can be realized.
[0136]
As described above, the mixed-type modulator of the present invention and the oversampling D / A and A / D converters using the mixed-type modulator of the present invention can be easily realized to achieve the above-described object, and It has been shown to work effectively.
[0137]
The mixed modulator of the present invention can be used, for example, in an AFC circuit in a mobile terminal for mobile communication as shown in FIG.
[0138]
As described above, what the present invention assumes as an input signal is a signal that does not change for a certain period of time as shown in FIG. That is, it is not a signal that changes in real time.
[0139]
For example, in a CDMA AFC circuit (an automatic frequency control circuit for synchronizing the oscillation clock of a local oscillator on the receiving side with a transmitted carrier wave), feedback control of AFC is performed at a predetermined cycle. The input signal is held for a predetermined time. Further, since the amplitude of the signal received by the antenna changes greatly due to the influence of fading, there is always a possibility that the input will be excessive during A / D conversion and D / A conversion.
[0140]
Therefore, it can be said that the AFC circuit is a circuit suitable for applying an A / D converter or a D / A converter using the mixed modulator of the present invention.
[0141]
In FIG. 17, in mobile terminal 600, a CDMA signal received by antenna 601 is amplified by amplifier 602 and input to mixer 604 via bandpass filter 603.
[0142]
The mixer 604 multiplies the local oscillation signal (LO) output from the local oscillation circuit (VCO) 615, and converts the frequency of the received signal. Then, the frequency-converted signal is input to the baseband conversion circuit 606 via the bandpass filter 605 and becomes a baseband signal.
[0143]
The synchronous clock detection circuit 607 extracts a synchronous clock included in the baseband signal. The extracted synchronous clock is frequency-divided by a frequency divider 608, and the frequency-divided clock signal is input to an AFC (automatic frequency control circuit) 609. The AFC circuit 609 includes the D / A converter 610 and the A / D converter 611 of the present invention.
[0144]
The AFC circuit 609 compares the clock signal divided by the frequency divider 608 with the clock signal obtained by dividing the oscillation clock of the temperature compensated crystal oscillator (TCXO) 612 by the frequency divider 613, and the frequency divider 613. Are synchronized with the output signal of the frequency divider 608. The output of the frequency divider 613 is input to the PLL circuit 614. The PLL circuit 614 functions to synchronize the oscillation output (local oscillation signal LO) of the local oscillator (VCO) 615 with the output clock of the frequency divider 613.
[0145]
In the CDMA receiver, it is necessary to synchronize the oscillation output of the local oscillator with the carrier wave transmitted with extremely high accuracy. When the present invention is applied to an AFC circuit, an extremely high precision conversion output can be obtained using a relatively inexpensive A / D converter and D / A converter with a low number of bits, and there is an excessive input. Even in the case of settling, the settling time does not increase and the usability is improved.
[0146]
FIG. 18 shows a modified example of the present invention. In this example, in the mixed modulator, a switch SW3 is provided in addition to the switches SW1 and SW2, and these switches are controlled by the control unit 700.
[0147]
As described with reference to FIG. 1, when the switches SW1 and SW2 are switched, the state changes to a Δ modulator, and when the switch SW3 is switched, the state changes to a ΔΣ modulator.
[0148]
In this way, by independently controlling the built-in switches, the Δ modulator and the ΔΣ modulator can be individually separated from the mixed modulator. Therefore, it is possible to determine which modulator is used in accordance with the application and use conditions.
[0149]
【The invention's effect】
As described above, according to the present invention, in an oversampling D / A and A / D converter using a mixed modulator, a large step for causing the “tilt overload” of the Δ modulator is an input signal. Even when it is input, the occurrence of ringing can be suppressed and the settling time can be shortened.
[0150]
The configuration of the mixed modulator of the present invention can be realized only by adding very few circuit elements, and can be said to be very effective in an analog / digital mixed system LSI whose scale is increasing.
[Brief description of the drawings]
FIG. 1A is a diagram showing a configuration of a Δ modulator.
(B) Diagram showing the configuration of the ΔΣ modulator
(C) Diagram showing the configuration of a mixed modulator
(D) The figure for demonstrating the characteristic of the mixed modulator of this invention
FIG. 2 is a block diagram showing a configuration of an example of a mixed modulator according to the present invention.
FIG. 3 is a timing diagram showing an operation when an excessive input and an integer multiple of Δ are applied to the mixed modulator of FIG. 2;
4 is a timing chart showing an operation when an input that is excessive and is not an integral multiple of Δ is applied to the mixed modulator of FIG. 2;
FIG. 5 is a block diagram showing a configuration of another example of the mixed modulator according to the present invention (a configuration in which the output of the difference determiner is supplied to the selector without passing through the delay device);
6 is a timing diagram showing an operation when an input that is excessive and an integer multiple of Δ is applied to the mixed modulator of FIG. 5;
7 is a timing chart showing an operation when an input that is excessive and is not an integral multiple of Δ is applied to the mixed modulator of FIG. 5;
FIG. 8 is a block diagram showing a configuration of another example of the mixed modulator of the present invention (a configuration in which the scale of the difference determiner is reduced);
FIG. 9 is a timing chart showing an operation when an input that is excessive and an integer multiple of Δ is applied to the mixed modulator of FIG. 8;
FIG. 10 is a timing chart (time T0 to T9) showing an operation when an input that is excessive and is not an integral multiple of Δ is given to the mixed modulator of FIG.
11 is a timing chart showing the operation when an input that is excessive and is not an integral multiple of Δ is given to the mixed modulator of FIG. 8 (time T6 to T15).
12 is a timing chart (time T6 to T15) showing an operation when the output of the difference determiner of the mixed modulator in FIG. 8 is set to Δ and an input that is excessive and is not an integral multiple of Δ is given.
FIG. 13 is a block diagram showing an example of the overall configuration of an oversampling D / A converter using the mixed modulator of the present invention.
FIG. 14 is a block diagram showing an example of the overall configuration of an oversampling A / D converter using the mixed modulator of the present invention.
FIG. 15 is a block diagram showing a configuration of another example of an oversampling A / D converter using the mixed modulator of the present invention.
FIG. 16 is a block diagram showing the configuration of an oversampling A / D converter in which all the mixed modulators of the present invention are realized using analog circuits.
FIG. 17 is a block diagram showing the configuration of an A / D converter using a mixed modulator of the present invention and a CDMA receiver equipped with the D / A converter.
FIG. 18 is a block diagram showing a configuration of a modification of the mixed modulator of the present invention.
FIG. 19 is a block diagram showing a circuit in which a mixed modulator and a reproduction integrator are combined.
FIG. 20 is a block diagram showing a configuration of an oversampling D / A converter using a mixed modulator.
FIG. 21A is a block diagram showing a configuration of an example of a conventional mixed modulator.
(B) The block diagram which shows the structure of the other example of the conventional mixed modulator.
FIG. 22 is a timing diagram showing changes in the state of each part until the output signal converges when there is an excessive input to the conventional mixed modulator;
FIG. 23A is a diagram illustrating an example of an input signal of a mixed modulator;
(B) A diagram showing how ringing occurs in the output of the mixed modulator when an excessive signal is input.
[Explanation of symbols]
1 Difference discriminator
2 Quantizer
3a, 3b Selector for stopping the function of the integrator of the ΔΣ modulator
4 Delay unit for delaying the output of the difference judgment unit
5, 6, 7 delay device
8a, 8b, 8c, 9 Adder (subtracter; computing unit)
10 Integrator of ΔΣ modulator
11 Predictive integrator
13 Regenerative integrator
90,91 adder
100 Quantizer
200 delay device
300 Prediction filter
400 Noise shape filter
500 Difference judger
SW1, SW2 Switch for separating the part that executes ΔΣ modulation

Claims (9)

It is a mixed type modulator that mixes Δ modulation and ΔΣ modulation,
Switch means for separating the portion that performs the ΔΣ modulation;
Control means for controlling the switching of the switch means ,
When the change amount of the input signal exceeds a predetermined allowable range, the control means controls the switch means to cut off a portion of the mixed modulator that performs the ΔΣ modulation, and switches to Δ modulation. A mixed modulator. In claim 1,
When the amount of change in the input signal exceeds a predetermined allowable range, the control means controls the switch means to disconnect the part that executes the ΔΣ modulation, and then releases the disconnection. Modulator. A modulator that mixes Δ modulation and ΔΣ modulation, performs a process of performing ΔΣ modulation on a differential signal between an input signal and a prediction signal, or a process substantially equivalent to this,
A prediction signal generator that integrates a result of ΔΣ modulation of a difference signal between the input signal and the prediction signal to generate the prediction signal;
A quantizer capable of changing an output value in a positive direction or a negative direction by a quantization step width per clock;
At least one computing unit for obtaining a difference between the difference signal between the input signal and the prediction signal and the output signal of the quantizer;
An integrator for integrating the difference between the difference signal between the input signal and the prediction signal and the output signal of the quantizer;
A first selector for stopping the function of the integrator;
A second selector for prohibiting feedback of the output signal one clock before the quantizer;
Selector control means for controlling the first and second selectors,
The selector control means includes
When the amount of change per clock of the input signal exceeds a predetermined allowable amount, the first selector is switched to stop the function of the integrator, and the second selector is switched to switch the quantum When the feedback of the output signal one clock before the quantizer is stopped and the difference between the input signal and the prediction signal falls within the step width of the quantizer, the first and second selectors are returned to the original A mixed modulator characterized by returning to a state. In claim 3,
The selector control means whether or not the amount of change per clock of the input signal exceeds the step width of the quantizer, or exceeds an integer multiple of the step width of the quantizer; A mixed type modulator characterized by: An oversampling D / A converter using the mixed modulator according to any one of claims 1 to 4. The mixed modulator according to any one of claims 1 to 4, a reproducing integrator for regenerating a signal by integrating an output signal of the modulator, and a D / D provided at a subsequent stage of the integrator An oversampling D / A converter comprising: an A converter; and an analog filter for limiting a band of an output signal of the D / A converter. 5. A mixing device comprising an analog circuit as an input interface of the mixed modulator on the assumption that an analog signal is input to the mixed modulator according to claim 1. Type modulator. An oversampling A / D converter using the mixed modulator according to claim 7. 8. An overmodulator comprising: the mixed modulator according to claim 7; an integrator for integrating an output signal of the modulator; and a signal band limiting digital filter provided at a subsequent stage of the integrator. Sampling type A / D converter.

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