JP3970068B2 - Imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus that performs color imaging using a solid-state imaging device with a color filter mounted thereon.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a digital camera is known as an imaging device using a CCD (Charge Coupled Device) image sensor as an imaging device. In such a digital camera, an imaging mode generally called a monitor mode is set. This monitor mode is a mode for determining a subject while viewing an image displayed on the display screen, and does not require a much higher resolution than when capturing a still image recorded in a built-in memory. In recent years, a digital camera mounted on a mobile phone, for example, that can be handled as a simple digital camera at the destination has become widespread. In such a digital camera, the resolution is less important than the monitor mode of a normal digital camera because the display screen is relatively smaller than that of a normal digital camera. In such a digital camera, rather, there is a strong demand for being small and inexpensive.
[0003]
FIG. 4 is a block diagram illustrating a schematic configuration of a conventional imaging apparatus. The imaging apparatus shown here includes a CCD image sensor (solid-state imaging device) 1, a CCD driver circuit 2, a timing control circuit 3, an analog signal processing circuit 4, an A / D conversion circuit 5, and a digital signal processing circuit 6.
[0004]
The solid-state imaging device 1 includes a light receiving region having a plurality of light receiving pixels arranged in a matrix. Each light receiving pixel receives light incident on the light receiving surface and generates information charges by photoelectric conversion. In the solid-state imaging device 1, this information charge is accumulated in each light receiving pixel during the accumulation period, and then sequentially transferred through a plurality of shift registers. Then, it is converted into a voltage value by an output unit provided at the final stage of the transfer path, and is output as an image signal Y0 (t). As described above, there are several types of solid-state imaging devices that sequentially transfer accumulated information charges and output image signals, which have different transfer methods. As these types, a frame transfer type that collectively transfers information charges accumulated in the imaging unit to the accumulation unit, an interline type that transfers information charges to a vertical transfer unit arranged between each column of light receiving pixels, and a frame There is a frame interline type that has the characteristics of both transfer type and interline type.
[0005]
The CCD driver circuit 2 generates a plurality of clock pulses synchronized with a vertical synchronization signal VT and a horizontal synchronization signal HT supplied from a timing control circuit 3 described later. Then, the generated plurality of clock pulses are supplied to the solid-state imaging device 1, and the solid-state imaging device 1 is driven to sequentially transfer the information charges accumulated in the plurality of light receiving pixels.
[0006]
The analog signal processing circuit 3 performs analog signals such as CDS (Correlated Double Sampling) and AGC (Automatic Gain Control) on the image signal Y0 (t) output from the solid-state imaging device 1. Processing is performed to generate an image signal Y1 (t). The A / D conversion circuit 4 normalizes the image signal Y1 (t) in synchronization with the operation timing of the solid-state imaging device 1, converts it to a digital signal, and outputs it as image data Y0 (n).
[0007]
The digital signal processing circuit 5 performs digital signal processing such as color separation and matrix calculation on the image data Y0 (n) output from the A / D conversion circuit 4 to obtain image data Y1 (including luminance data and color difference data). n).
[0008]
The timing control circuit 6 counts the reference clock CK to generate the vertical synchronization signal VT and the horizontal synchronization signal HT, and determines the vertical scanning and horizontal scanning periods of the solid-state imaging device 1. For example, in accordance with the NTSC system, the horizontal synchronizing signal HT is generated by dividing the reference clock CK having a frequency four times the frequency 3.58 MHz of the color subcarrier used in the signal processing into 1/910. Further, the horizontal synchronizing signal HT is divided by 2/525 to generate a vertical synchronizing signal VT.
[0009]
In such an imaging apparatus that obtains image data by performing various signal processing on the image signal output from the solid-state imaging device, so-called exposure control is performed to adjust the information charge accumulation period according to the illuminance of the subject. Is called. As this exposure control means, there is one that performs expansion / contraction control of the accumulation period in accordance with the illuminance measured by the photometric sensor, or one that performs expansion / contraction control of the accumulation period by referring to the integral value of the previous image information. is there. For example, in the latter case, the accumulation time of the solid-state imaging device 1 is shortened when the integral value of the image data exceeds the proper range, and conversely, the accumulation time is lengthened when the integral value falls below the proper range. Perform feedback control. Thereby, the illuminance range of the solid-state imaging device 1 is expanded, and appropriate image information according to the illuminance of the subject can be obtained. Then, as a means for further expanding the illuminance range when the above-described exposure control means cannot be used to solve the shortage of exposure, there is a technique for synthesizing the information charges obtained in the respective light receiving pixels. In this case, when the illuminance of the subject is low and sufficient information charges cannot be obtained, the information charges in the vicinity are mixed together to extract a plurality of pixels, thereby compensating for the shortage of image information. . According to such means, it is possible to obtain a sufficient level of image information without underexposure even for a dark subject.
[0010]
[Problems to be solved by the invention]
In the imaging apparatus as described above, when performing color imaging, a color filter is attached to the light receiving surface of the solid-state imaging device. In this color filter, each of the three primary colors or their complementary colors are regularly arranged in a predetermined order, and each segment thereof is assigned to each light receiving pixel of the solid-state imaging device. For example, in the case of a mosaic type color filter, as shown in FIG. 5, green (G) and red (R) are alternately arranged in odd-numbered segments, and G and blue (B) are arranged in even-numbered segments. Is done. In such a color filter, two adjacent segments correspond to colors different from each other. Therefore, when information charges are combined, inconvenience may occur in color reproducibility. An imaging apparatus as a solution to this problem has been proposed by the present applicant in Japanese Patent Laid-Open No. 8-154253. This provides a difference in the number of bits between the odd-numbered columns and the even-numbered columns of the vertical transfer unit, and alternately outputs the information charges obtained at the odd-numbered columns and the information charges obtained at the even-numbered columns to the horizontal transfer unit. The information charges corresponding to the same color component are made continuous. However, in such an image pickup apparatus, there is a problem that it is necessary to change the device structure of the solid-state image pickup element, and it is impossible to avoid an increase in manufacturing cost associated therewith. In particular, it is completely unsuitable for an object such as an image pickup apparatus that picks up an image to be displayed on a relatively small display screen for the purpose of providing at a low price without requiring much resolution.
[0011]
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an imaging apparatus capable of improving the sensitivity while preventing an increase in cost even for color imaging using a mosaic color filter.
[0012]
[Means for Solving the Problems]
The present invention has been made in view of the above-described problems, and is characterized in that a color filter is attached to a plurality of light receiving pixels arranged in a matrix, and a vertical transfer unit is provided in each column of the plurality of light receiving pixels. The solid-state imaging device in which each output of the vertical transfer unit is connected to each bit of the horizontal transfer unit and the output unit is disposed on the output side of the horizontal transfer unit, and the plurality of light receiving pixels. The stored information charges are taken into the plurality of vertical transfer units and transferred to the horizontal transfer unit, then transferred to the output unit by the horizontal transfer unit, and an output corresponding to the accumulated charge amount is obtained at the output unit. And a drive circuit that resets the accumulated charge and a signal processing circuit that performs predetermined signal processing on the image signal output from the solid-state imaging device, and the drive circuit performs reset operation of the output unit. The period It is set to an integral multiple of the period of the transfer operation of the flat transfer unit, the information charges indicating the first and second color components are combined to generate a first combined image signal, and the second and third colors The information charge indicating the component is combined to generate a second combined image signal, and the signal processing circuit generates a first color component signal that approximately represents the first color component from the first combined image signal. And a third color component signal that approximately represents the third color component from the second composite image signal, and further, the second color image from the first and second composite image signals. Is to generate a second color component signal that approximately represents the color component.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block configuration diagram showing a schematic configuration of an imaging apparatus according to the present invention, and FIGS. 2 and 3 are timing diagrams showing the operation thereof. The imaging apparatus shown in FIG. 1 includes a solid-state imaging device 11, a CCD driver circuit 12, a timing control circuit 13, a frequency dividing circuit 14, an analog signal processing circuit 15, an A / D conversion circuit 16, and a digital signal processing circuit 17. .
[0014]
The solid-state imaging device 11 is, for example, a frame transfer type, and includes an imaging unit 11i, a storage unit 11s, a horizontal transfer unit 11h, and an output unit 11d. The imaging unit 11i includes a plurality of vertical shift registers, and each bit of the vertical shift registers forms each light receiving pixel, and the plurality of light receiving pixels are arranged in a matrix. A color filter for color imaging is mounted on the surface of the imaging unit 11i, and each segment of the color filter is associated with each of a plurality of light receiving pixels. For example, when this color filter is a mosaic type color filter as shown in FIG. 5, green (G) and red (R) are alternately associated with odd rows of a plurality of light receiving pixels arranged in a matrix. G and blue (B) are alternately associated in even rows. In addition, in the imaging unit 11i, an area called a so-called OPB (Optical Black) area is set by shielding some columns of the plurality of vertical shift registers, and an image is obtained based on information charges obtained in this area. The black level of information is determined.
[0015]
The storage unit 11s is composed of a plurality of vertical shift registers that are continuous with the plurality of vertical shift registers that constitute the imaging unit 11i, and is set to the same number of bits as that of the plurality of vertical shift registers that constitute the imaging unit 11i. The The horizontal transfer unit 11h is composed of a single horizontal shift register arranged on the output side of the storage unit 11s, and is connected so that each output of a plurality of vertical shift registers constituting the storage unit 11s is associated with each bit. The The output unit 11d is disposed on the output side of the horizontal transfer unit 11h, and includes a capacitor that takes in information charges output from the water transfer unit 11h. The output unit 11d sequentially converts the information charge taken into the capacitor into a voltage value according to the charge amount, and outputs it as an image signal Y0 (t).
[0016]
The frame transfer type solid-state imaging device 11 having these configurations includes a horizontal overflow drain (LOD) structure and a vertical overflow drain (VOD) structure. Regardless of the type, the information charges accumulated in the imaging unit 11i can be discharged, and the information charge accumulation state in the imaging unit 11i is reset by the discharge of the information charges.
[0017]
The CCD driver circuit 12 includes a B-clock generator 12b, an F-clock generator 12f, a V-clock generator 12v, an H-clock generator 12h, an R-clock generator 12r, and an S-clock generator 12s. The
[0018]
The B-clock generator 12 b generates the discharge clock φb in response to the discharge timing signal BT supplied from the timing control circuit 13. This discharge clock φb is applied to the overflow drain region when the solid-state imaging device 11 has a horizontal overflow drain structure, and is applied to the substrate side of the solid-state imaging device 11 when it has a vertical overflow drain structure. For example, when the solid-state imaging device 11 has a vertical overflow drain structure, the substrate-side potential is temporarily raised to the high-potential side by the discharge clock φb, so that the information charges accumulated in the imaging unit 11i are solid. It is discharged to the substrate side of the image sensor 11.
[0019]
In response to the frame shift timing signal FT supplied from the timing control circuit 13, the F-clock generator 12f generates, for example, a four-phase frame transfer clock φf. The frame transfer clock φf is applied to the imaging unit 11i and is generated so as to be clocked in the blanking period of the vertical scanning period 1V as shown in FIG. As a result, information charges for one screen accumulated in the imaging unit 11i are output to the accumulation unit 11s at high speed. In the solid-state imaging device 11, a period L from when the discharge clock φb is raised to when the clocking of the frame transfer clock φf is started is an information charge accumulation period in the imaging unit 11i.
[0020]
The V-clock generator 12v generates, for example, a four-phase line transfer clock φv in response to the vertical synchronization signal VT and the horizontal synchronization signal HT supplied from the timing control circuit 13. The line transfer clock φv is applied to the accumulating unit 11s and is clocked at the same cycle as the frame transfer clock φf in a period corresponding to the frame transfer clock φf as shown in FIG. As a result, information charges for one screen output at high speed from the imaging unit 11i are sequentially taken into the storage unit 11s at the same speed. Further, as shown in FIG. 2, the line transfer clock φv is clocked at a period according to the horizontal synchronization signal HT in a period excluding a period for taking in information charges from the imaging unit 11i. As a result, the information charges stored in the storage unit 11s are sequentially output to the horizontal transfer unit 11h in units of one horizontal line every horizontal scanning period.
[0021]
In response to the horizontal synchronization signal HT supplied from the timing control circuit 13, the H-clock generator 12h generates, for example, a two-phase horizontal transfer clock φh. The horizontal transfer clock φh is applied to the horizontal transfer unit 11h, and the information charges taken in the horizontal transfer unit 11h are transferred in the horizontal direction. As shown in FIG. 2, the horizontal transfer clock φh is generated so as to be clocked within one horizontal scanning period, whereby information charges for one horizontal line are sequentially output in units of one pixel within one horizontal period. Is output to the unit 11d.
[0022]
The R-clock generator 12r generates a reset clock φr that is synchronized with the H-clock generator 12h. The reset clock φr is applied to the output unit 11d via the first frequency divider 13a, and resets the output unit 11d that repeats charging and discharging according to the information charges output from the horizontal transfer unit 11h. As shown in FIG. 3, the reset clock φr is normally set to a cycle that coincides with the horizontal transfer clock φh. For this reason, in the output unit 11d, a reset operation is performed every time information charge for one pixel is accumulated in the capacitor.
[0023]
The S-clock generator 12s generates the sampling clock φs based on the horizontal transfer clock φh. This sampling clock φs is applied to a sample hold circuit 15a, which will be described later, via the second frequency divider 14b, and samples the image signal Y0 (t) output from the output unit 11d. Usually, in the output unit 11d, the charge / discharge of the capacitor is repeated at the timing according to the reset clock φr, and therefore the image signal Y (t) alternately repeats the reset level and the signal level. Therefore, the phase of the sampling clock φs is set so that only the signal level is extracted from the image signal Y0 (t).
[0024]
The frequency divider circuit 13 includes a first frequency divider 13a that receives the reset clock φr and a second frequency divider 13b that receives the sampling clock φs. The first frequency divider 13a takes in the reset clock φr output from the R-clock generator 12r and divides the reset clock φr as necessary to generate a divided reset clock φr ′. The frequency-divided reset clock φr ′ is for intermittently resetting the output unit 11d. For example, as shown in FIG. 3, when the reset clock φr is divided by two and the period is set to double, the reset operation period of the output unit 11d is determined to be double. At this time, for example, when information charges obtained from odd rows of a plurality of light receiving pixels, that is, information charges indicating G component and R component are alternately accumulated in the horizontal transfer portion 11h, the output portion 11d In response to the horizontal transfer clock φh, information charge for one pixel (information charge indicating the G component) is accumulated in the capacitor. In response to this, a voltage value (image signal Y1 (t)) corresponding to the amount of information charges for one pixel indicating the G component is output from the output side of the output unit 11d. Normally, at this timing, the reset clock φr is applied to the output unit 11d and the potential on the output side of the output unit 11d is reset to the reset level. Here, however, the reset clock φr is divided by two. Therefore, the output side potential is not reset in the output unit 11d. Thereafter, the information charge for the next one pixel (information charge indicating the R component) is transferred from the horizontal transfer unit 11h to the output unit 11d, and the information charge for two pixels is accumulated in the capacity of the output unit 11d. Will be. Thereby, from the output side of the output unit 11d, although the voltage value corresponding to the information charge amount for one pixel (the charge amount of the information charge indicating the G component) is output, the information charge for two pixels is continuously output. A voltage value corresponding to the amount (the amount of information charges of the G component + R component) is output. Then, after the voltage value corresponding to two pixels is output, the reset operation is performed by the divided clock φr ′, and the potential on the output side of the output unit 11d is reset to the reset level. The above-described operation by the frequency division reset clock φr ′ is performed with all information charges of one horizontal line. As a result, from the output side of the output unit 11d, the information charges of the G component + R component are combined for two pixels. The output of the voltage value corresponding to is sequentially repeated. Note that these combining processes are performed in the same manner even when the even-numbered rows of the plurality of light receiving pixels, that is, the information charges indicating the B component and the G component are alternately accumulated in the horizontal transfer unit 11h. At this time, from the output side of the output unit 11d, voltage values corresponding to two pixels obtained by combining the information charges of the B component and the G component are sequentially output as the image signal Y1 (t).
[0025]
The second frequency divider 13b takes in the sampling clock φs output from the S-clock generator 12s and divides the sampling clock φs as necessary to generate a divided sampling clock φs ′. The frequency-divided sampling clock φs ′ is used to intermittently perform the sampling operation of the sample hold circuit 15a. For example, as shown in FIG. 3, when the sampling clock φs is divided by half and the period is set to double, the sampling period of the sample hold circuit 15a is set to double. This is performed in response to the period of the reset operation of the output unit 11d being doubled by the first frequency divider 13a. Therefore, sampling is performed at the timing when the image signal Y1 (t) corresponding to the information charges for two pixels is output from the output unit 11d, and the image signal Y2 (t) having image information for two pixels is extracted. Such a sampling operation is repeatedly performed each time a voltage value corresponding to the information charges for two pixels is output from the output unit 11d. As a result, in the sample and hold circuit 15a, the R component + G component, or The image signal Y2 (t) in which the image information of the B component + G component is combined is sequentially extracted.
[0026]
The frequency dividing operations of the first and second frequency dividers 13 a and 13 b are switched according to the exposure state of the solid-state imaging device 11. That is, when sufficient exposure is obtained in the imaging unit 11i, the frequency dividing operation is not performed, and the reset clock φr and the sampling clock φs are the same as those output from the R-clock generation unit 12r and the S-clock generation unit 12s. The signal is output to the output unit 11d while maintaining the cycle. On the contrary, in the imaging unit 11i, when the exposure is insufficient, a frequency dividing operation is performed, and the information charges are synthesized as described above. As described above, in the first and second frequency dividers 13 a and 13 b, the presence or absence of the information charge combining operation is switched according to the exposure state of the solid-state imaging device 11.
[0027]
The timing control circuit 14 includes a plurality of counters that count the reference clock CK. The timing control circuit 14 generates a vertical synchronization signal VT and a horizontal synchronization signal HT and also generates a frame timing signal FT. Further, the timing control circuit 14 generates the discharge timing signal BT based on the illuminance measured by the photometric sensor or the value calculated from the integrated value of the image data obtained by the digital signal processing circuit 17. These vertical synchronization signal VT, horizontal synchronization signal HT, frame timing signal FT and discharge clock φb are supplied to the drive circuit 12. Further, the timing control circuit 14 supplies control signals to the analog signal processing circuit 15, A / D conversion circuit 16 and digital signal processing circuit 17 other than the drive circuit 12, and the operation timing matching is achieved in these circuits. I am trying to do it.
[0028]
The analog signal processing circuit 15 includes a sample and hold circuit 15a, and performs analog signal processing such as CDS and AGC on the image signal Y1 (t) output from the solid-state imaging device 11. In the CDS, an image signal Y1 (t) that repeats a signal level and a reset level is taken into the sample hold circuit 15a, and the image signal Y1 (t) is sampled according to the sampling period determined by the divided sampling clock φs ′ to obtain the signal level. Take out only. Thereby, an image signal Y2 (t) having a continuous signal level is obtained. In the AGC, the image signal Y2 (t) extracted by the CDS is integrated in one screen or in units of one vertical scanning period, and gain feedback control is performed so that the integration data falls within a predetermined range.
[0029]
The A / D conversion circuit 16 takes the image signal Y2 (t) output from the analog signal processing circuit 15, converts it into a digital signal, and outputs it as image data Y0 (n). At this time, the A / D conversion circuit 16 normalizes the image signal Y2 (t) in accordance with the A / D conversion sampling clock SCK supplied from the timing control circuit 14, and as a result, as shown in FIG. Data having image information for two pixels of R component + G component is assigned to the data for pixels.
[0030]
The digital signal processing circuit 17 includes a luminance data generation circuit 17a, a color separation circuit 17b, a color data generation circuit 17c, and a selector 17d. The luminance data generation circuit 17a takes in the image data Y0 (n) output from the A / D conversion circuit 16, stores data for a plurality of lines in the line memory, and performs predetermined arithmetic processing on these data. Luminance data Y is generated. For example, for image data Y0 (n) having image information for two pixels of R component + G component or B component + G component, the nth (n is an integer) -th data (R component + G Component data), n + 1th data (R component + G component data), nth data (B component + G component data) and n + 1th data (B component + G component data) in even-numbered rows The image data for 4 pixels including is added, and the average value thereof is calculated as luminance data Y. The luminance data Y in this case does not coincide with the original luminance data, but there is no practical problem because the color components are synthesized at a rate close to the rate according to a predetermined standard.
[0031]
The color separation circuit 17b takes in the image data Y0 (n) output from the A / D conversion circuit 16, and from this image data Y0 (n), color component data R ′ (n), G ′ (n) for each color of RGB. ), B ′ (n) are separated and output. The image data Y0 (n) input to the color separation circuit 17b has continuous data having image information of G component + R component in the reading operation of odd rows, and has image information of B + G component in reading of even rows. Data is continuous. Therefore, in the color separation circuit 17b, data having image information of G component + R component is set as color component data R ′ (n) as data that approximately represents image information of R component, and image information of B component is approximated. As data represented by the above, data having image information of B component + G component is defined as color component data B ′ (n). Then, the data for one pixel having image information of R component + G component and the data for one pixel having image information of B component + G component are added, and an average value thereof (1 / 2R component + G component + 1 / 2B) Component) is calculated to generate color component data G ′ (n) that approximately represents the G component image information. The color separation circuit 17b has a built-in line memory similar to the luminance data generation circuit 17a. For example, when a line image signal Y0 (n) including image information of R component + G component is captured, Based on image information of another line stored in the line memory, color component data B ′ (n) and color component data G ′ (n) are interpolated by interpolating B component + G component image information that does not exist in the captured line. ) Is generated.
[0032]
The color data generation circuit 17c captures each color component data R ′ (n), B ′ (n), G ′ (n) output from the color separation circuit 17b and also captures the brightness data Y from the brightness data generation circuit 17a. The color difference signals U and V are generated. In the color data generation circuit 17c, the color difference signal U is generated by subtracting the luminance data Y from the color component data B ′ (n), and the color difference signal V is generated by subtracting the luminance data Y from the color component data R ′ (n). Generate. In the color data generation circuit 17c, not only the generated color difference signals U and V but also each color component data R ′ (n), B ′ (n), G ′ (n) fetched from the color separation circuit 17b is also the color difference. It is output simultaneously with the signals U and V. The selector 17d takes in each signal output from the luminance data generation circuit 17a and the color data generation circuit 17c, and selectively outputs them according to a request from the receiver side.
[0033]
The digital signal processing circuit 17b is provided with an exposure control circuit and a white balance control circuit (not shown) in addition to the above-described luminance data generation circuit 17a to selector 17d. For example, in the exposure control circuit, the expansion / contraction control of the information charge accumulation time is performed according to the exposure state of the solid-state imaging device 11, and the frequency dividing process in the frequency dividing circuit 14 is also switched. On the other hand, in the white balance control circuit, each color component data is multiplied by a unique gain coefficient to adjust each other's balance, thereby improving the color reproducibility of the reproduced image. Normally, in white balance control, each color component data is integrated in units of one screen or a plurality of screens, and feedback control is applied so that these integrated values are equal. In the white balance control, the color component data R ′ (n), B ′ (n), G ′ (n) generated by the color separation circuit 17b is used.
[0034]
The embodiment of the present invention has been described above with reference to FIGS. 1 to 3. According to the present invention, information charges indicating different color components are combined to obtain a combined image signal, and this combined image signal is approximated to a signal indicating R or B color components in the process of signal processing. By handling, even an imaging apparatus using a solid-state imaging device with a mosaic color filter mounted can improve the sensitivity while preventing an increase in cost. In other words, without changing the device structure of the solid-state imaging device itself, only the period of various clock pulses applied to the output unit and the sample-and-hold circuit is changed, and the information charges for a plurality of pixels are synthesized and the lack of image information Color imaging that compensates for the above can be performed. In the operation of the present invention, since information charges indicating mutually different color components are mixed, some deterioration in color reproducibility is unavoidable, but such deterioration in color reproducibility does not require high resolution, for example. If it is used in the monitor mode, it does not become a problem level. Rather, it is possible to obtain a sufficient effect in that it is effective for provision in a low price range due to prevention of an increase in cost due to no need to change the device structure.
[0035]
In the present embodiment, an image pickup apparatus using a frame transfer type solid-state image pickup device has been exemplified, but the present invention is not limited to this. For example, even an imaging apparatus using an interline type or frame interline type solid-state imaging device can be sufficiently applied.
[0036]
【The invention's effect】
According to the imaging apparatus of the present invention, in an imaging apparatus using a solid-state imaging device equipped with a mosaic type color filter, it is possible to improve sensitivity while preventing an increase in cost.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention.
FIG. 2 is a timing chart showing vertical scanning and horizontal scanning operations of the solid-state imaging device 11;
FIG. 3 is a timing chart showing the operation of the imaging apparatus of the present invention.
FIG. 4 is a block diagram illustrating a schematic configuration of a conventional imaging apparatus.
FIG. 5 is a schematic diagram illustrating a configuration of a mosaic type color filter.
[Explanation of symbols]
1, 11: Solid-state imaging device
2, 12: CCD driver
3, 15: Analog signal processing circuit
4, 16: A / D conversion circuit
5, 17: Digital signal processing circuit
6, 14: Timing control circuit
13: Frequency divider
13a: first frequency divider
13b: Second frequency divider
15a: Sample hold circuit
17a: Luminance data generation circuit
17b: Color separation circuit
17c: Color data generation circuit
17d: Selector

Claims (3)

A color filter is attached to the plurality of light receiving pixels arranged in a matrix, and a vertical transfer unit is connected to each column of the plurality of light receiving pixels, and each output of the vertical transfer unit is connected to each bit of the horizontal transfer unit. Furthermore, a solid-state imaging device having an output unit disposed on the output side of the horizontal transfer unit, and information charges accumulated in the plurality of light receiving pixels are taken into the plurality of vertical transfer units and transferred to the horizontal transfer unit side. Thereafter, the horizontal transfer unit transfers the output to the output unit side, the output unit obtains an output corresponding to the amount of accumulated charge, and resets the accumulated charge, and the image signal output from the solid-state imaging device. A signal processing circuit that performs predetermined signal processing on the output circuit, wherein the driving circuit sets the cycle of the reset operation of the output unit to an integral multiple of the cycle of the transfer operation of the horizontal transfer unit, and Information indicating two color components The charge is combined to generate a first combined image signal, and the information charges indicating the second and third color components are combined to generate a second combined image signal. A first color component signal that approximately represents the first color component from the first composite image signal is generated, and a third that approximately represents the third color component from the second composite image signal And a second color component signal that approximately represents the second color component from the first and second combined image signals. 2. The imaging device according to claim 1, wherein the solid-state imaging device has the first and second color components alternately arranged in even columns and odd columns in even rows, and even columns and odd columns in odd rows. An image pickup apparatus comprising: a color filter in which the second and third color components are alternately arranged. 3. The imaging device according to claim 1, wherein the first color component is a red component, the second color component is a green component, and the third color component is a blue component. There is an imaging apparatus.

Images