JP3968572B2 - Power converter with multiple inverters connected in parallel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power conversion device having a configuration in which a plurality of inverters are connected in parallel.
[0002]
[Prior art]
As one of the conventional parallel operation methods of inverters, the output voltage and output current of each inverter are detected, the active power is calculated based on this, the output frequency of the inverter is controlled by the calculated value of active power, There is a method of operating each inverter synchronously.
[0003]
[Problems to be solved by the invention]
However, this conventional method has the following drawbacks.
(1) It takes time to calculate the active power and the response characteristics are poor.
(2) Since the active power of the load or the active power of the cross current cannot be distinguished, the frequency changes depending on the load.
(3) The active power with respect to the frequency is determined by the constant of the main circuit of the inverter, and each inverter needs to be adjusted.
[0004]
SUMMARY OF THE INVENTION An object of the present invention is to provide a power conversion device that has a small time delay for detecting a phase difference between a plurality of inverters and can perform synchronous operation relatively easily.
[0005]
[Means for Solving the Problems]
In order to solve the above problems and achieve the above object, the present invention is connected to a plurality of inverter circuits each including a conversion switch for converting direct current to alternating current, and to the output terminals of the plurality of inverter circuits. A plurality of LC filters, a common output conductor for connecting output terminals of the plurality of LC filters in parallel to each other, and a common or a plurality of output voltage amplitude command means for giving amplitude command values of output voltages of the plurality of inverter circuits And a common or a plurality of frequency command means for providing a frequency command value of the output voltage of the plurality of inverter circuits, and a first and a second provided for forming a common phase signal of the plurality of inverter circuits Bias power supply for supplying a predetermined DC bias voltage between the common phase signal forming conductor and the first and second common phase signal forming conductors Single or plural common phase signals for detecting whether or not the first and second common phase signal forming conductors are electrically connected to each other and outputting the detection signal as a common phase signal A plurality of inverter circuits connected to the detection means, the output voltage amplitude command means, the frequency command means, the first and second common phase signal forming conductors, and the common phase signal detection means, respectively; A plurality of inverter control circuits for controlling the switch for conversion so that each of the plurality of inverter control circuits is connected to the frequency command means and the first input terminal A second input terminal for receiving a correction signal for performing a synchronous operation of a plurality of inverter circuits, and correcting the frequency command value by the correction signal to correct a correction frequency. Frequency command correcting means for forming a number command, and a sine wave generating means connected to the output voltage amplitude command means and the frequency command correction means for generating a sine wave signal in accordance with the output voltage amplitude command and the corrected frequency command A switch control signal forming means for forming a switch control signal for controlling the conversion switch of the inverter circuit so that an output voltage of the inverter circuit becomes a voltage commanded by the sine wave signal, and the sine A square wave generating means for generating a square wave signal synchronized with the wave signal, and being connected between the first and second common phase signal forming conductors and responding to the square wave generated from the square wave generating means Connected to the common phase signal forming switch means configured to be turned on, the square wave generating means and the common phase signal detecting means, and the square A phase difference between the wave signal and the common phase signal is detected, the correction signal is generated so as to correspond to the phase difference detection signal, and the correction signal is supplied to the second input terminal of the frequency command correction means. The present invention relates to a power converter characterized by having a phase difference detecting means.
[0006]
According to another aspect of the present invention, the common phase signal forming switch means is connected to the collector connected to the first common phase signal forming conductor and to the second common phase signal forming conductor. Preferably, it comprises a transistor or phototransistor having an emitter, and means for controlling the transistor or phototransistor in an on state in response to the square wave signal.
According to a third aspect of the present invention, the common phase signal detecting means outputs a phase inversion signal of a voltage between the first and second common phase signal forming conductors as the phase signal. It is desirable.
According to a fourth aspect of the present invention, the phase difference detection means is connected to the square wave generation means and the common phase signal detection means, and calculates a phase difference between the square wave signal and the common phase signal detection signal. A logic circuit that generates a pulse indicating the phase, and the pulse indicating the phase difference obtained from the logic circuit is converted into a voltage whose amplitude changes inversely or in proportion to the width of the pulse, and this is output as the correction signal And a pulse / voltage conversion circuit.
[0007]
【The invention's effect】
In the invention of each claim, it is common by the action of the square wave generating means synchronized with the sine wave including the frequency information of each inverter, the common phase signal forming switch means, and the first and second common phase signal forming conductors. A phase signal is formed, and a signal indicating a phase difference between the common phase signal and a square wave as its own phase signal is formed, thereby correcting the frequency command. Therefore, synchronous operation of a plurality of inverters can be achieved by a relatively simple method.
Further, in the present invention, it is unnecessary to calculate the active power by calculation as in the conventional method, so that the time delay in detecting the phase difference is reduced and the response characteristics of the parallel operation are improved.
Further, according to the present invention, the inverter can be operated synchronously regardless of the ratio between the load and the cross current of the active power, and the frequency change due to the load change can be reduced or eliminated.
[0008]
[First Embodiment]
Next, with reference to FIGS. 1-6, the power converter device which connected the some inverter which concerns on the 1st Embodiment of this invention in parallel is demonstrated.
[0009]
The power conversion device shown in FIG. 1 includes first and second inverter circuits 2a and 2b connected to DC power supplies 1a and 1b, and first and second inverter circuits 2a and 2b connected to output terminals. First and second filters 3a and 3b, first and second common output conductors 4 and 5 connected to output terminals of the first and second filters 3a and 3b, respectively, and first and second inverters The first and second control circuits 6a and 6b, the first and second common phase signal forming conductors 7 and 8, and the first and second inverter control circuits 6a and 6b are shown to be included in the first and second inverter control circuits 6a and 6b. DC bias voltage sources 9a and 9b and first and second current limiting resistors 10a and 10b are provided. A common load circuit (not shown) is connected to the first and second common output conductors 4 and 5. Accordingly, the first and second inverter circuits 2a and 2b are connected in parallel via the first and second filters 3a and 3b, and supply AC power to a common load circuit.
[0010]
Hereinafter, each part of FIG. 1 will be described in more detail. The first inverter comprising the first inverter circuit 2a, the first filter 3a, and the first inverter control circuit 6a, the second inverter circuit 2b, the second filter 3b, and the second inverter control circuit. Since the second inverter composed of 6b is configured identically, the same reference numerals are assigned to the common components, the first and second inverters are distinguished by the subscripts a and b, The first inverter will be described in detail, and the description of the second inverter will be omitted.
[0011]
As shown in FIG. 2, the first inverter circuit 2a for converting direct current into alternating current, that is, the direct current-alternating current circuit, includes first, second, third and fourth conversion switches Q1, Q2, Q3, Q4. It consists of a bridge circuit. The first to fourth conversion switches Q1 to Q4 are constituted by semiconductor switches such as IGBTs or transistors or FETs, for example. The first series circuit of the first and second conversion switches Q1, Q2 and the second series circuit of the third and fourth conversion switches Q3, Q4 are connected in parallel to the DC power source 1a. The line 11a as the first output terminal connected to the interconnection point of the first and second conversion switches Q1 and Q2 and the interconnection point of the third and fourth conversion switches Q3 and Q4 The line 12a as the second output terminal is connected to the first and second common output conductors 4 and 5 through the first filter 3a. In the first inverter circuit 2a, when the first and fourth conversion switches Q1, Q4 are simultaneously turned on, an output voltage in the first direction is obtained between the first and second output lines 11a, 12a. When the second and third conversion switches Q2 and Q3 are simultaneously turned on, an output voltage in the second direction is obtained between the first and second output lines 11a and 12a.
[0012]
The first filter 3a is an LC filter and includes an inductor 13a and a capacitor 14a. The inductor 13a is connected in series to the first output line 11a, and the capacitor 14a is connected in parallel between the first and second output lines 11a and 12a via the inductor 13a. The filter 3a removes high frequency components based on the on / off states of the conversion switches Q1 to Q4 of the inverter circuit 2a to create an approximate sine wave.
[0013]
As shown in FIG. 1, the first and second inverter control circuits 6a and 6b are roughly divided into first and second output voltage amplitude command means 15a and 15b, and first and second output frequency command means 16a. 16b, first and second frequency command correcting means 17a, 17b, first and second sine wave generating means 18a, 18b, first and second switch control signal forming means 19a, 19b, First and second square wave generating means 20a, 20b, first and second common phase signal forming switch means 21a, 21b, first and second common phase signal detecting means 22a, 22b, It comprises first and second phase difference detection means 23a, 23b, first and second bias power supplies 9a, 9b, and first and second current limiting resistors 10a, 10b. The first and second inverter control circuits 6a and 6b are formed identical to each other for unitization.
[0014]
The switch control signal forming means 19a is a switch for turning on / off the switches Q1 to Q4 of the inverter circuit 2a so that the output voltage of the inverter circuit 2a matches the sine wave signal generated from the sine wave generating means 18a, that is, the voltage command. Circuit means for forming a control signal, as shown in FIG. 2, an error signal forming means 24, a proportional-integral-derivative or PID device 25, a sawtooth generator 26, a comparator 27, and a NOT circuit 28 Consists of. The error signal forming means 24 and the PID device 25 may be collectively referred to as an error signal forming circuit or an error amplifier.
[0015]
The error signal forming means 24 has a first input terminal connected to the output terminal of the first filter 3a by a line 29a and a second input terminal connected to the sine wave generating means 18a by a line 30a. An error signal indicating a difference between the output voltage detection signal at the first input terminal and the sine wave signal at the second input terminal is output. A PID unit 25 connected to the error signal forming means 24 performs predetermined compensation on the error signal. Note that one input terminal of the error signal forming means 24 can be connected to the output line 11a of the inverter circuit 2a through the filter 31a as shown by a dotted line in FIG. In this case, the filter 31a is configured to remove a high frequency component from the output of the inverter circuit 2a in the same manner as the filter 3a.
[0016]
The sawtooth generator 26 has a repetition frequency (for example, 20 kHz) sufficiently higher than the frequency (for example, 50 Hz) of the AC voltage between the first and second output conductors 4 and 5, and the output signal of the PID unit 25. A sawtooth or triangular voltage having an amplitude level across
[0017]
The comparator 27 has one input terminal connected to the PID device 25 and the other input terminal connected to the sawtooth generator 26, and is obtained from the PID device 25 as shown in FIG. The compensated error signal Ve and the sawtooth signal Vt are compared, and the pulse width modulation output shown in FIG. 3B, which becomes high when the compensated error signal Ve is higher than the sawtooth signal Vt, is generated. The output of the comparator 27 is connected to the control terminals of the first and fourth conversion switches Q1 and Q4 via a well-known drive circuit not shown, and the NOT circuit 28 and the drive not shown. The control terminals of the second and third conversion switches Q2 and Q3 are connected through a circuit. The NOT circuit 28 inverts the phase of the output of the comparator 27 in FIG. 3B as shown in FIG. Note that it is desirable to provide a known dead time, that is, a pause period, between the pulse in FIG. 3B and the pulse in FIG. Further, the switch control forming means 19a is not limited to the circuit of FIG. 2, but forms a PWM pulse for causing the inverter output voltage to follow a sine wave signal as an output voltage command to generate first to fourth switches. Any circuit may be used as long as it can be supplied to the conversion switches Q1 to Q4. Further, in the embodiment of FIG. 1, these are configured identically in order to unitize the first and second inverters. Accordingly, the first and second switch control signal forming means 19a and 19b in FIG. 1 have the sawtooth generator 26 independently, but instead, one sawtooth generator 26 is provided for the first and second sawtooth generators 26. The switch control signal forming circuits 19a and 19b can be shared.
[0018]
The output voltage amplitude command means 15a in FIG. 2 generates a command value indicating the target output voltage amplitude of the inverter circuit 2a, and is connected to the sine wave generation means 18a by a line 32a.
[0019]
The frequency command generating means 16a generates a command value indicating a target frequency (for example, 50 Hz) of the output voltage of the inverter circuit 2a on the line 33a.
[0020]
The frequency command correction means 17a is composed of a subtractor or a synthesizer, and has a first input terminal connected to the frequency command line 33a and a second input terminal connected to the output line 34a of the phase difference detection means 23a. The correction value of the line 34a is subtracted from the frequency command of the line 33a, and the corrected frequency command is output to the line 35a. The subtraction in the correction means 17a is performed so as to synchronize the outputs of the first and second inverter circuits 2a and 2b.
[0021]
The sine wave generating means 18a is connected to the output voltage amplitude command line 32a and the corrected frequency command line 35a, has amplitude information corresponding to the output voltage amplitude command of the line 32a, and corresponds to the corrected frequency command of the line 35a. A sine wave signal having frequency information to be output is output to the line 30a. This sine wave signal indicates the target output voltage command of the inverter circuit 2a.
[0022]
The square wave generating means 20a is connected to the sine wave generating means 18a via a line 36a, and a square wave signal Va shown in FIG. 5 (A) synchronized with the sine wave signal generated from the sine wave generating means 18a is supplied to the line 37a. Output. The square wave generating means 20a of this embodiment is formed by a Xerox comparator, and shapes the sine wave signal into a square wave and outputs a square wave signal Va having a duty ratio of 50% shown in FIG. However, the square wave generating means 20a is not limited to this. For example, the square wave generating means 20a is connected to the output line 35a of the correcting means 17a, and the square wave signal Va is based on the corrected frequency command of the line 35a. Can be formed independently.
Since the square wave signal Va is a signal including phase information of the first inverter circuit 2a, that is, its own machine, it can also be called its own machine phase signal and has the same repetition frequency as that of the sine wave signal.
[0023]
The common phase signal forming switch means 21 a includes an NPN phototransistor 38 and a light emitting diode 39. The collector of the phototransistor 38 is connected to the first common phase signal forming conductor 7, and the emitter is connected to the second common phase signal forming conductor 8. A light emitting diode 39 as a means for controlling the phototransistor 38 to be turned on in response to the square wave signal is connected between the square wave signal line 37a and the ground, and is optically coupled to the phototransistor 38. When one or both of the first and second common phase signal forming switch means 21a and 21b for the first and second inverters are in the ON state, the first and second common phase signal forming conductors 7 are used. , 8 are electrically short-circuited, and during these periods, a low level, that is, a logic 0 state is obtained. When both the first and second common phase signal forming switch means 21a and 21b are simultaneously turned off, the first and second common phase signal forming conductors 7 and 8 are in a high level, that is, a logic one state. .
[0024]
In order to form a common phase signal, a first bias DC power supply 9a is connected between the first and second common phase signal forming conductors 7 and 8 via a first current limiting resistor 10a. In FIG. 1 and FIG. 2, the bias power source 9 is provided independently for the first and second inverter control circuits 6a and 6b.
[0025]
The common phase signal detection means 22a includes a light emitting diode 40, a phototransistor 41, a DC power source 42, and a current limiting resistor 43, and generates a common phase detection signal Vcom shown in FIG. The light emitting diode 40 is connected between the first and second common phase signal forming conductors 7 and 8, and emits light when the conductors 7 and 8 are at a high level. The collector of the phototransistor 41 optically coupled to the light emitting diode 40 is connected to the power supply 42 via the resistor 43, and the emitter is connected to the ground. A common phase signal output line 44 is connected to the collector of the phototransistor 41. The power source 42 can be omitted and the power source 9a can be shared.
During the light emission period of the light emitting diode 40, the phototransistor 41 is turned on, and the common phase detection signal Vcom on the line 44 is at a low level as shown in FIGS. Further, during the non-light emission period of the light emitting diode 40, the phototransistor 41 is turned off, and the common phase detection signal Vcom becomes a high level.
[0026]
FIGS. 5A and 5D show square wave signals Va and Vb as the own machine phase signals of the first and second inverters, and FIGS. 5B and 5E show the common phase detection signal Vcom. 5 (C) shows the phase difference between the first square wave signal Va in FIG. 5 (A) and the common phase detection signal Vcom in FIG. 4 (B), and FIG. 5 (F) shows the phase difference in FIG. 5 (D). 2 shows the phase difference between the square wave signal Vb of FIG. 2 and the common phase detection signal Vcom of FIG. 5E. FIG. 5G shows the voltage Vab between the first and second common phase signal forming conductors 7 and 8. Indicates.
The voltage Vab between the common phase signal forming conductors 7 and 8 shown in FIG. 5G and the common phase detection signal Vcom in FIGS. 5B and 5E are in opposite phases. That is, when at least one of the first and second common phase signal forming switch means 21a and 21b is in the ON state, the voltage Vab between the common phase signal forming conductors 7 and 8 becomes a low level, and conversely the common phase detection signal Vcom goes high.
[0027]
The phase difference detection means 23a is connected to the square wave generation means 20a by lines 45 and 37a, and is connected to the common phase signal detection means 22a by line 44, and the phase difference between the square wave signal Va and the common phase detection signal Vcom. And a signal indicating this phase difference is output as a frequency correction signal Vfc.
[0028]
FIG. 4 shows an example of the phase difference detecting means 23a of FIG. This phase difference detection means 23a is roughly composed of an exclusive OR circuit 46 as a phase difference pulse forming means and a pulse / voltage conversion circuit 47. One input terminal of the exclusive OR circuit 46 is connected to the square wave signal line 45, and the other input terminal is connected to the output line 44 of the common phase signal detecting means 22a. Therefore, as shown in FIG. 6D, the output Vpa of the exclusive OR circuit 46 has different levels of the square wave signal Va in FIG. 6A and the common phase detection signal Vcom in FIG. 6C. A phase difference pulse that is at a high level is generated in the periods t1 to t2 and t4 to t6. In FIG. 6, the common phase difference detection signal Vcom shown in FIG. 6C is shown to be different from that shown in FIG. 5B in order to show the change in the phase difference.
Instead of the exclusive OR circuit 46, another logic circuit capable of generating an output pulse equivalent to this can be used.
[0029]
The pulse / voltage conversion circuit 47 includes a first NOT circuit 48, first and second selection switches 49 and 50, a 90-degree delay circuit 51, a second NOT circuit 52, and a definite integration circuit 53. The definite integration circuit 53 includes an integrator 54 and a sample / hold circuit 55.
[0030]
The 90 degree delay circuit 51 is connected to the square wave signal line 45 and generates a 90 degree delayed signal Va90 of the square wave signal Va shown in FIG. 6A as shown in FIG. 6B. The period from t2 to t3 in FIG. 6 corresponds to a delay time of 90 degrees.
[0031]
The output terminal of the exclusive OR circuit 46 is connected to the integrator 54 via the first NOT circuit 48 and the first selection switch 49 and is connected to the integrator 54 via the second selection switch circuit 50. Yes. The first selection switch 49 has a control terminal connected to the delay circuit 51 and is turned on when the output signal of the delay circuit 51 is at a high level. The second selection switch 50 has a control terminal connected to the delay circuit 51 via the second NOT circuit 52, and is turned on when the output of the delay circuit 51 is at a low level. Therefore, the integrated input signal Vin shown in FIG. 6E is obtained on the common output line of the first and second selection switches 49, 50, that is, the input line of the integrator 54. The output Vpa obtained from the exclusive OR circuit 46 in FIG. 6D, that is, the width of the phase difference detection pulse, changes according to the change in phase. In FIG. 6, the width of the output Vpa during the period t4 to t6 is shown larger than the width of the output Vpa during the period t1 to t2. Accordingly, the integrator input signal Vin in FIG. 6E also changes.
[0032]
The integrator 54 integrates the integrator input signal Vin shown in FIG. 6E to generate the integrator output signal Vout shown in FIG. The integrator 54 is reset at the rising edge of the square wave signal Va on the line 45 and starts integrating again. When the integrator input signal Vin becomes low at t1 and t4 in FIG. 6, the integrator output signal Vout decreases with a slope due to discharge. The sample and hold circuit 55 connected to the integrator 54 samples the integrator output Vout of FIG. 6F in response to the rising edge of the square wave signal Va on line 45 shown at t2 and t6 in FIG. 6, and The frequency correction signal Vfc shown in FIG. 6G is sent to the line 34a. A smoothing filter can be connected to the output stage of the sample and hold circuit 55.
Further, the frequency correction means 17a of FIG. 1 can be constituted by an adder, and the frequency correction signal Vfc having a negative polarity can be generated from the phase difference detection means 23a.
[0033]
When the frequency correction signal Vfc changes as shown in FIG. 6G, the output of the frequency correction means 17a shown in FIGS. 1 and 2 also changes. As a result, the output frequency of the inverter circuit 2a also changes. Synchronous operation of the two inverters is achieved.
[0034]
As apparent from the above, this embodiment has the following effects.
(1) Since a common phase signal is formed, a phase difference between this common phase signal and a square wave indicating the phase of its own inverter is detected and used as a frequency correction signal, synchronous operation can be achieved relatively easily.
(2) Since the calculation of the active power required by the conventional method is not required, the time delay of the phase difference detection is reduced, and the response characteristics of the synchronous operation control are improved.
(3) Since the synchronous operation is controlled regardless of the active power, it is possible to prevent the fluctuation of the frequency due to the change of the load caused by the conventional method.
(4) Since the common phase signal is formed by using the common phase signal forming switch means 21a, 21b and the first and second common phase signal forming conductors 7, 8, the common phase signal is easily created. be able to.
(5) Since the phototransistor 38 and the light emitting diode 39 are used as the common phase signal forming switch means 21a, the common phase signal can be easily created by being electrically separated from the main circuit portion of the inverter control circuit 6a. be able to.
(6) Since the light emitting diode 40 and the phototransistor 41 are used as the common phase signal detection means 22a, the common phase signal can be easily detected by being electrically separated from the main circuit portion of the inverter control circuit 6a. it can.
(7) Since the phase difference detection means 23a is configured using a phase difference pulse forming circuit comprising an exclusive OR circuit 46 and a pulse / voltage conversion circuit comprising a definite integration circuit 53, the phase difference detection and frequency correction signal Formation can be easily achieved.
[0035]
[Second Embodiment]
Next, the power converter device of 2nd Embodiment is demonstrated with reference to FIG. 7 that are the same as those in FIG. 1 are assigned the same reference numerals, and descriptions thereof are omitted.
[0036]
The main circuit of the power conversion device in FIG. 7 is configured the same as in FIG. The switch control circuits 6a 'and 6b' in FIG. 7 are the same as the switch control circuits 6a and 6b in FIG. 1 in many parts, but are partially different. That is, in FIG. 7, instead of the first and second output voltage amplitude command means 15a and 15b of FIG. 1, a common output voltage amplitude command means 15 having the same function as these is provided, In place of the second frequency command means 16a and 16b, a common frequency command means 16 having the same function as these is provided, and instead of the first and second common phase signal detection means 22a and 22b. A common phase signal detecting means 22 having the same function as these is provided, and a common phase signal detecting means 22 having the same function is used instead of the first and second bias DC power supplies 9a and 9b and resistors 10a and 10b. The bias DC power source 9 and the resistor 10 are provided, and the other configurations are the same as those in FIG.
[0037]
More specifically, the common output voltage amplitude command means 15 is connected to the first and second sine wave generation means 18a and 18b by lines 32a and 32b, respectively. A common frequency command means 16 is connected to the first and second frequency command correction means 17a and 17b by lines 33a and 33b. The common phase signal detection means 22 is connected to the first and second phase difference detection means 23a, 23b by lines 44a, 44b.
[0038]
According to the second embodiment, in addition to the same effects as those of the first embodiment, output voltage amplitude command means 15, frequency command means 16, common phase signal detection for the first and second inverters. Since the means 22, the bias direct current power source 9, and the resistor 10 are provided in common, it is possible to obtain an effect that the size and the cost can be reduced by this amount.
[0039]
[Modification]
The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible.
(1) The inverter circuits 2a and 2b, the filters 3a and 3b, and the common output conductors 4 and 5 can be transformed into a known three-phase AC circuit.
(2) In FIGS. 1 and 7, the DC power supplies 1a and 1b of the first and second inverters are provided independently, but these can be used as a common power supply.
(3) The common phase signal forming switch means 21a and 21b are formed of bipolar transistors, which are connected between the conductors 7 and 8 instead of the phototransistor 38, and the base is connected to the square wave generating means 20a and 20b. Can do.
(4) The common phase signal detection means 22a and 22b can be formed of a circuit including a bipolar transistor. In this case, for example, the phototransistor 41 of FIG. 2 is a bipolar transistor, and a voltage between the conductors 7 and 8 is applied to the base of the bipolar transistor instead of the light emitting diode 4.
(5) Only one or more selected from the output voltage amplitude command means 15, frequency command means 16, common phase signal detection means 22, and bias DC voltage source 9 of FIG. The rest that has not been selected can be provided individually as in FIG. Alternatively, the output voltages of the first and second inverters may be detected at one place and shared.
(6) The present invention can also be applied when three or more inverters are connected in parallel.
(7) A part of the inverter control circuits 6a, 6b, 6a ', 6b' can be constituted by a digital circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a power conversion device according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing in detail a first inverter part of FIG. 1;
3 is a waveform diagram showing voltage states of respective parts of the switch control signal forming circuit of FIG. 2;
4 is a circuit diagram showing in detail an example of the phase difference detection means of FIG. 2;
FIG. 5 is a waveform diagram showing voltage states at various parts in FIG. 2;
6 is a waveform diagram showing voltage states at various parts in FIG. 4; FIG.
FIG. 7 is a block diagram illustrating a power conversion apparatus according to a second embodiment.
[Explanation of symbols]
1a, 1b First and second DC power supplies
2a, 2b first and second inverter circuits
3a, 3b first and second filters
4, 5 first and second common output conductors
6a, 6b first and second inverter control circuits
7, 8 First and second common phase signal forming conductors
9, 9a, 9b DC power supply for bias
10, 10a, 10b resistance
15, 15a, 15b Output voltage amplitude command means
16, 16a, 16b Frequency command means
17a, 17b First and second frequency command correction means
18a, 18b first and second sine wave generating means
19a, 19b First and second switch control signal forming means
20a, 20b first and second square wave generating means
21a, 21b First and second common phase signal forming switch means
22a, 22b First and second common phase signal detection means
23a, 23b First and second phase difference detection means

Claims (4)

A plurality of inverter circuits each including a conversion switch for converting direct current to alternating current;
A plurality of LC filters respectively connected to output terminals of the plurality of inverter circuits;
A common output conductor for connecting the output terminals of the plurality of LC filters in parallel with each other; a common or a plurality of output voltage amplitude command means for giving an amplitude command value of an output voltage of the plurality of inverter circuits;
A common or a plurality of frequency command means for giving a frequency command value of the output voltage of the plurality of inverter circuits;
First and second common phase signal forming conductors provided to form a common phase signal for the plurality of inverter circuits;
A bias power source for supplying a predetermined DC bias voltage between the first and second common phase signal forming conductors;
Single or multiple common phase signal detection that detects whether or not the first and second common phase signal forming conductors are electrically connected to each other and outputs the detection signal as a common phase signal Means,
The output voltage amplitude command means, the frequency command means, the first and second common phase signal forming conductors, and the common phase signal detection means are connected to each other, and the plurality of inverter circuits can be operated synchronously. A plurality of inverter control circuits for controlling the conversion switch,
Each of the plurality of inverter control circuits is
A first input terminal connected to the frequency command means and a second input terminal for receiving a correction signal for performing a synchronous operation of the plurality of inverter circuits; A frequency command correcting means for correcting by the correction frequency command to form a corrected frequency command;
A sine wave generating means connected to the output voltage amplitude command means and the frequency command correction means, for generating a sine wave signal according to the output voltage amplitude command and the correction frequency command;
Switch control signal forming means for forming a switch control signal for controlling the conversion switch of the inverter circuit so that an output voltage of the inverter circuit becomes a voltage commanded by the sine wave signal;
A square wave generating means for generating a square wave signal synchronized with the sine wave signal;
Common phase signal forming switch means connected between the first and second common phase signal forming conductors and configured to be turned on in response to the square wave generated from the square wave generating means. When,
Connected to the square wave generation means and the common phase signal detection means, detects a phase difference between the square wave signal and the common phase signal, and creates the correction signal to correspond to the phase difference detection signal. And a phase difference detecting means for supplying the correction signal to the second input terminal of the frequency command correcting means. The common phase signal forming switch means includes:
A transistor or phototransistor having a collector connected to the first common phase signal forming conductor and an emitter connected to the second common phase signal forming conductor;
2. The power converter according to claim 1, further comprising means for controlling the transistor or the phototransistor in an on state in response to the square wave signal. The said common phase signal detection means outputs the phase inversion signal of the voltage between the said 1st and 2nd common phase signal formation conductors as said phase signal. The power converter described. The phase difference detecting means includes
A logic circuit connected to the square wave generating means and the common phase signal detecting means, and generating a pulse indicating a phase difference between the square wave signal and the common phase signal detection signal, and the logic circuit obtained from the logic circuit 4. A pulse / voltage conversion circuit for converting a pulse indicating a phase difference into a voltage whose amplitude changes so as to be inversely proportional to or proportional to the width of the pulse, and outputting the voltage as the correction signal. The power converter described.

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